JPH08204993A - Frame memory device and video reproducing device - Google Patents

Abstract

PURPOSE: To read inputted video signals as they are by the use of a simple circuit. CONSTITUTION: At the time of the input of interlace signals, a flip-flop 34 is reset by reset signals from the flip-flop 42 and input side field discrimination signals to be inverted in synchronism with vertical synchronizing signals on an input side are generated from the flip-flop 34. At the time of the input of noninterlace signals, the reset signals are not outputted from the flip-flop 42, however, based on inversion signals from the flip-flop 32, the input side field discrimination signals to be inverted in synchronism with the vertical synchronizing signals on the input side are outputted from the flip-flop 34. Based on the input side field discrimination signals, video signals are written alternately for respective fields in a field memory 26 for even numbers and the field memory 28 for odd numbers. Even when the video signals are read with sychronizing signals for which interlace is performed as reference, the written video signals are read as they are.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory device and a video reproducing device, and more particularly to a frame memory device and a video reproducing device having a function of asynchronously operating input and output.

[0002]

2. Description of the Related Art Conventionally, when a composite video signal is stored in a frame memory, it is determined whether the composite video signal is an odd / even field and the video signal is stored in a memory of a different series for each field. There has been proposed a frame memory device for storing. The frame memory device 1 is configured as shown in FIG. 5, for example.

The frame memory device 1 includes a PLL circuit 2, and the PLL circuit 2 uses a system clock, for example, 910.
The frequency is divided to generate the HREF signal (FIG. 6 (b)). The system clock is the HREF signal and the horizontal sync signal (Fig. 6 (a)
) Is compared in phase by the phase comparison circuit 3 and is generated by passing through LPF 4 and VCO 5. Note that FIG.
As can be seen from the above, in the steady state, the horizontal synchronizing signal and the HREF signal are in phase with each other, and the duty of the HREF signal is 50%.

When this HREF signal is latched by the field discrimination signal generation circuit 6 by the vertical synchronizing signal (FIG. 6 (c)), an input side field discrimination signal is generated. The operation of the field discrimination signal generation circuit 6 is shown in FIG.
6A shows when the input video signal changes to the even field, and FIG. 6B shows when the input video signal changes to the odd field.

When the field discriminating signal is "L", it is an odd field, so the video signal is written in the odd field memory 7 by the field discriminating signal. Similarly, when the field discrimination signal is "H", it is an even field, so that the video signal is written in the even field memory 8 by the field discrimination signal. here,
FIG. 7A shows the timing when the video signal written in the field memory is asynchronously read. Figure 7
As shown in FIG. 7A, when the video signal is asynchronously read from the field memory, the video signal for each field (see FIG. 7 (c) is synchronized with the vertical synchronization signal (FIG. 7 (e)) which is the reference on the output side. ) And (d)) are read alternately, the video signals can be read from the field memory in the order in which they were written in the field memory (FIG. 7 (g)).

However, when the fields of the input signal cannot be discriminated, for example, when the input signal is a non-interlaced signal, the field discrimination signal generation circuit 6 does not invert the polarity for each field, and FIG. As shown in '), the field discrimination signal is fixed in the state of "H", and all the video signals are written in either one of the field memories (in this case, the even field memory).

When this is read out with reference to the interlaced sync signal, data is written every other field from the odd-numbered field memory which is not written on the input side. It becomes impossible to read all the video signals that have been recorded (X portion in FIG. 7 (g ')).

[0008]

In order to prevent this,
A circuit for checking in which field memory the input video signal is written and reading the video signal only from the written field memory is required on the output side. Therefore, there is a problem that the configuration of the frame memory device becomes complicated.

Therefore, a main object of the present invention is to provide a frame memory device and a video reproducing device which can read a video signal as it is with a simple structure.

[0010]

A first aspect of the present invention includes a first field memory and a second field memory, which determines whether an input video signal is an even field or an odd field and outputs the video signal as a first field. In the frame memory device for writing in the memory or the second field memory,
When a video signal for which the field cannot be identified is input,
A frame memory device comprising video signal writing means for alternately writing a video signal in a first field memory and a second field memory based on a vertical synchronizing signal.

A second aspect of the present invention includes a first field memory and a second field memory, and determines whether the input video signal is an even field or an odd field and outputs the video signal as a first field memory or a second field memory. And a video signal writing means for writing the video signal to the first field memory and the second field memory alternately based on the vertical synchronizing signal when the video signal whose field cannot be discriminated is input. The feature is a video reproducing apparatus.

[0012]

In the frame memory device or the video reproducing device having the function of operating the input and the output asynchronously, when the even / odd field of the input video signal can be discriminated, the video signal is sent to the first field according to the field. Write to memory or second field memory. On the other hand, when a video signal such as a non-interlaced signal whose field cannot be determined is input, the video signal writing means alternately writes the video signal in the first field memory and the second field memory based on the vertical synchronizing signal. . Non-interlaced signals include special reproduction signals such as still signals.

Even when the field cannot be discriminated in this way, the video signal is written alternately in the first field memory and the second field memory for each field.
Therefore, even if the video signal is read with reference to the interlaced synchronization signal, the written video signal can always be read as it is.

[0014]

According to the present invention, the written video signal can be read as it is with a simple structure. The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a frame memory device 10 of this embodiment has a function of asynchronously operating an input and an output. The frame memory device 10 includes a PLL circuit 12. The PLL circuit 12 includes a 1/455 frequency divider 14 and 1 /
Includes a divide-by-two frequency divider 16 and sets the system clock to, for example, 91.
The frequency is divided by 0 and the HREF signal is generated. The HREF signal and the horizontal synchronizing signal HD are compared in phase by the phase comparison circuit 18, and the phase comparison result is passed through the LPF 20 and the VCO 22 to generate the system clock.

The HREF signal is applied to the field discrimination signal generation circuit 24. Field discrimination signal generation circuit 24
Will be described in detail later. The input side field discrimination signal output from the field discrimination signal generation circuit 24 is input to the even field memory 26 and the odd field memory 28 of the frame memory 25. Even field memory 26 and odd field memory 28
A video signal is alternately written in each field according to the input side field discrimination signal. Then, in accordance with the output side field discrimination signal, the video signal is read alternately from the even field memory 26 and the odd field memory 28 for each field.

The operation of the field discriminating signal generating circuit 24 of the frame memory device 10 configured as described above will be described with reference to FIG.
Will be described with reference to. 2A shows the case where the input video signal is an interlaced signal, and FIG. 2B shows the case where the input video signal is a non-interlaced signal. Vertical sync signal separated from the composite video signal (Fig. 2 (c))
The system clock (Fig. 2 (b)
2) to obtain a synchronization signal (FIG. 2 (d)), the synchronization signal is delayed by another stage by the flip-flop 32 to obtain its inverted signal (FIG. 2 (k)). A flip-flop 34, which uses this inverted signal as a clock, outputs an input-side field discrimination signal (FIG. 2 (l)) that is inverted at each fall of the vertical synchronizing signal to the even field memory 26 and the odd field memory 28.

Further, the HREF signal (FIG. 2 (a)) from the PLL circuit 12 is applied to the flip-flop 36, and the flip-flop 3 is supplied with the synchronizing signal (FIG. 2 (d)) as a clock.
An inverted signal (FIG. 2 (e)) which is inverted every 6 fields is output. This inverted signal is applied to the NOR gate 38 and the flip-flop 40. The signal shown in FIG. 2 (f) is given from the flip-flop 40 to the NOR gate 38,
As a result, the signal shown in FIG. 2 (h) is obtained from the NOR gate 38. This signal is a signal having a falling edge 1 clock width of the inverted signal shown in FIG. And FIG.
The signal shown in (h) is applied to the flip-flop 42 and synchronized with the system clock to obtain the signal shown in FIG. 2 (i), and the flip-flop 34 is reset by the signal.

That is, the field discrimination signal generation circuit 2
4, the flip-flops 36 and 40, the NOR gate 3
8 and the reset signal output via the flip-flop 42, the input side field discrimination signal based on the field discrimination is obtained. Also, flip-flop 3
An input side field discrimination signal based on the vertical synchronizing signal is obtained by the inversion signal obtained through 0 and 32.

When the non-interlaced signal shown in FIG. 2B is input, the vertical synchronizing signal (FIG. 2 (b ')) is generated when the HREF signal is "H" (FIG. 2 (a')) in any field.
Is input, the output of the flip-flop 36 which receives the HREF signal at the timing of the vertical synchronizing signal remains "H" (FIG. 2 (e ')). But flip-flop 3
4 is a reset signal from the flip-flop 42 (see FIG.
(i ')) is not input, and the input side field discrimination signal is inverted for each field based on the inversion signal (FIG. 2 (k')) from the flip-flop 32 (FIG. 2).
(l ')).

Next, the access states of the even field memory 26 and the odd field memory 28 will be described with reference to FIG. Incidentally, FIG. 3 shows a conventional input side field discrimination signal for the convenience of comparison between this embodiment and the conventional. 3A shows the input of an interlaced signal, and FIG. 3B shows the input of a non-interlaced signal.

When the interlaced signal shown in FIG. 3 (A) is input, the vertical synchronizing signal on the input side is output for each field as shown in FIG. 3 (a), and the flip-flop 34 as shown in FIG. 3 (b). The reset signal to the is output once every two fields. Therefore, the input side field discrimination signal of this embodiment shown in FIG. 3 (d) is output in synchronization with the input side vertical synchronizing signal. At this time, the conventional input side field discrimination signal shown in FIG. 3C is also output in synchronization with the input side vertical synchronizing signal. As can be seen by comparing FIGS. 3 (c) and 3 (d), the conventional input side field discrimination signal and the input side field discrimination signal of this embodiment are equal, and the polarity is inverted for each field.

Therefore, in this embodiment, as in the conventional case,
The video signal of FIG. 3 (e) is written in the even field memory 26, and the odd field memory 28 of FIG. 3 (f) is written.
The video signal of is written. When this is read at the timing of the output side vertical sync signal shown in FIG. 3 (g), which is asynchronous with the input, the even field memory 26 and the odd number field memory 26 are read according to the output side field discrimination signal shown in FIG. 3 (h). The video signal shown in FIG. 3 (i) is alternately read from the field memory 28 for each field.

On the other hand, when the non-interlaced signal shown in FIG. 3B is input, the reset signal is not output as shown in FIG. 3B '. Therefore, the conventional input side field discrimination shown in FIG. 3C' is performed. Although the signal is fixed to "H", the input side field discrimination signal in this embodiment is based on the input side vertical synchronizing signal (Fig. 3 (a ')) as shown in Fig. 3 (d'). The polarity is inverted every time.

As a result, in this embodiment, the video signal of FIG. 3 (e ') is written in the even field memory 26,
The video signal shown in FIG. 3 (f ') is written in the odd-numbered field memory 28. This writing order is shown in FIGS. 3 (e ') and (f'). If this is read at the timing of the output side vertical sync signal shown in FIG. 3 (g '), which is asynchronous with the input,
In response to the output-side field discrimination signal shown in FIG. 3 (h '), the even-numbered field memory 26 and the odd-numbered field memory 28 alternately output video signals for each field. The video signals are output in the order of input as shown in FIG.

By generating the input side field discrimination signal from the flip-flop 34 based on the reset signal output from the flip-flop 42, the reading order from the even field memory 26 and the odd field memory 28 is erroneous. Instead, the video signals can be read in the order in which they were written. It is also effective to use this input-side field discrimination signal to generate a still signal from the memory. That is, if the frame memory device has a structure in which the still image is applied only in a specific (even or odd) field, in the conventional case, still image cannot be obtained in one side field at the time of non-interlaced input. Since the field discrimination signal on the input side is inverted for each vertical synchronizing signal, it becomes possible to easily apply still in field units even at the time of non-interlaced input.

Therefore, according to this embodiment, in the frame memory device in which the input and the output operate asynchronously, when the input video signal is written by switching the memory system for each field, the video signal is interlaced. Signal or non-interlaced signal, and if it is a non-interlaced signal, the output side does not judge which field (even field or odd field) is written to the memory, and if the video signal is read out, it is input It can be output in the order in which it was done.

Further, instead of the field discrimination signal generation circuit 24 shown in FIG. 1, a field discrimination signal generation circuit 24 'shown in FIG. 4 may be used. The field discrimination signal generating circuit 24 'is obtained by omitting the NOR gate 38 of the field discrimination signal generating circuit 24 and adding an OR gate 44 and an AND gate 46. The other configurations are the same as those of the field discrimination signal generating circuit 24. Therefore, duplicate description will be omitted.

In the field discrimination signal generating circuit 24 ',
Instead of directly resetting the flip-flop 34 by the reset signal from the flip-flop 42, an inverted signal output from the flip-flop 32 (FIG. 2 (k))
The AND gate 46 generates a reset signal (FIG. 2 (j)) such that the synchronous reset is applied. 2 (g) shows the output from the OR gate 44.

Even when the frame memory device 10 is constructed by using the field discrimination signal generating circuit 24 ', FIG.
The same effect as the embodiment shown in can be obtained. The present invention can also be applied to a teletext decoder. Although the frame memory device 10 has been described in the above embodiment, the present invention can be applied to a video reproducing device including the frame memory device 10, and in that case, the same effect as that of the frame memory device 10 can be obtained. There is no end.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2A is a timing chart showing a field discrimination signal generation timing at the time of inputting an interlaced signal and FIG. 2B at the time of inputting a non-interlaced signal.

FIG. 3A is a timing diagram showing a memory access state at the time of inputting an interlaced signal and FIG. 3B at the time of inputting a non-interlaced signal.

FIG. 4 is a circuit diagram showing a modified example of a field discrimination signal generation circuit.

FIG. 5 is a block diagram showing a conventional technique.

FIG. 6 is a timing diagram showing a conventional field discrimination signal generation timing.

FIG. 7A is a timing diagram showing a conventional memory access state when an interlaced signal is input, and FIG. 7B is a non-interlaced signal input.

[Explanation of symbols]

10 ... Frame memory device 12 ... PLL circuit 24, 24 '... Field discrimination signal generation circuit 25 ... Frame memory 26 ... Even field memory 28 ... Odd field memory 30, 32, 34, 36, 40, 42 ... Flip-flop 38 ... NOR gate 44 ... OR gate 46 ... AND gate

Claims (2)

[Claims] 1. A first field memory and a second field memory are included, and it is determined whether an input video signal is an even field or an odd field, and the video signal is stored in the first field memory or the second field memory. In the frame memory device to write, when a video signal whose field cannot be identified is input,
A frame memory device comprising video signal writing means for alternately writing the video signal in the first field memory and the second field memory based on a vertical synchronization signal. 2. A first field memory and a second field memory are included, and whether the input video signal is an even field or an odd field is discriminated and the video signal is stored in the first field memory or the second field memory. When a video signal for which the field cannot be identified is input in the video playback device to be written,
A video reproducing apparatus comprising video signal writing means for alternately writing the video signal in the first field memory and the second field memory based on a vertical synchronizing signal.