JPH09270937A - Vertical synchronization circuit and timing controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vertical synchronization circuit in which an output image is made stable under an unstable synchronization input state. SOLUTION: A decoder 22 of a vertical synchronizing circuit 9 generates and outputs phase comparison signals PA, PB, corresponding to a lock in period of a vertical synchronizing signal and an internal vertical synchronizing signal MVSYNC corresponding to the vertical synchronizing signal VSYNC based on a count of a counter 21. A discrimination section 24 decides a state of the vertical synchronizing signal VSYNC, based on the received phase comparison signals PA, PB and outputs an open signal SO or a close signal SC to a selection section 26, based on the result of decision. The selection section 26 selects the vertical synchronizing signal VSYNC or the internal vertical synchronizing signal MVSYNC based on the open signal SO, and the close signal SC and outputs a clear signal VCLR to clear the counter 21 based on the selected signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical synchronizing circuit and a timing controller.

[0002]

2. Description of the Related Art FIG. 11 is a circuit diagram of a conventional vertical synchronizing circuit 71. The vertical synchronization circuit 71 includes a counter 72, a decoder 73, JK flip-flops (hereinafter referred to as JKFF) 74 and 75, D flip-flops (hereinafter referred to as DFF) 76, AND circuits 77 and 78, an OR circuit 79, and an inverter circuit. It is composed of 80.

The vertical synchronizing circuit 71 is supplied with a vertical synchronizing signal VSYNC which is synchronously separated from the composite video signal. Further, the vertical synchronizing circuit 71 is supplied with the clock signal CLK generated based on the horizontal synchronizing signal which is synchronously separated from the composite video signal by the horizontal synchronizing circuit.

The counter 72 clears its count value based on a clear signal VCLR generated based on the vertical synchronizing signal VSYNC. Then, the counter 72 counts the clock signal CLK and outputs the count value to the decoder 73.
Output to The decoder 73, based on the count value,
The signals S1 and S2 are output during a predetermined period. For example, the signal S1 is output when the period is "20H" (H is one horizontal scanning period and is two clocks of the clock signal CLK), and the signal S2 is output when "22H". The signals S1 and S2 are output to the input terminals J and K of the JKFF 74, respectively, and the JKFF 74 outputs a one-pulse control signal STV based on the signals S1 and S2.

That is, the vertical synchronizing circuit 71 is configured to detect the vertical synchronizing signal.
A control signal STV is generated based on VSYNC and a clock signal CLK and output to a display device such as an LCD. The indicator is
By starting the vertical scanning based on the control signal STV, the display timing of the image is adjusted to display a complete image.

Further, the vertical synchronizing circuit 71, as shown in FIG. 12, provides a pull-in period at a planned input position of the vertical synchronizing signal VSYNC. During the pull-in period, the decoder 73
It is set based on the signal output from. Decoder 7
3 outputs a signal S3 when the period is "224H" and a signal S4 when the period is "296H" based on the count value from the counter 72 which counts the clock signal CLK.
Vertical sync signal VSYN is applied during periods "224H" and "296H".
In the case of the NTSC system, since C is repeatedly input at approximately "262.5H", it is set to be before and after the planned input position of the vertical synchronizing signal VSYNC.

The signal S3 is input to the input terminal J of the JKFF 75, and the JKFF 75 outputs H based on the signal S3.
A level signal is output from the output terminal Q to the AND circuit 77. The AND circuit 77 outputs the vertical synchronizing signal VSYNC based on the signal output from the output terminal Q of the JKFF 75 when the signal is at the H level, and outputs the vertical synchronizing signal VSYNC.
Based on JKFF75, DFF76, AND circuit 7
A clear signal VCLR of 1 pulse is generated and output by 8.

That is, the vertical synchronizing circuit 71 allows the input of the vertical synchronizing signal VSYNC during the pull-in period and generates the clear signal VCLR based on the vertical synchronizing signal. Conversely,
The vertical synchronization circuit 71 uses the vertical synchronization signal outside the pull-in period.
Do not allow VSYNC input. Therefore, the vertical synchronization circuit 71
Prevents the clear signal VCLR from being generated due to noise or the like input outside the pull-in period, and improves noise resistance. Further, the vertical synchronizing circuit 71 sets the width of the pull-in period appropriately so that the output image is vertically synchronized even if the vertical synchronizing signal VSYNC is deviated.

In practice, the counter 72 clears the count value by the clear signal VCLR. Therefore, when the vertical synchronizing signal VSYNC is normally input, when the decoder 73 outputs "296H" based on the count value. Signal S
4 is not output.

[0010]

By the way, when the input state of the video signal becomes unstable due to deterioration of the propagation state of the radio wave or ghost, noise is mixed in during the pull-in period and the level of the vertical synchronizing signal VSYNC is lowered. Then, it may be easily dropped. The mixed noise causes jitter, and the output image fluctuates in the vertical direction, which makes it difficult to see.

If the vertical synchronizing signal VSYNC is missing,
As shown in FIG. 13, the vertical synchronizing circuit 71 outputs the clear signal VC.
LR is generated based on the signal S4 which is the end of the pull-in period. As a result, the display starts vertical scanning at a cycle of "296H" and displays an image. However, since the image for one field is sent at an interval of "262.5H", the image and the start of vertical scanning are sequentially shifted.
Since this is a so-called synchronous flow state, as shown in FIG.
There is a problem that the output image displayed on the display unit 81 cannot be confirmed in detail, and becomes very difficult.

The present invention has been made to solve the above problems, and an object thereof is to provide a vertical synchronizing circuit and a timing controller capable of stabilizing an output image in an unstable synchronous input state. To provide.

[0013]

According to a first aspect of the present invention, there is provided a counter for counting a clock signal generated based on a horizontal synchronizing signal, and an output image is timed based on the count value of the counter. A control signal is generated and output, and a pull-in period is provided before and after the planned input position of the vertical sync signal, the vertical sync signal input within the pull-in period is validated, and a clear signal is generated based on the vertical sync signal. A vertical synchronizing circuit that generates and clears the count value of the counter, generates an internal vertical synchronizing signal corresponding to the vertical synchronizing signal, generates a clear signal using the internal vertical synchronizing signal, and clears the counter. Then, the state of the vertical synchronization signal is determined, and if the vertical synchronization signal is stably input based on the determination result, the vertical synchronization signal is detected. And summarized in that which is adapted to generate the clear signal by selecting the signal.

According to a second aspect of the present invention, in the vertical synchronizing circuit according to the first aspect, an internal vertical synchronizing signal corresponding to the vertical synchronizing signal is generated, and one field is placed in the pull-in period and outside the pull-in period. Of the two vertical periods, determine the state of the vertical synchronizing signal based on the periods, select the internal vertical synchronizing signal or the vertical synchronizing signal based on the determination result, and select the selected internal vertical synchronizing signal or the vertical synchronizing signal. The gist is that a clear signal is generated based on the synchronization signal to clear the counter.

According to a third aspect of the present invention, a counter for counting clock signals generated based on the horizontal synchronizing signal is provided, and a control signal for timing the output image is generated based on the count value of the counter. The output of the counter is provided with a pull-in period before and after the planned input position of the vertical sync signal, the vertical sync signal input within the pull-in period is validated, and a clear signal is generated based on the vertical sync signal to generate a clear signal. A vertical synchronization circuit configured to clear a count value, based on the count value of the counter, generating phase comparison signals before and after a planned input position of the vertical synchronization signal corresponding to the pull-in period of the vertical synchronization signal. An internal vertical synchronization signal corresponding to the vertical synchronization signal is generated based on the count value of the decoder of No. 1 and the counter. The second decoder and the phase comparison signal generated by the first decoder are input, and based on the phase comparison signal, one field is divided into two periods, a pull-in period and a pull-out period, and based on those periods. A determination circuit for determining whether the state of the vertical synchronization signal is stable and outputting a determination signal according to the determination result, and the determination circuit for inputting the vertical synchronization signal and the internal vertical synchronization signal. Input the decision signal output from the, if the vertical synchronization signal is stable based on the determination signal, select the vertical synchronization signal, if the vertical synchronization signal is not stable, the internal vertical synchronization signal The gist is that a selection circuit that selects and outputs a clear signal based on the selected signal is provided.

According to a fourth aspect of the present invention, in the vertical synchronizing circuit according to the third aspect, the determination circuit outputs the determination signal when the vertical synchronization signal is stably input in a plurality of fields. The summary is what you did.

The invention according to claim 5 is the invention according to claim 3 or 4.
In the vertical synchronization circuit according to claim 1, the determination circuit counts up based on the vertical synchronization signal, a counter that counts down based on the phase comparison signal, a count value of the counter, and based on the phase comparison signal. One pulse is input within the pull-in period based on the set pull-in period and outside the pull-in period, and
Vertical sync signal when the number of pulses input outside the pull-in period is 0, or when the number of pulses input during the pull-in period is 0 and the number of pulses input outside the pull-in period is 1 Is determined to be stable, and a phase determination circuit that outputs the determination result is provided.

According to a sixth aspect of the present invention, in the vertical synchronizing circuit according to the fifth aspect, the determination circuit further counts the determination result output from the phase determination circuit, and the count value is a predetermined value. It is a gist to provide a counter that outputs the determination signal when the value exceeds.

According to a seventh aspect of the present invention, a horizontal synchronizing circuit for generating and outputting a control signal for timing an output image and a clock signal based on the horizontal synchronizing signal,
The gist is that the vertical synchronization circuit according to any one of claims 1 to 6 is provided.

Therefore, according to the invention of claim 1,
An internal vertical sync signal corresponding to the vertical sync signal is generated,
A clear signal is generated using the internal vertical sync signal to clear the counter. Further, the state of the vertical synchronization signal is determined, and based on the determination result, when the vertical synchronization signal is stably input, the vertical synchronization signal is selected and the clear signal is generated.

According to the second aspect of the present invention, the internal vertical synchronizing signal corresponding to the vertical synchronizing signal is generated, and one field is divided into two periods, that is, within the pull-in period and outside the pull-in period. The state of the vertical synchronization signal is determined based on the period, the internal vertical synchronization signal or the vertical synchronization signal is selected based on the determination result, and the clear signal is generated based on the selected internal vertical synchronization signal or the vertical synchronization signal. Counter is cleared.

According to the third aspect of the invention, the first phase comparison signal is generated based on the count value of the counter before and after the planned input position of the vertical synchronization signal in correspondence with the pull-in period of the vertical synchronization signal. And a second decoder that generates an internal vertical synchronization signal corresponding to the vertical synchronization signal based on the count value of the counter, and the phase comparison signal generated by the first decoder are input to the phase comparison signal. 1 field is divided into two periods, that is, within the pull-in period and outside the pull-in period, based on these periods, it is determined whether or not the state of the vertical synchronizing signal is stable, and a determination signal according to the determination result. Inputting the vertical synchronizing signal and the internal vertical synchronizing signal, and inputting the determination signal output from the determining circuit. And a vertical sync signal is selected, an internal vertical sync signal is selected when the vertical sync signal is not stable, and a clear circuit is output based on the selected signal. .

According to the fourth aspect of the present invention, the determination signal is output when the vertical synchronizing signal is stably input in a plurality of fields. According to the invention of claim 5, the determination circuit counts up based on the vertical synchronization signal,
A counter that counts down based on the phase comparison signal, a count value of the counter, and one pulse input within the pull-in period based on the pull-in period and the outside of the pull-in period set based on the phase comparison signal, and ,
Vertical sync signal when the number of pulses input outside the pull-in period is 0, or when the number of pulses input during the pull-in period is 0 and the number of pulses input outside the pull-in period is 1 Is determined to be stable, and a phase determination circuit that outputs the determination result is provided.

According to the sixth aspect of the invention, the determination circuit further counts the determination result output from the phase determination circuit, and outputs a determination signal when the count value exceeds a predetermined value. A counter is provided.

According to the invention described in claim 7, a horizontal synchronizing circuit for generating and outputting a control signal for timing an output image and a clock signal based on the horizontal synchronizing signal, The gist is that the vertical synchronization circuit according to any one of 6 is provided.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block circuit diagram of the image display device 1. The image display device 1 is
It is composed of a drive circuit unit 2 and a liquid crystal display module 3.

The drive circuit section 2 includes a sync separation circuit 4, a timing controller 5, a voltage controlled oscillator circuit (VCO) 6,
And a video signal processing circuit 7. A video signal is input to the sync separation circuit 4 from the outside.
The sync separation circuit 4 converts the video signal from the horizontal sync signal HSYNC.
The vertical sync signal VSYNC is separated, and the separated horizontal sync signal HSYNC and vertical sync signal VSYNC are output to the timing controller 5.

The timing controller 5 is provided with a horizontal synchronizing circuit 8 and a vertical synchronizing circuit 9. A horizontal synchronizing signal HSYNC is input to the horizontal synchronizing circuit 8. The horizontal synchronizing circuit 8 generates a control signal for controlling the start of horizontal scanning based on the horizontal synchronizing signal HSYNC and outputs it to the liquid crystal display module 3. Further, the horizontal synchronizing circuit 8 is a VCO.
A PLL (Phase Locked Loop) is configured with 6 and a clock signal CL having a predetermined frequency based on the horizontal synchronization signal HSYNC.
K is generated and output to the vertical synchronizing circuit 9. The vertical synchronizing circuit 9 generates a control signal for controlling the start of vertical scanning based on the vertical synchronizing signal VSYNC and the clock signal CLK input from the horizontal synchronizing circuit 8, and outputs the control signal to the liquid crystal display module 3.

The video signal processing circuit 7 amplifies the image signal. Further, although not shown in the figure, the polarity inversion signal FRP is input to the video signal processing circuit 7. The video signal processing circuit 7 operates in synchronization with the polarity inversion signal FRP, converts the amplified image signal into a waveform necessary for driving the liquid crystal display module 3, and outputs the image signal Vd as the image signal Vd.
Output to

The liquid crystal display module 3 includes the liquid crystal panel 1
0, a horizontal drive circuit 11, and a vertical drive circuit 12. The control signal generated by the horizontal synchronizing circuit 8 is input to the horizontal drive circuit 11, and
The image signal processed by the video signal processing circuit 7 is input. The control signal generated by the vertical synchronizing circuit 9 is input to the vertical drive circuit 12. Horizontal drive circuit 1
1. The vertical drive circuit 12 starts horizontal scanning and vertical scanning based on control signals, respectively, and the liquid crystal panel 1 outputs an image signal whose image signal is complete by the horizontal scanning and vertical scanning.
Displayed as 0.

As shown in FIG. 2, the vertical synchronizing circuit 9 includes:
A counter 21 is provided. The clock signal CLK is input to the counter 21. The counter 21 counts the clock signal CLK and outputs the count value to the decoder 22.
Output to Based on the count value input from the counter 21, the decoder 22 outputs the pulse signals S1 and S2 to JK when the count value matches a preset value.
The data is output to a flip-flop (hereinafter referred to as JKFF) 23.

The JKFF 23 generates, for example, a 1-pulse control signal STV based on the pulse signals S1 and S2 and outputs it to the liquid crystal display module 3. Liquid crystal display module 3
When the control signal STV is input, the scanner starts scanning based on the control signal STV and displays an image.

In the present embodiment, the decoder 22 is
The count value of the counter 21 is “20H” (1H = 1 horizontal scanning period, which corresponds to 2 clocks of the clock signal CLK)
The pulse signal S1 is generated and output when the count value is a value corresponding to "22H", and the pulse signal S2 is generated and output. These count values "2
"0H" and "22H" correspond to the timing for starting vertical scanning based on the composite video signal of the NTSC system.

Further, the decoder 22 is adapted to generate and output the phase comparison signals PA and PB based on the count value from the counter 21. The phase comparison signal PA,
PB is before and after the planned input position of the vertical synchronization signal VSYNC and corresponds to the pull-in period.
Indicates the start position of the pull-in period, and the phase comparison signal PB corresponds to the end position of the pull-in period.

For example, the decoder 22 generates the phase comparison signal PA when the count value is "447" and the phase comparison signal PB when the count value is "68". The counter 21 clears the count value when a clear signal VCLR described later is input. The clear signal VCLR is generated based on the vertical synchronizing signal VSYNC or the internal vertical synchronizing signal MVSYNC. That is, the counter 21 clears the count value every time the vertical synchronizing signal VSYNC or the internal vertical synchronizing signal MVSYNC is input. Therefore, the decoder 22 uses the counter 2
After the phase comparison signal PB corresponding to the end position of the pull-in period is output based on the count value of 1, the phase comparison signal PA corresponding to the start position of the next pull-in period is output.

Further, the decoder 22 corresponds to the expected input position of the vertical synchronizing signal VSYNC based on the count value from the counter 21 and corresponds to the cycle of one field.
The internal vertical synchronizing signal MVSYNC is generated and output corresponding to one vertical scanning period (= 1 V) of the NTSC system. Since the vertical synchronization signal VSYNC is input at about “262.5H”, the decoder 22 determines that the value corresponding to “262.5H”, that is, the vertical synchronization signal VSYNC, based on the count value of the counter 21. To generate and output an internal vertical synchronization signal MVSYNC.

Further, the vertical synchronizing circuit 9 includes a judging section 24,
A signal processing unit 25 and a selection unit 26 are provided.
The judging section 24 is provided for judging the state of the vertical synchronizing signal VSYNC. The status of the vertical sync signal VSYNC is
The input is normal, the input is out of phase, there is no input, noise is mixed, etc.

The clock signal CLK, the vertical synchronizing signal VSYNC, and the phase comparison signals PA and PB are input to the judging section 24. The determination unit 24 operates in synchronization with the clock signal CLK and divides one field into two periods, a pull-in period and a pull-out period, based on the phase comparison signals PA and PB. During the period, it is determined whether or not the vertical synchronizing signal VSYNC is input. Then, the determination unit 24 generates the open signal SO and the close signal SC based on the determination result, and outputs the open signal SO to the signal processing unit 25 and the open signal SO and the close signal SC to the selection unit 26. Has become.

As shown in FIG. 6, the signal processing section 25 includes AND circuits 65 and 66, a JKFF 67, and a DFF 68.
It consists of. The vertical synchronizing signal VSYNC is input to the AND circuit 65, and the output terminal is connected to the input terminal K of the JKFF 67. The open signal SO is input to the input terminal J of the JKFF 67 from the determination unit 24, and the clock signal CLK is input to the clock input terminal. JKF
The output terminal Q of F67 and the input terminal of the AND circuit 65 are
It is connected to the input terminal D of the DFF 68, and the inverting output terminal QN
Is connected to one input terminal of the AND circuit 66, and the other input terminal of the AND circuit 66 is connected to the output terminal Q of the DFF 68.
It is connected to the. The clock signal CLK is input to the clock input terminal of the DFF 68.

When the open signal SO is input, the signal processing section 25 enters a standby state, validating only the first input signal and invalidating the next input signal.
The signal processing unit 25 operates in synchronization with the clock signal CLK, processes the validated signal into a width corresponding to one cycle of the clock signal CLK, and outputs the processed signal to the selection unit 26.

For example, the signal processing unit 25 sets the vertical synchronizing signal VS after the standby state in which the open signal SO is input.
When noise is input following YNC, the vertical sync signal VSYNC input first is valid, and the noise input next is invalid. With this configuration, the counter 2 is affected by noise input after the vertical synchronization signal VSYNC.
It is possible to prevent an erroneous operation in which 1 is cleared and to eliminate vertical movement of the output image.

The vertical synchronizing signal VSYNC is input to the selecting unit 26 via the signal processing unit 25, and the internal vertical synchronizing signal MVSYNC is input from the decoder 22. In addition, the selection unit 26 includes an open signal SO and a close signal S from the determination unit 24.
C is input. The selection unit 26 outputs the clear signal VCLR based on the internal vertical synchronization signal MVSYNC, for example. Then, when the open signal SO is input from the determination unit 24, the selection unit 26 selects the vertical synchronization signal VSYNC and outputs the clear signal VCLR based on the selected vertical synchronization signal VSYNC. In addition, the selector 26 outputs the clear signal VCLR based on the vertical synchronizing signal VSYNC during the operation of closing the signal S
When C is input, the internal vertical sync signal MVSYNC is selected, and a clear signal is output based on the selected internal vertical sync signal MVSYNC.
The operation switches to outputting VCLR.

The open signal SO is a vertical synchronizing signal VSYNC.
Is output when the input is stable and the close signal S
C is output when the vertical synchronizing signal VSYNC is not stable (noise is mixed, the vertical synchronizing signal VSYNC is not input). When the open signal SO is input, the selection unit 26 selects the vertical synchronization signal VSYNC and closes the signal SC.
Is input, the internal vertical sync signal MVSYNC is selected.

That is, the selection unit 26 has a vertical synchronization signal VSYNC.
Is input stably, the vertical sync signal VSYNC
And outputs the clear signal VCLR based on the vertical synchronizing signal VSYNC. On the other hand, the selection unit 26 controls the vertical synchronization signal.
When VSYNC is not stably input, the internal vertical synchronizing signal MVSYNC is selected, and the clear signal VCLR is output to the counter 21 based on the internal vertical synchronizing signal MVSYNC.

The vertical synchronizing signal VSYNC is input at intervals substantially corresponding to the cycle of one field. Further, the internal vertical synchronization signal MVSYNC is generated and input at intervals corresponding to the cycle of one field. The internal vertical sync signal MVSYNC is
It is output corresponding to the expected input position of the vertical sync signal VSYNC. Therefore, the clear signal VCLR is output at intervals substantially corresponding to the cycle of one field, and the vertical sync signal VCLR is output.
It is generated and output at the position corresponding to the expected input position of VSYNC.

Then, the counter 21 outputs the clear signal VCLR.
When is input, the counter value is cleared. Decoder 2
2 outputs pulse signals S1 and S2 based on the count value of the counter 21, and a control signal STV is generated based on the pulse signals S1 and S2 and is output to the liquid crystal display module 3. Therefore, the control signal STV is generated at an interval corresponding to the cycle of one field, and is generated and output at a position corresponding to the planned input position of the vertical synchronizing signal VSYNC. As a result, since there is no deviation between the vertical scanning of the output image and the video signal, the output image is stably output.

Next, the structure of the judging section 24 will be described in detail. As shown in FIG. 3, the determination unit 24 includes a counter 31
To 33, a phase determination circuit 34, AND circuits 35 and 36, and OR circuits 37 to 39 are provided.

The vertical synchronizing signal VSYNC is input to the counter 31. The input terminal of the counter 31 is connected to the output terminal of the OR circuit 37, and the OR signal of the phase comparison signals PA and PB input to the OR circuit 37 is input. Further, the clock signal CLK is input to the counter 31.

The counter 31 is an up / down counter, operates in synchronization with the clock signal CLK, counts up when the vertical synchronizing signal VSYNC is input, and outputs the signal output from the OR circuit 37, that is, the phase comparison. It counts down when the signal PA or PB is input. The counter 31 then outputs the signals IN0, IN corresponding to the count value.
1 is output to the phase determination circuit 34.

The maximum and minimum count values are preset and stored in the counter 31. The counter 31 has a vertical synchronization signal when the count value is the maximum value.
Even if VSYNC is input, it does not count up any more,
Further, when the count value is the minimum value, the phase comparison signal PA,
Even if PB is input, it will not count down any more.

The maximum count value is set to "3" and the minimum count value is set to "0". Therefore, the counter 31 outputs the signals IN0 and IN1 according to the count value from "0" to "3". Then, in the present embodiment, the counter 31 outputs bit 0 of the count value as the signal IN0 and bit 1 as the signal IN1.

The phase comparison signals PA and PB are vertical synchronization signals.
Specifies the VSYNC pull-in period, and the vertical sync signal VSYN
It is generated and output before and after the expected input position of C. Then, in the normal case (when vertical synchronization is achieved), one vertical synchronization signal VSYNC is input between the phase comparison signal PA and the phase comparison signal PB, and the phase signal PB to the phase comparison signal PA is input. No signal is input between them.

As shown in FIGS. 7 and 8, for example, when the count value of the counter 31 is "0" when the phase comparison signal PA is input, the count value is "1" when the vertical synchronizing signal VSYNC is input. Becomes When the phase comparison signal PB is input next to the vertical synchronizing signal VSYNC, the count value becomes "0" and becomes the minimum value. Then, when the phase comparison signal PA is next input, the counter 31 holds the count value at “0” without counting down because the count value is “0” which is the minimum value.

Therefore, when the input of the vertical synchronizing signal VSYNC is normal, the count value of the counter 31 is the phase comparison signal P.
It is "0" when A is input and "1" when the phase comparison signal PB is input. That is, when the phase comparison signals PA and PB are input, one of the count values is "1" and the other is "0".

When the input of the vertical synchronizing signal VSYNC is out of phase with respect to the phase comparison signals PA and PB, no signal is input between the phase comparison signal PA and the phase comparison signal PB, and the phase comparison signals are compared. The vertical synchronizing signal VSYNC is input between the signal PB and the phase comparison signal PA. Then, the count value of the counter 31 is "1" when the phase comparison signal PA is input and "0" when the phase comparison signal PB is input. Therefore, the phase comparison signals PA, P
As for the count value when B is input, one of them is "1" and the other is "0".

On the other hand, when the input state of the composite video signal is deteriorated and the vertical synchronizing signal VSYNC is not input, the counter 31 does not count up because the vertical synchronizing signal VSYNC is not input. As a result, the count value of the counter 31 is "0" when the phase comparison signals PA and PB are input.

When noise is mixed in the vertical synchronizing signal VSYNC, the counter 31 also counts up due to the mixed noise. As a result, the count value of the counter 31 is counted up by the amount of the mixed noise, so that when the phase comparison signals PA and PB are input, they become “1” and “2” or more, respectively.

The signals IN0 and IN1 output from the counter 31 are input to the phase determination circuit 34. Further, the phase comparison signals PA and PB are input to the phase determination circuit 34. The phase determination circuit 34 outputs the determination signals AO, AC, BO, BC based on the phase comparison signals PA, PB in accordance with the count value between the phase comparison signals PA, PB.

As shown in FIG. 4, the phase determination circuit 34
D flip-flops (hereinafter referred to as DFF) 41, 4
2, NOR circuits 43 and 44, NAND circuits 45 and 46, AND circuits 47 to 50, and inverter circuits 51 to 55.

The NOR circuits 43 and 44 are 2-input elements, and the signals IN0 and IN1 are input to the NOR circuit 43. The signal IN0 is input to one input terminal of the NOR circuit 44 via the inverter circuit 51, and the signal IN1 is directly input to the other input terminal. The output terminal of the NOR circuit 44 is connected to the input terminal D of the DFFs 41 and 42.

The clock input terminal of the DFF 41 is connected to the output terminal of the inverter circuit 52, and the phase comparison signal PB inverted by the inverter circuit 52 is input.
The output terminal of the DFF 41 is connected to the NAND circuit 45.

The clock input terminal of the DFF 42 is connected to the output terminal of the inverter circuit 53, and the phase comparison signal PA inverted by the inverter circuit 53 is input.
The output terminal of the DFF 42 is connected to the NAND circuit 46.

The output terminal of the NAND circuit 46 is connected to one input terminal of the AND circuit 47 via the inverter circuit 54 and is also connected to one input terminal of the AND circuit 48. The phase comparison signal PA is input to the other input terminals of the AND circuits 47 and 48. Then, the AND circuit 47 outputs the determination signal AO, and the AND circuit 48 outputs the determination signal AC.

The output terminal of the NAND circuit 46 is connected to one input terminal of the AND circuit 49 via the inverter circuit 55 and is also connected to one input terminal of the AND circuit 50. The phase comparison signal PB is input to the other input terminals of the AND circuits 49 and 50. Then, the AND circuit 49 outputs the determination signal BO, and the AND circuit 50 outputs the determination signal BC.

When the vertical synchronizing signal VSYNC is normally input, the count value of the counter 31 is "0" when the phase comparison signal PA is input and "0" when the phase comparison signal PB is input, as described above. It is 1 ”.

For example, when the phase comparison signal PA is input, since the count value of the counter 31 is "0", the NOR circuit 43 outputs an H level signal. Since the count value is "1" when the phase comparison signal PB is input prior to the phase comparison signal PA, D
The FF 41 outputs an H level signal. Therefore, the NAND circuit 45 outputs an L level signal, and the L level signal is input to the AND circuit 48.
A signal of H level which is inverted by the inverter circuit 54 is input to 7. As a result, the AND circuit 47 outputs the input phase comparison signal PA as the determination signal AO.

Next, when the phase comparison signal PB is input, since the count value of the counter 31 is "1", the NOR circuit 43 outputs an L level signal. When the phase comparison signal PA is input prior to the phase comparison signal PB, the count value is "0", so D
The FF 42 outputs an L level signal. Therefore, the NAND circuit 46 outputs an H level signal, and the AND circuit 50 receives the H level signal.
A signal of L level which is inverted by the inverter circuit 55 is input to 9. As a result, the AND circuit 50 outputs the input phase comparison signal PB as the determination signal BC.

That is, when the vertical synchronization signal VSYNC is normally input, the phase determination circuit 34 outputs the determination signal AO when the phase comparison signal PA is input and outputs the determination signal AO when the phase comparison signal PB is input. Output BC.

Next, when the phase of the vertical synchronizing signal VSYNC is deviated, the count value of the counter 31 is as described above.
It is "1" when the phase comparison signal PA is input, and "0" when the phase comparison signal PB is input.

For example, when the phase comparison signal PA is input, since the count value of the counter 31 is "1", the NOR circuit 43 outputs an L level signal. Since the count value is "0" when the phase comparison signal PB is input prior to the phase comparison signal PA, D
The FF 41 outputs an L level signal. Therefore, the NAND circuit 45 outputs an H level signal and the AND circuit 48 receives the H level signal.
A signal of L level which is inverted by the inverter circuit 54 is input to 7. As a result, the AND circuit 48 outputs the input phase comparison signal PA as the determination signal AC.

Next, when the phase comparison signal PB is input, since the count value of the counter 31 is "0", the NOR circuit 43 outputs an H level signal. When the phase comparison signal PA is input prior to the phase comparison signal PB, the count value is "1", so D
The FF 42 outputs an H level signal. Therefore, the NAND circuit 46 outputs an L level signal and the AND circuit 50 receives the L level signal.
A signal of H level which is inverted by the inverter circuit 55 is input to the signal 9. As a result, the AND circuit 49 outputs the input phase comparison signal PB as the determination signal BO.

That is, when the phase of the vertical synchronizing signal VSYNC is deviated, the phase determination circuit 34 outputs the determination signal AC when the phase comparison signal PA is input, and the determination signal BO when the phase comparison signal PB is input. Is output. Next, the vertical sync signal
When there is no VSYNC input, the count value of the counter 31 is "0" when the phase comparison signals PA and PB are both input, so the NOR circuit 43 outputs H level signals. Also, the phase comparison signal P
Since the count value is “0” when the phase comparison signal PB (PA) is input prior to A (PB), D
L-level signals are output from the FFs 41 and 42, respectively. As a result, when the phase comparison signal PA is input, the AND circuit 48 outputs the phase comparison signal PA to the determination signal AC.
When the phase comparison signal PB is input as
The phase comparison signal PB from the AND circuit 50 is the judgment signal B.
Output as C.

That is, when the vertical synchronizing signal VSYNC is not input, the phase determination circuit 34 outputs the determination signal AC when the phase comparison signal PA is input, and outputs the determination signal BC when the phase comparison signal PB is input. Output.

Further, when noise is mixed in the vertical synchronizing signal VSYNC, the count value of the counter 31 is the phase comparison signal P.
Since it is "1" or more when A and PB are input, the NOR circuit 43 outputs an L level signal. Further, when the phase comparison signal PB (PA) is input prior to the phase comparison signal PA (PB), the count value is larger than “1”, so that the DFFs 41 and 42 output L level signals, respectively. It As a result, when the phase comparison signal PA is input, the phase comparison signal PA is output from the AND circuit 48 as the determination signal AC, and when the phase comparison signal PB is input, the phase comparison signal PB is output from the AND circuit 50. It is output as the determination signal BC.

That is, when noise is mixed in the vertical synchronization signal VSYNC, the phase determination circuit 34 outputs the determination signal AC when the phase comparison signal PA is input and outputs the determination signal BC when the phase comparison signal PB is input. Is output.

Therefore, the phase determination circuit 34 determines the phase of the vertical synchronizing signal VSYNC based on the phase comparison signals PA and PB. Then, the phase determination circuit 34 determines that the vertical synchronization signal VS
The phase of YNC is normal, that is, the count value of the counter 31 is "1" in the period from the phase comparison signal PA to the phase comparison signal PB, and the phase comparison signal PB to the phase comparison signal PA.
When it is "0" in the period up to, the decision signal AO is output in response to the phase comparison signal PA, and otherwise the decision signal AC is output. Further, the phase determination circuit 34 uses the vertical synchronization signal VS.
The YNC is out of phase, that is, the count value of the counter 31 is "1" during the period from the phase comparison signal PB to the phase comparison signal PA and is "0" during the period from the phase comparison signal PA to the phase comparison signal PB. , The decision signal BO is output in response to the phase comparison signal PB, and otherwise BC is output.

The period from the phase comparison signal PA to the phase comparison signal PB is within the pull-in period of the vertical synchronizing signal VSYNC, and the period from the phase comparison signal PB to the phase comparison signal PA is outside the pull-in period. . Therefore, the phase determination circuit 34 outputs the determination signal AO when the vertical synchronization signal VSYNC is input within the phase pull-in period, and outputs the determination signal BO when the vertical synchronization signal VSYNC is input outside the pull-in period. Output. Then, the phase determination circuit 34 determines whether the vertical synchronization signal VSYNC is input, or when noise is mixed in the vertical synchronization signal VSYNC, the determination signal AC,
Output BC.

As shown in FIG. 3, the determination signals AO and AC output from the phase determination circuit 34 are input to the counter 32, and the determination signals BO and BC are input to the counter 33.
Each of the counters 32 and 33 is an up counter, and the counter 32 counts up when the determination signal AO is input, and clears the count value when the determination signal AC is input. The counter 33 counts up when the judgment signal BO is input, and clears the count value when the judgment signal BC is input. Each of the counters 32 and 33 normally outputs an L level signal, and outputs an H level signal when each count value exceeds a preset predetermined value.

The phase determination circuit 34 outputs the determination signals AO and AC in response to the phase comparison signal PA, and the phase comparison signal P
In response to B, the determination signals BO and BC are output. Since the phase comparison signals PA and PB correspond to the pull-in period of the vertical synchronization signal VSYNC, they are generated and output at intervals corresponding to one field period. Therefore, the determination signals AO, AC and B are generated.
O and BC are also output at intervals corresponding to one field period.

Therefore, the counters 32 and 33 output H-level signals when the determination signals AO and BO are continuously input in a plurality of fields based on a preset predetermined value. In this embodiment, the predetermined values of the counters 32 and 33 are set to "3", respectively. Therefore, the counters 32 and 33 are set to H when the determination signals AO and BO are continuously input for three fields.
It is designed to output a level signal.

The signal output from the counter 32 is input to one input terminal of the AND circuit 35, and the AND circuit 35
The determination signal AO is input to the other input terminal of the. The signal output from the counter 33 is the AND circuit 36.
One of the input terminals is input, and the other input terminal of the AND circuit 36 is input with the determination signal BO. The signals output from the AND circuits 35 and 36 are input to the OR circuit 38, and the open signal SO is output from the OR circuit 38.
Is output.

The determination signals AC and BC output from the phase determination circuit 34 are input to the OR circuit 39, and the OR circuit 39 outputs the determination signal AC or BC as the close signal SC.

Therefore, the determination unit 24 determines that the vertical synchronization signal VSYN
When C is normally input in a plurality of fields in succession or is continuously input in a plurality of fields in a state where the phase of the vertical synchronization signal VSYNC is out of phase, the open signal SO is output to the selection unit 26. The selection unit 26 uses the open signal S
When O is input, the vertical synchronizing signal VSYNC is switched from the internal vertical synchronizing signal MVSYNC, and the clear signal VCLR is output based on the vertical synchronizing signal VSYNC. And the counter 21
Clears the count value based on the clear signal VCLR. With this configuration, a margin for multiple fields is provided after the vertical sync signal VSYNC is normally input, so that there is hysteresis when switching from the internal vertical sync signal MVSYNC to the vertical sync signal VSYNC to prevent flapping at the time of switching. It is like this.

Next, the configuration of the selection unit 26 will be described. As shown in FIG. 5, the selection unit 26 includes a JKFF6.
1, AND circuits 62 and 63, and an OR circuit 64 are provided. The open signal SO is input to the input terminal J of the JKFF 61, and the close signal SC is input to the input terminal K. The clock signal CLK is input to the clock input terminal of the JKFF 61.

The output terminal Q of the JKFF 61 is an AND circuit 6
The vertical synchronizing signal VSYNC is input to the other input terminal of the AND circuit 62. JK
The inverting output terminal QN of the FF 61 is connected to one input terminal of the AND circuit 63, and the internal vertical synchronizing signal MVSYNC is input to the other input terminal of the AND circuit 63. The output terminals of the AND circuits 62 and 63 are respectively connected to the input terminals of the OR circuit 64, and the clear signal VCLR is output from the OR circuit 64.
Is output.

When the open signal SO is input to the input terminal J, the JKFF 61 outputs an H level signal from the output terminal Q to the AND circuit 62 and an L level signal from the inverting output terminal QN to the AND circuit 63. As a result, the vertical synchronizing signal VSYNC is input to the OR circuit 64 via the AND circuit 62 having the H level signal input to one input terminal, and the vertical synchronizing signal VSYNC is output as the clear signal VCLR.

On the other hand, when the close signal SC is input to the input terminal K, the JKFF 61 outputs an L level signal from the output terminal Q to the AND circuit 62 and an H level signal from the inverting output terminal QN to the AND circuit 63. To do. As a result, the internal vertical synchronizing signal MVSY is supplied to the OR circuit 64 via the AND circuit 63 whose H-level signal is input to one input terminal.
NC is input, and its internal vertical synchronizing signal MVSYNC is output as a clear signal VCLR.

That is, the selecting section 26 selects the vertical synchronizing signal VSYNC when the open signal SO is input, and selects the internal vertical synchronizing signal MVSYNC when the close signal SC is input. Then, the selection unit 26 causes the selected vertical synchronization signal VSYN
Clear signal VC based on C or internal vertical sync signal MVSYNC
Output LR.

As described above, according to this embodiment, the following effects can be obtained. (1) The decoder 22 of the vertical synchronization circuit 9 uses the clock signal
Based on the count value of the counter 21 that counts CLK, the internal vertical synchronization signal MV corresponding to the vertical synchronization signal VSYNC
SYNC and phase comparison signals PA and PB corresponding to the pull-in period of the vertical synchronizing signal VSYNC are generated and output. Further, the vertical synchronizing circuit is provided with a judging section 24 and a selecting section 26. The determination unit 24 receives the input phase comparison signals PA and P.
Based on B, one field is divided into two periods, that is, inside the pull-in period and outside the pull-in period, and it is determined in which period the vertical synchronizing signal VSYNC is input. Then, the determination unit 24
Is an open signal SO when the vertical sync signal VSYNC is stably input or a phase shift is input based on the determination result, and a close signal when the vertical sync signal VSYNC is not stable. The SC is output to the selection unit 26. The selector 26 selects the vertical sync signal VSYNC or the internal vertical sync signal MV based on the open signal SO and the close signal.
SYNC is selected, and the clear signal VCLR for clearing the counter 21 is output based on the selected signal.

As a result, when the vertical synchronizing signal VSYNC is not stable, the counter 21 can be cleared based on the internal vertical synchronizing signal MVSYNC corresponding to the vertical synchronizing signal VSYNC, so that the output image is moved in the vertical direction. Can be prevented, and the output image can be displayed stably.

(2) The judging section 24 determines the vertical synchronizing signal VSYNC.
Is input normally in multiple fields continuously, or
When the vertical synchronizing signal VSYNC is continuously input in a plurality of fields in a phase-shifted state, the open signal SO is output to the selecting unit 26. When the open signal SO is input, the selection unit 26 switches from the internal vertical synchronization signal MVSYNC to the vertical synchronization signal VSYNC, and outputs the clear signal VCLR based on the vertical synchronization signal VSYNC. Then, the counter 21 clears the count value based on the clear signal VCLR.
With this configuration, a margin for multiple fields is provided after the vertical sync signal VSYNC is normally input, so that there is hysteresis when switching from the internal vertical sync signal MVSYNC to the vertical sync signal VSYNC to prevent flapping at the time of switching. be able to.

The present invention is not limited to the above embodiment, but may be carried out as follows. (1) In the above embodiment, the vertical synchronizing circuit 9 of the timing controller 5 that handles an NTSC video signal is embodied, but it may be implemented by handling a PAL or SECAM video signal. For example, in the case of the PAL system, the decoder 22 of the vertical synchronizing circuit 9 generates the internal vertical synchronizing signal MVSYNC312.5H because the vertical synchronizing signal VSYNC is input at an interval of approximately 312.5H. Then, the selection unit 26
Is the internal vertical sync signal MVSYNC or vertical sync signal VSYNC
Select the clear signal VCLR based on the selected signal
Is output to clear the counter 21. With this configuration, it is possible to display an image in which the vertical synchronization flow is suppressed in the PAL-type image display device as in the above-described embodiment.

(2) In the above embodiment, the counter 3
The setting values of 2 and 33 are set to "3", respectively, and when switching from the internal vertical synchronizing signal MVSYNC to the vertical synchronizing signal VSYNC, a margin for a plurality of fields is provided to suppress fluttering of switching. The set value of 33 may be set to any value of "1", "2", or "4" or more. In addition, the set value of the counter 32 is set to the counter 33.
The set value of 1 may be set to a value different from each other.

(3) In the above embodiment, the configuration of the phase determination circuit 34 may be changed appropriately. For example, the OR circuits 43 and 44 for decoding the signals IN0 and IN1 input from the counter 31 and the inverter circuit 51 may be provided as separate blocks. Further, the OR circuits 43 and 44 and the inverter circuit 51 may be built in the counter 31.

(4) In the above embodiment, the image display device 1 using the liquid crystal display module 3 is embodied, but instead of the liquid crystal display module 3, another display device such as a CRT or PDP (plasma display panel). It may be embodied in an image display device using.

(5) In the above embodiment, the up counters are used as the counters 32 and 33 of the determination section 24, but down counters may be used instead. In this case, the counters 32 and 33 load predetermined values set in advance in response to the judgment signals AC and BC, and count down each time the judgment signals AO and BO are input from the predetermined values. Then, when the count value becomes "0", an H level signal is output. With this configuration,
The same effects as those of the above-described embodiment can be obtained.

(6) In the above embodiment, as shown in FIG. 9, the counter 32a is used. The counter 32a has a preset function and has an AND circuit 3
When the signal output from 6 is input, it is preset to a preset value (“3”). Therefore, as shown in FIG. 10, the counter 33 counts the determination signal BO and outputs the open signal CO, and at the same time, the count value of the counter 32a which has not been operated until then is "3".
Preset to. As a result, after that, the determination signal AO
Is input, the open signal SO is immediately output, and thereafter, the vertical synchronizing signal VSYNC is selected. With this configuration, the same effect as that of the above-described embodiment can be obtained.

[0098]

As described in detail above, according to the present invention, it is possible to provide a vertical synchronizing circuit and a timing controller capable of stabilizing an output image in an unstable synchronizing input state.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment.

FIG. 2 is a block circuit diagram of a vertical synchronizing circuit according to an embodiment.

FIG. 3 is a block circuit diagram of a determination unit.

FIG. 4 is a circuit diagram of a phase determination circuit section.

FIG. 5 is a circuit diagram of a selection unit.

FIG. 6 is a circuit diagram of a signal processing unit.

FIG. 7 is a timing chart showing the operation of the vertical synchronizing circuit.

FIG. 8 is a timing chart showing the operation of the vertical synchronizing circuit.

FIG. 9 is a block circuit diagram of another determination unit.

FIG. 10 is a timing chart showing the operation of another determination unit.

FIG. 11 is a block circuit diagram of a conventional vertical synchronizing circuit.

FIG. 12 is a timing chart showing a vertical synchronization signal.

FIG. 13 is a timing chart showing a case of synchronous flow.

FIG. 14 is an explanatory diagram showing a screen in the case of synchronous flow.

[Explanation of symbols]

 5 Timing Controller 9 Vertical Synchronous Circuit 21 Counter 22 (First and Second) Decoder 24 Judgment Unit as Judgment Circuit 26 Selection Part as Selection Circuit 31 Counter 32, 33 Counter 34 Phase Judgment Circuit CLK Clock Signal SO As Judgment Signal Open signal SC Close signal as judgment signal PA, PB Phase comparison signal MVSYNC Internal vertical sync signal VSYNC Vertical sync signal VCLR Clear signal

Claims (7)

[Claims] 1. A counter that counts a clock signal generated based on a horizontal synchronization signal, generates and outputs a control signal for timing an output image based on the count value of the counter, and also performs vertical synchronization. A pull-in period is provided before and after the planned signal input position, the vertical synchronizing signal input within the pull-in period is validated, and a clear signal is generated based on the vertical synchronizing signal to clear the count value of the counter. In the vertical synchronizing circuit, an internal vertical synchronizing signal corresponding to the vertical synchronizing signal is generated, a clear signal is generated using the internal vertical synchronizing signal to clear the counter, and the state of the vertical synchronizing signal is determined.
A vertical synchronizing circuit that generates a clear signal by selecting the vertical synchronizing signal when the vertical synchronizing signal is stably input based on the determination result. 2. The vertical synchronizing circuit according to claim 1, wherein an internal vertical synchronizing signal corresponding to the vertical synchronizing signal is generated, and one field is divided into two periods, a pull-in period and a pull-out period. , Determine the state of the vertical synchronization signal based on those periods, select the internal vertical synchronization signal or vertical synchronization signal based on the determination result, the clear signal based on the selected internal vertical synchronization signal or vertical synchronization signal A vertical synchronization circuit that generates a and clears the counter. 3. A counter that counts a clock signal generated based on a horizontal synchronizing signal, generates and outputs a control signal for timing an output image based on the count value of the counter, and also performs vertical synchronization. A pull-in period is provided before and after the planned signal input position, the vertical synchronizing signal input within the pull-in period is validated, and a clear signal is generated based on the vertical synchronizing signal to clear the count value of the counter. In the vertical synchronization circuit, a first decoder that generates a phase comparison signal before and after a planned input position of the vertical synchronization signal based on the count value of the counter, corresponding to the pull-in period of the vertical synchronization signal; A second decoder for generating an internal vertical synchronization signal corresponding to the vertical synchronization signal based on the count value of The phase comparison signal generated by the first decoder is input, one field is divided into two periods, that is, within the pull-in period and outside the pull-in period, based on the phase comparison signal, and based on these periods, the vertical synchronization signal A determination circuit that determines whether the state is stable and outputs a determination signal according to the determination result, and a determination signal that is input from the vertical synchronization signal and the internal vertical synchronization signal and that is output from the determination circuit The vertical synchronizing signal is selected based on the determination signal when the vertical synchronizing signal is stable, and when the vertical synchronizing signal is not stable, the internal vertical synchronizing signal is selected and the selected vertical synchronizing signal is selected. A vertical synchronization circuit including a selection circuit that outputs a clear signal based on a signal. 4. The vertical synchronization circuit according to claim 3, wherein the determination circuit outputs the determination signal when the vertical synchronization signal is stably input in a plurality of fields. 5. The vertical synchronization circuit according to claim 3, wherein the determination circuit counts up based on the vertical synchronization signal and counts down based on the phase comparison signal, and a count of the counter. Based on the value and the pull-in period and the pull-out period set based on the phase comparison signal, one pulse is input in the pull-in period and 0 is input in the pull-out period. Or
Or, the pulse input during the pull-in period is 0, and
A vertical synchronization circuit, comprising: a phase determination circuit that determines that the vertical synchronization signal is stable when there is one pulse input outside the pull-in period and outputs the determination result. 6. The vertical synchronization circuit according to claim 5, wherein the determination circuit further counts the determination result output from the phase determination circuit, and when the count value exceeds a predetermined value, the determination is performed. A vertical synchronizing circuit having a counter for outputting a signal. 7. A horizontal synchronizing circuit that generates and outputs a control signal for timing an output image and a clock signal based on the horizontal synchronizing signal, and the horizontal synchronizing circuit according to claim 1. A timing controller comprising the vertical synchronization circuit described.