JPH088659A - Microwave semiconductor package - Google Patents
Microwave semiconductor packageInfo
- Publication number
- JPH088659A JPH088659A JP6139831A JP13983194A JPH088659A JP H088659 A JPH088659 A JP H088659A JP 6139831 A JP6139831 A JP 6139831A JP 13983194 A JP13983194 A JP 13983194A JP H088659 A JPH088659 A JP H088659A
- Authority
- JP
- Japan
- Prior art keywords
- feedback circuit
- cap
- dielectric
- semiconductor package
- pedestal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Microwave Amplifiers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体パッケージに関
するものであり、特にマイクロ波帯で使用される半導体
パッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a semiconductor package used in the microwave band.
【０００２】[0002]
【従来の技術】図５は、従来のマイクロ波半導体パッケ
ージの誘電体キャップを取り外した状態を示す平面図、
図６は、図５のＡ−Ａ線断面図である。図において、１
はアルミナ等の誘電体材料から成る台座であり、２はア
ルミナ等の誘電体材料から成るリング状の側壁である。
３、４、５、６は金属板に金メッキ等を施した電極リー
ドである。３はゲート電極リード、４はドレイン電極リ
ード、５、６はソース電極リードである。また、７は誘
電体製の封止用キャップをロー付けするためのメタライ
ズである。図７は従来の誘電体製キャップの下面を示す
図である。８は誘電体キャップ側のロー付け用メタライ
ズである。2. Description of the Related Art FIG. 5 is a plan view showing a conventional microwave semiconductor package with a dielectric cap removed.
FIG. 6 is a sectional view taken along the line AA of FIG. In the figure, 1
Is a pedestal made of a dielectric material such as alumina, and 2 is a ring-shaped side wall made of a dielectric material such as alumina.
Reference numerals 3, 4, 5, and 6 are electrode leads obtained by plating a metal plate with gold or the like. Reference numeral 3 is a gate electrode lead, 4 is a drain electrode lead, and 5 and 6 are source electrode leads. Further, 7 is a metallization for brazing a sealing cap made of a dielectric material. FIG. 7 is a view showing the lower surface of a conventional dielectric cap. 8 is a brazing metallization on the side of the dielectric cap.
【０００３】[0003]
【発明が解決しようとする課題】以下、ＦＥＴ（電界効
果型トランジスタ）用パッケージについて説明する。図
８は、低雑音増幅器を示す図である。ＦＥＴを使用し
て、マイクロ波帯の低雑音増幅器を設計する場合、パッ
ケージに搭載されたＦＥＴ９を実装するマイクロストリ
ップライン基板１０の入力側、出力側にそれぞれスタブ
等を利用した整合回路１１、１２を接続し、所望のＮＦ
（雑音指数）特性、利得特性、安定性を実現している。
１３はＤＣバイアス供給回路、１４は接地用グランドパ
ターンである。また、前記の整合回路１１、１２に加え
てマイクロストリップライン上に帰還回路を付加してさ
らに設計の自由度を向上させる方法も特開平２−１１３
６１０号公報により開示されている。図９は、マイクロ
ストリップラインにて構成される帰還回路１５を付加し
た低雑音増幅器を示す図である。しかし、帰還回路１５
を付加する場合、マイクロストリップラインにて構成す
ると、基板１０上に帰還回路１５のメタライズパターン
が大きな面積を占めるため小型化に不利であるという問
題点があった。The FET (field effect transistor) package will be described below. FIG. 8 is a diagram showing a low noise amplifier. In the case of designing a microwave band low noise amplifier using FETs, matching circuits 11 and 12 using stubs or the like on the input side and the output side of a microstrip line substrate 10 on which the FET 9 mounted in the package is mounted, respectively. Connect the desired NF
(Noise figure) characteristics, gain characteristics, and stability are realized.
Reference numeral 13 is a DC bias supply circuit, and 14 is a grounding ground pattern. In addition to the matching circuits 11 and 12, a method of adding a feedback circuit on the microstrip line to further improve the degree of freedom of design is also disclosed in Japanese Patent Laid-Open No. 2-113.
No. 610 publication. FIG. 9 is a diagram showing a low noise amplifier to which a feedback circuit 15 composed of a microstrip line is added. However, the feedback circuit 15
In the case of adding, the metallization pattern of the feedback circuit 15 occupies a large area on the substrate 10 if it is constituted by a microstrip line, which is disadvantageous in miniaturization.
【０００４】本発明の目的は、かかる問題点を解決し、
帰還回路を付加した小型のマイクロ波半導体パッケージ
を提供することにある。The object of the present invention is to solve these problems,
It is to provide a small microwave semiconductor package to which a feedback circuit is added.
【０００５】[0005]
【課題を解決するための手段】本発明のマイクロ波半導
体パッケ−ジは、アルミナ等の誘電体材料からなる封止
用のキャップの下面に、入力部からのメタライズパター
ンと出力部からのメタライズパターンを形成し、容量性
結合させるようにパッケージ内部に帰還回路を付加する
ようにしてマイクロ波半導体パッケージを構成した。A microwave semiconductor package according to the present invention comprises a metallized pattern from an input portion and a metallized pattern from an output portion on the lower surface of a sealing cap made of a dielectric material such as alumina. Then, a microwave semiconductor package was constructed by adding a feedback circuit inside the package so as to form a capacitive coupling.
【０００６】[0006]
【作用】本発明は、上記のように構成したので、パッケ
ージ内部に帰還回路の機能を組み込むことができるの
で、帰還回路を付加した低雑音増幅器の小型化が可能と
なる。Since the present invention is configured as described above, the function of the feedback circuit can be incorporated inside the package, and therefore the low noise amplifier to which the feedback circuit is added can be miniaturized.
【０００７】[0007]
【実施例】以下図面を用いて本発明の実施例を説明す
る。図１は、本発明のマイクロ波半導体パッケージの第
１実施例であり、誘電体製キャップを取り外し、ＦＥＴ
を実装した状態の上面図、図２はＢ−Ｂ線断面図であ
る。図３は、誘電体製キャップの下面を示す底面図であ
る。ゲート電極リード３から入力した信号は台座の側面
メタライズ１６をあがって台座１の上面メタライズ１７
からＦＥＴのゲート電極１８に到達する。また、ＦＥＴ
のドレイン電極１９から出力された増幅信号は、台座１
の上面メタライズ２０から台座の側面メタライズ２１を
下がってドレイン電極リード４から出力される。また、
入力側の台座１の上面メタライズ１７は、リング状の誘
電体の内側のメタライズパターン２３につながってお
り、同様に出力側から分岐してキャップ下面のメタライ
ズパターン２４との間で容量性の結合を生じている。２
６は気密封止を行う際にキャップをロー付けするための
リング状のメタライズであり、２７はキャップ側のロー
付けするためのリング状のメタライズである。ロー付け
用メタライズ２７は、前記のメタライズパターン２３、
２４とは接触しないものとする。これにより帰還回路を
パッケージ内部に組み込むことが可能となる。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a microwave semiconductor package according to a first embodiment of the present invention.
Is a top view of the mounted state, and FIG. 2 is a sectional view taken along line BB. FIG. 3 is a bottom view showing the lower surface of the dielectric cap. A signal input from the gate electrode lead 3 is raised on the side surface metallization 16 of the pedestal and then on the upper surface of the pedestal 1
Reaches the gate electrode 18 of the FET. In addition, FET
The amplified signal output from the drain electrode 19 of the
It is output from the drain electrode lead 4 from the upper surface metallization 20 to the side surface metallization 21 of the pedestal. Also,
The upper surface metallization 17 of the pedestal 1 on the input side is connected to the inner metallization pattern 23 of the ring-shaped dielectric, and similarly branches off from the output side to form a capacitive coupling with the metallization pattern 24 on the lower surface of the cap. Has occurred. Two
Reference numeral 6 is a ring-shaped metallization for brazing the cap when performing airtight sealing, and 27 is a ring-shaped metallization for brazing the cap side. The brazing metallization 27 is the metallization pattern 23,
No contact with 24. This makes it possible to incorporate the feedback circuit inside the package.
【０００８】図３は、本発明のマイクロ波半導体パッケ
ージの第２実施例の誘電体製キャップの下面を示す図で
ある。２８は、メタライズパターン、２９は容量製のギ
ャップである。図３のキャップは、高誘電率の誘電体か
らなっているので、ギャップ２９による容量を大きくす
ることが出来る。FIG. 3 is a view showing the lower surface of the dielectric cap of the second embodiment of the microwave semiconductor package of the present invention. 28 is a metallized pattern, and 29 is a gap made of a capacitor. Since the cap shown in FIG. 3 is made of a dielectric material having a high dielectric constant, the capacitance of the gap 29 can be increased.
【０００９】ここでは、ＦＥＴ用のマイクロ波半導体パ
ッケージについて説明したが、ＨＥＭＴ等他にトランジ
スタ用のマイクロ波パッケージについても同様に実施で
きることは明らかである。Although the microwave semiconductor package for the FET has been described here, it is apparent that the same can be applied to the microwave package for the transistor other than the HEMT and the like.
【００１０】[0010]
【発明の効果】以上説明したように、本発明のパッケー
ジを使用すれば、パッケージ内部に帰還回路の機能を組
み込むことが可能となるので、帰還回路を付加した低雑
音増幅器の小型化が図れるという効果がある。As described above, when the package of the present invention is used, the function of the feedback circuit can be incorporated into the package, so that the low noise amplifier including the feedback circuit can be downsized. effective.
【図１】本発明の第１の実施例を示すマイクロ波半導体
パッケージの誘電体キャップを外し、ＦＥＴを実装した
状態の平面図。FIG. 1 is a plan view showing a microwave semiconductor package according to a first embodiment of the present invention in which a dielectric cap is removed and an FET is mounted.
【図２】本発明の第１の実施例を示すマイクロ波半導体
パッケージの誘電体キャップを外し、ＦＥＴを実装した
状態の図１Ｂ−Ｂ線断面図。FIG. 2 is a sectional view taken along the line BB of FIG. 1 showing a state where the dielectric cap of the microwave semiconductor package according to the first embodiment of the present invention is removed and the FET is mounted.
【図３】本発明の第１実施例であるマイクロ波パッケー
ジの誘電体キャップ底面図FIG. 3 is a bottom view of the dielectric cap of the microwave package according to the first embodiment of the present invention.
【図４】本発明の第２実施例であるマイクロ波パッケー
ジの誘電体キャップ底面図FIG. 4 is a bottom view of the dielectric cap of the microwave package according to the second embodiment of the present invention.
【図５】従来のマイクロ波半導体パッケージの誘電体キ
ャップを外した状態の平面図。FIG. 5 is a plan view of a conventional microwave semiconductor package with a dielectric cap removed.
【図６】図５のマイクロ波半導体パッケージの誘電体キ
ャップを外した状態のＡ−Ａ線断面図。6 is a cross-sectional view taken along the line AA of the microwave semiconductor package of FIG. 5 with a dielectric cap removed.
【図７】従来のマイクロ波半導体パッケージの誘電体キ
ャップ底面図。FIG. 7 is a bottom view of a dielectric cap of a conventional microwave semiconductor package.
【図８】従来の低雑音増幅器の回路構成図。FIG. 8 is a circuit configuration diagram of a conventional low noise amplifier.
【図９】従来の帰還回路を付加した低雑音増幅器の回路
構成図。FIG. 9 is a circuit configuration diagram of a low noise amplifier to which a conventional feedback circuit is added.
１ 誘電体の台座 ２ 誘電体製のリング ３ ゲート電極リード ４ ドレイン電極リード ５ ソース電極リード ６ ソース電極リード ７ ロー付け用メタライズ ８ ロー付け用メタライズ ９ ＦＥＴが搭載されたパッケージ １０ マイクロストリップライン基板 １１ 入力側整合回路 １２ 出力側整合回路 １３ ＤＣバイアス供給回路 １４ 接地用グランドパターン １５ 帰還回路 １６ 台座の側面メタライズ １７ 台座の上面メタライズ １８ ＦＥＴのゲート電極 １９ ＦＥＴのドレイン電極 ２０ 台座の上面メタライズ ２１ 台座の側面メタライズ ２２ リング状誘電体の内側面メタライズ ２３ キャップ裏面のメタライズ ２４ キャップ裏面のメタライズ ２５ リング状誘電体の内側面メタライズ ２６、２７ ロー付け用メタライズ ２８ キャップ裏面のメタライズ ２９ 容量性ギャップ ３０ 半導体チップ 1 pedestal of dielectric 2 dielectric ring 3 gate electrode lead 4 drain electrode lead 5 source electrode lead 6 source electrode lead 7 brazing metallization 8 brazing metallization 9 package with FET 10 microstripline substrate 11 Input side matching circuit 12 Output side matching circuit 13 DC bias supply circuit 14 Ground pattern for ground 15 Feedback circuit 16 Side metallization of pedestal 17 Top side metallization of pedestal 18 Gate electrode of FET 19 FET drain electrode 20 Top side metallization of pedestal 21 Pedestal Side metallization 22 Inner side metallization of ring-shaped dielectric 23 Metallization of backside of cap 24 Metallization of backside of cap 25 Metallization of inner side of ring-shaped dielectric 26, 27 Metallization for brazing 28 Metalization on backside of cap Rise 29 capacitive gap 30 semiconductor chip
Claims (1)
する誘電体の台座と、台座の上に固定されてデバイスチ
ップを収納するための凹部を形成するリング状の誘電体
と、凹部を封止するためにリング状の誘電体の上に固定
される誘電体キャップと、台座の誘電体より導出した複
数の電極リードを有するマイクロ波半導体パッケージに
おいて、誘電体キャップの下面に入力側からのメタライ
ズパターンと出力側からのメタライズパターンを形成す
るとともにこれらを容量性結合させることにより帰還回
路の機能を付加したことを特徴とするマイクロ波半導体
パッケ−ジ1. A pedestal of a dielectric material on which a semiconductor device chip for microwaves is mounted, a ring-shaped dielectric material fixed on the pedestal to form a concave portion for housing a device chip, and the concave portion is sealed. In a microwave semiconductor package having a dielectric cap fixed on a ring-shaped dielectric and a plurality of electrode leads derived from the pedestal dielectric, a metallization pattern from the input side is formed on the lower surface of the dielectric cap. A microwave semiconductor package characterized by adding a function of a feedback circuit by forming a metallized pattern from the output side and capacitively coupling these.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6139831A JPH088659A (en) | 1994-06-22 | 1994-06-22 | Microwave semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6139831A JPH088659A (en) | 1994-06-22 | 1994-06-22 | Microwave semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH088659A true JPH088659A (en) | 1996-01-12 |
Family
ID=15254512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6139831A Pending JPH088659A (en) | 1994-06-22 | 1994-06-22 | Microwave semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH088659A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007520129A (en) * | 2004-01-30 | 2007-07-19 | ノキア コーポレイション | Adjustment circuit |
-
1994
- 1994-06-22 JP JP6139831A patent/JPH088659A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007520129A (en) * | 2004-01-30 | 2007-07-19 | ノキア コーポレイション | Adjustment circuit |
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