JPH0870118A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0870118A JPH0870118A JP6206415A JP20641594A JPH0870118A JP H0870118 A JPH0870118 A JP H0870118A JP 6206415 A JP6206415 A JP 6206415A JP 20641594 A JP20641594 A JP 20641594A JP H0870118 A JPH0870118 A JP H0870118A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- region
- conductivity type
- drain electrode
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 239000000758 substrate Substances 0.000 claims description 15
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 230000000694 effects Effects 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 230000002040 relaxant effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000005684 electric field Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000005669 field effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は高耐圧横型ＭＯＳ電界
効果トランジスタ等の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a high voltage lateral MOS field effect transistor.
【０００２】[0002]
【従来の技術】従来の半導体装置として、高耐圧横型Ｍ
ＯＳ電界効果トランジスタについて説明する。図５は従
来の半導体装置の平面図であり、図６は図５におけるＣ
−Ｃ断面図である。また、図５におけるＤ−Ｄ断面図は
実施例の図３と同様であるので、図５，図６および図３
を参照しながら説明する。図３，図５，図６において、
１は第２導電型の高濃度のドレインコンタクト領域、２
は第２導電型のドレイン領域、３は第１導電型領域（以
下「ＰＴ領域」と称する）、４は第１導電型のシリコン
基板、５はチャンネル部、６はゲート酸化膜、７はゲー
ト電極、８は第２導電型のソース領域、９は第１導電型
の高濃度のチャンネルストッパ、１０は第１導電型の高
濃度領域、１１はソース電極、１２はドレイン電極、１
３は層間絶縁膜、１４はフィールド酸化膜である。な
お、第１導電型をｐ型，第２導電型をｎ型としてもよい
し、第１導電型をｎ型，第２導電型をｐ型としてもよ
い。2. Description of the Related Art As a conventional semiconductor device, a high withstand voltage lateral type M
The OS field effect transistor will be described. FIG. 5 is a plan view of a conventional semiconductor device, and FIG. 6 is C in FIG.
FIG. Further, the sectional view taken along the line D-D in FIG. 5 is similar to that of the embodiment shown in FIG.
Will be described with reference to. In FIGS. 3, 5 and 6,
1 is a high-concentration drain contact region of the second conductivity type, 2
Is a second conductivity type drain region, 3 is a first conductivity type region (hereinafter referred to as “PT region”), 4 is a first conductivity type silicon substrate, 5 is a channel portion, 6 is a gate oxide film, and 7 is a gate. Electrode, 8 is a second conductivity type source region, 9 is a first conductivity type high concentration channel stopper, 10 is a first conductivity type high concentration region, 11 is a source electrode, 12 is a drain electrode, 1
Reference numeral 3 is an interlayer insulating film, and 14 is a field oxide film. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type.
【０００３】高濃度のドレインコンタクト領域１は、ド
レイン領域２上に形成されるとともに、ドレイン領域２
上に形成されたＰＴ領域３に周囲を取り囲まれている。
ドレイン領域２とシリコン基板４との接合部におけるシ
リコン基板４の側の表面にはチャンネル部５が形成さ
れ、チャンネル部５の上にはゲート酸化膜６および多結
晶シリコン膜からなるゲート電極７が形成されている。
チャンネル部５の横にはドレイン領域２に相対して第２
導電型のソース領域８が形成されており、またソース領
域８を取り囲むようにして高濃度の第１導電型のチャン
ネルストッパ９が形成されている。さらにチャンネル部
５の基板バイアス効果を抑制するため、ソース領域８に
隣接して第１導電型の高濃度領域１０を設け、ソース領
域８と同様にソース電極１１と電気的に接続されてい
る。またＰＴ領域３は、図６に示すように、その一部が
シリコン基板４と電気的に接続されるとともに、第１導
電型の高濃度のチャンネルストッパ９および第１導電型
の高濃度領域１０を介してソース電極１１と電気的に接
続されている。The high-concentration drain contact region 1 is formed on the drain region 2, and the drain region 2 is also formed.
It is surrounded by the PT region 3 formed above.
A channel portion 5 is formed on the surface of the junction of the drain region 2 and the silicon substrate 4 on the silicon substrate 4 side, and a gate oxide film 6 and a gate electrode 7 made of a polycrystalline silicon film are formed on the channel portion 5. Has been formed.
Next to the drain region 2 is a second side of the channel portion 5.
A conductive type source region 8 is formed, and a high-concentration first conductive type channel stopper 9 is formed so as to surround the source region 8. Further, in order to suppress the substrate bias effect of the channel portion 5, a high-concentration region 10 of the first conductivity type is provided adjacent to the source region 8 and is electrically connected to the source electrode 11 like the source region 8. As shown in FIG. 6, a part of the PT region 3 is electrically connected to the silicon substrate 4, and the first conductivity type high concentration channel stopper 9 and the first conductivity type high concentration region 10 are provided. Is electrically connected to the source electrode 11 via.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら上記従来
の構成では、図６に示すドレイン領域２の長手方向（図
５のＣ−Ｃ方向）先端部において電界集中が起こり、ド
レイン・ソース間耐圧を低下させてしまうという課題を
有していた。この発明は上記従来の課題を解決するもの
で、ドレイン領域の長手方向先端部での電界の集中を緩
和し、ドレイン・ソース間耐圧を向上することのできる
半導体装置を提供することを目的とする。However, in the above conventional structure, electric field concentration occurs at the tip of the drain region 2 shown in FIG. 6 in the longitudinal direction (CC direction in FIG. 5), and the drain-source breakdown voltage is lowered. There was a problem of causing it. The present invention solves the above-described conventional problems, and an object of the present invention is to provide a semiconductor device capable of alleviating the concentration of an electric field at the tip of the drain region in the longitudinal direction and improving the drain-source breakdown voltage. .
【０００５】[0005]
【課題を解決するための手段】請求項１記載の半導体装
置は、第１導電型の半導体基板上に細長形状の第２導電
型のドレイン領域を形成し、ドレイン領域上の内部に細
長形状の高濃度第２導電型のドレインコンタクト領域を
介して細長形状のドレイン電極を形成し、ドレイン領域
上のドレインコンタクト領域の周囲に半導体基板と電気
的に接続された第１導電型領域を形成し、ドレイン領域
の両側にチャンネル部を介して第２導電型のソース領域
をドレイン領域の長手方向と略平行に形成し、ドレイン
領域の両側のソース領域上にソース電極を形成し、チャ
ンネル部の上にゲート絶縁膜を介してゲート電極を形成
し、細長形状のドレイン電極はその輪郭が細長形状のド
レインコンタクト領域の輪郭の外側になるように形成さ
れた半導体装置であって、ドレイン電極を長手方向に延
伸し、ドレイン電極の長手方向端部のドレインコンタク
ト領域からの距離を、ドレイン電極の幅方向端部のドレ
インコンタクト領域からの距離よりも長くしたことを特
徴とする。According to another aspect of the present invention, there is provided a semiconductor device having a first conductivity type semiconductor substrate, an elongated second conductivity type drain region formed on the first conductivity type semiconductor substrate, and an elongated shape drain region formed inside the drain region. An elongated drain electrode is formed through the high-concentration second conductivity type drain contact region, and a first conductivity type region electrically connected to the semiconductor substrate is formed on the drain region around the drain contact region. A source region of the second conductivity type is formed on both sides of the drain region substantially parallel to the longitudinal direction of the drain region, and source electrodes are formed on the source regions on both sides of the drain region. In a semiconductor device in which a gate electrode is formed through a gate insulating film, the elongated drain electrode is formed so that its contour is outside the contour of the elongated drain contact region. Therefore, the drain electrode is extended in the longitudinal direction, and the distance from the drain contact region at the longitudinal end of the drain electrode is longer than the distance from the drain contact region at the lateral end of the drain electrode. To do.
【０００６】請求項２記載の半導体装置は、請求項１記
載の半導体装置において、ドレイン電極の長手方向端部
のドレインコンタクト領域からの距離を２０μｍよりも
長くしている。According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the distance from the drain contact region at the longitudinal end of the drain electrode is longer than 20 μm.
【０００７】[0007]
【作用】この発明の構成によれば、細長形状のドレイン
電極を長手方向に延伸し、ドレイン電極の長手方向端部
のドレインコンタクト領域からの距離を、ドレイン電極
の幅方向端部のドレインコンタクト領域からの距離より
も長くしたことにより、いわゆるフィールドプレートの
効果により、ドレイン領域の長手方向先端部での電界の
集中を緩和し、ドレイン領域の長手方向先端部における
ドレイン・ソース間耐圧を向上することができる。According to the structure of the present invention, the elongated drain electrode is elongated in the longitudinal direction, and the distance from the drain contact region at the longitudinal end of the drain electrode is defined as the drain contact region at the lateral end of the drain electrode. By increasing the distance from, the concentration of the electric field at the tip of the drain region in the longitudinal direction is relieved and the breakdown voltage between the drain and the source at the tip of the drain region in the longitudinal direction is improved due to the so-called field plate effect. You can
【０００８】[0008]
【実施例】以下、この発明の一実施例について、図面を
参照しながら説明する。図１はこの発明の一実施例の半
導体装置（高耐圧横型ＭＯＳ電界効果トランジスタ）の
平面図、図２は図１におけるＡ−Ａ断面図、図３は図１
におけるＢ−Ｂ断面図である。図１，図２，図３におい
て、１２ａはドレイン電極であり、その他の構成は従来
例と同様であるので図５，図６と同一符号を付し、その
説明を省略する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a plan view of a semiconductor device (high breakdown voltage lateral MOS field effect transistor) according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line AA in FIG. 1, and FIG.
6 is a sectional view taken along line BB in FIG. 1, FIG. 2, and FIG. 3, reference numeral 12a is a drain electrode, and the other configurations are similar to those of the conventional example, and therefore, the same reference numerals as those in FIGS.
【０００９】この実施例の半導体装置は、従来例同様、
シリコン基板（半導体基板）４上に、細長形状のドレイ
ン領域２を形成してあり、ドレイン領域２上の内部に、
細長形状のドレインコンタクト領域１を介して、細長形
状のドレイン電極１２ａを形成している。ドレイン領域
２上のドレインコンタクト領域１の周囲にシリコン基板
４と電気的に接続されたＰＴ領域（第１導電型領域）３
を形成している。また、ドレイン領域２の両側にチャン
ネル部５を介して、ソース領域８をドレイン領域２の長
手方向と略平行に形成してある。そして、両側に形成さ
れた２つのソース領域８はソース電極１１に接続されて
いる。また、チャンネル部５の上にゲート酸化膜（ゲー
ト絶縁膜）６を介してゲート電極７を形成してある。そ
して、細長形状のドレイン電極１２ａはその輪郭が細長
形状のドレインコンタクト領域１の輪郭の外側になるよ
うに形成されている。The semiconductor device of this embodiment is similar to the conventional example.
An elongated drain region 2 is formed on a silicon substrate (semiconductor substrate) 4, and inside the drain region 2,
An elongated drain electrode 12a is formed via the elongated drain contact region 1. A PT region (first conductivity type region) 3 electrically connected to the silicon substrate 4 around the drain contact region 1 on the drain region 2.
Is formed. A source region 8 is formed on both sides of the drain region 2 with a channel portion 5 interposed therebetween and is substantially parallel to the longitudinal direction of the drain region 2. The two source regions 8 formed on both sides are connected to the source electrode 11. A gate electrode 7 is formed on the channel portion 5 with a gate oxide film (gate insulating film) 6 interposed therebetween. The elongated drain electrode 12a is formed so that its contour is outside the contour of the elongated drain contact region 1.
【００１０】この実施例の特徴は、ドレイン電極１２ａ
を、図１におけるＡ−Ａ方向に延伸したことである。す
なわち、ドレイン電極１２ａの長手方向（Ａ−Ａ方向）
端部のドレインコンタクト領域１からの距離Ｌ1 を、ド
レイン電極１２ａの幅方向（Ｂ−Ｂ方向）端部のドレイ
ンコンタクト領域１からの距離Ｌ2 よりも大きくしてい
る。また、この実施例では距離Ｌ2 を２０μｍとし、距
離Ｌ1 を２０μｍより長くしている。なお、図５に示す
従来例ではＬ1 ＝Ｌ2 ＝２０μｍである。また、この実
施例では、ドレイン電極１２ａの長手方向におけるドレ
イン電極１２ａとソース電極１１との距離Ｌ3 を、ドレ
イン電極１２ａの幅方向におけるドレイン電極１２ａと
ソース電極１１との距離Ｌ4 よりも長くしている。The feature of this embodiment is that the drain electrode 12a is formed.
Was stretched in the AA direction in FIG. That is, the longitudinal direction of the drain electrode 12a (A-A direction)
The distance L 1 from the drain contact region 1 of the end portion is made larger than the distance L 2 from the drain contact region 1 in the width direction (B-B direction) end portion of the drain electrode 12a. Further, in this embodiment, the distance L 2 is 20 μm and the distance L 1 is longer than 20 μm. In the conventional example shown in FIG. 5, L 1 = L 2 = 20 μm. In this embodiment, the distance L 3 between the drain electrode 12a and the source electrode 11 in the longitudinal direction of the drain electrode 12a is longer than the distance L 4 between the drain electrode 12a and the source electrode 11 in the width direction of the drain electrode 12a. are doing.
【００１１】図４は距離Ｌ1 とドレイン・ソース間耐圧
の関係を示す図である。この図４からわかるように、ド
レイン電極１２ａを、その長手方向端部のドレインコン
タクト領域１からの距離Ｌ1 を２０μｍ（＝Ｌ2 ）より
長く形成することで、いわゆるフィールドプレートの効
果により、ドレイン領域２の長手方向先端部での電界の
集中を緩和し、ドレイン・ソース間耐圧を向上させるこ
とが可能となる。これは、逆バイアスされたとき、ドレ
イン領域２の長手方向先端部の曲率を有する部分で、空
乏層の伸びが滑らかとなり、電界強度を緩和することが
できるからである。FIG. 4 is a diagram showing the relationship between the distance L 1 and the drain-source breakdown voltage. As can be seen from FIG. 4, by forming the drain electrode 12a at a distance L 1 from the drain contact region 1 at the end in the longitudinal direction longer than 20 μm (= L 2 ), a so-called field plate effect is provided. It is possible to reduce the concentration of the electric field at the tip of the region 2 in the longitudinal direction and improve the drain-source breakdown voltage. This is because the extension of the depletion layer becomes smooth and the electric field strength can be relaxed in the portion having the curvature at the tip of the drain region 2 in the longitudinal direction when reverse biased.
【００１２】なお、ドレイン電極１２ａを幅方向（図１
のＢ−Ｂ方向）に拡大させる、すなわちＬ2 を大きくす
ると、ドレイン・ソース電極１２ａ，１１間の間隔が短
くなり、ドレイン領域２の内部にて、電界集中が発生
し、耐圧を低下させてしまうことになる。したがって、
この実施例ではＬ2 を大きくせず、ドレイン領域２内部
の耐圧を低下させることなく、ドレイン領域２の長手方
向先端部での耐圧を向上させている。The drain electrode 12a is formed in the width direction (see FIG.
In the BB direction), that is, when L 2 is increased, the distance between the drain and source electrodes 12a and 11 is shortened, electric field concentration occurs inside the drain region 2, and the breakdown voltage is lowered. Will end up. Therefore,
In this embodiment, L 2 is not increased, the breakdown voltage inside the drain region 2 is not lowered, and the breakdown voltage at the tip portion in the longitudinal direction of the drain region 2 is improved.
【００１３】[0013]
【発明の効果】以上のようにこの発明は、細長形状のド
レイン電極を長手方向に延伸し、ドレイン電極の長手方
向端部のドレインコンタクト領域からの距離を、ドレイ
ン電極の幅方向端部のドレインコンタクト領域からの距
離よりも長くしたことにより、いわゆるフィールドプレ
ートの効果により、ドレイン領域の長手方向先端部での
電界の集中を緩和し、ドレイン領域の長手方向先端部に
おけるドレイン・ソース間耐圧を向上することができ
る。As described above, according to the present invention, the elongated drain electrode is extended in the longitudinal direction, and the distance from the drain contact region at the end of the drain electrode in the longitudinal direction is defined as the drain at the end of the drain electrode in the width direction. By making it longer than the distance from the contact region, the so-called field plate effect reduces the concentration of the electric field at the tip of the drain region in the longitudinal direction and improves the breakdown voltage between the drain and source at the tip of the drain region in the longitudinal direction. can do.
【図１】この発明の一実施例の半導体装置の平面図であ
る。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.
【図２】この発明の一実施例の半導体装置のＡ−Ａ断面
図である。FIG. 2 is a sectional view taken along the line AA of the semiconductor device of the embodiment of the present invention.
【図３】この発明の一実施例の半導体装置のＢ−Ｂ断面
図である。FIG. 3 is a sectional view taken along line BB of the semiconductor device of the embodiment of the present invention.
【図４】この発明の一実施例におけるドレイン電極の先
端部の長さＬ1 とドレイン・ソース間耐圧との関係を示
す図である。FIG. 4 is a diagram showing the relationship between the length L 1 of the tip of the drain electrode and the drain-source breakdown voltage in one embodiment of the present invention.
【図５】従来の半導体装置の平面図である。FIG. 5 is a plan view of a conventional semiconductor device.
【図６】従来の半導体装置の断面図である。FIG. 6 is a cross-sectional view of a conventional semiconductor device.
１ ドレインコンタクト領域 ２ ドレイン領域 ３ ＰＴ領域（第１導電型領域） ４ シリコン基板（半導体基板） ５ チャンネル部 ６ ゲート酸化膜（ゲート絶縁膜） ７ ゲート電極 ８ ソース領域 ９ 高濃度第１導電型のチャンネルストッパ １０ 第１導電型の高濃度領域 １１ ソース電極 １２ａ ドレイン電極 １３ 層間絶縁膜 1 Drain contact region 2 Drain region 3 PT region (first conductivity type region) 4 Silicon substrate (semiconductor substrate) 5 Channel portion 6 Gate oxide film (gate insulating film) 7 Gate electrode 8 Source region 9 High concentration first conductivity type Channel stopper 10 High-concentration region of the first conductivity type 11 Source electrode 12a Drain electrode 13 Interlayer insulating film
Claims (2)
第２導電型のドレイン領域を形成し、前記ドレイン領域
上の内部に細長形状の高濃度第２導電型のドレインコン
タクト領域を介して細長形状のドレイン電極を形成し、
前記ドレイン領域上の前記ドレインコンタクト領域の周
囲に前記半導体基板と電気的に接続された第１導電型領
域を形成し、前記ドレイン領域の両側にチャンネル部を
介して第２導電型のソース領域を前記ドレイン領域の長
手方向と略平行に形成し、前記ドレイン領域の両側のソ
ース領域上にソース電極を形成し、前記チャンネル部の
上にゲート絶縁膜を介してゲート電極を形成し、前記細
長形状のドレイン電極はその輪郭が前記細長形状のドレ
インコンタクト領域の輪郭の外側になるように形成され
た半導体装置であって、 前記ドレイン電極を長手方向に延伸し、前記ドレイン電
極の長手方向端部の前記ドレインコンタクト領域からの
距離を、前記ドレイン電極の幅方向端部の前記ドレイン
コンタクト領域からの距離よりも長くしたことを特徴と
する半導体装置。1. An elongated second conductivity type drain region is formed on a first conductivity type semiconductor substrate, and an elongated high concentration second conductivity type drain contact region is provided inside the drain region. To form an elongated drain electrode,
A first conductivity type region electrically connected to the semiconductor substrate is formed around the drain contact region on the drain region, and a second conductivity type source region is formed on both sides of the drain region through a channel portion. The elongated shape is formed substantially parallel to the longitudinal direction of the drain region, the source electrodes are formed on the source regions on both sides of the drain region, and the gate electrode is formed on the channel portion via a gate insulating film. Is a semiconductor device formed such that the contour thereof is outside the contour of the elongated drain contact region, the drain electrode being extended in the longitudinal direction, and The distance from the drain contact region is set to be longer than the distance from the drain contact region at the widthwise end of the drain electrode. Characteristic semiconductor device.
コンタクト領域からの距離を２０μｍよりも長くした請
求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the distance from the drain contact region at the longitudinal end of the drain electrode is longer than 20 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06206415A JP3137840B2 (en) | 1994-08-31 | 1994-08-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06206415A JP3137840B2 (en) | 1994-08-31 | 1994-08-31 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0870118A true JPH0870118A (en) | 1996-03-12 |
| JP3137840B2 JP3137840B2 (en) | 2001-02-26 |
Family
ID=16522996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06206415A Expired - Fee Related JP3137840B2 (en) | 1994-08-31 | 1994-08-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3137840B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013254857A (en) * | 2012-06-07 | 2013-12-19 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method therefor |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010118419A (en) * | 2008-11-12 | 2010-05-27 | Sharp Corp | Semiconductor device |
| JP6092805B2 (en) * | 2014-04-03 | 2017-03-08 | 中村 弘之 | Acupressure aids |
| CN107546267A (en) * | 2016-06-29 | 2018-01-05 | 北大方正集团有限公司 | A kind of super-pressure lateral double diffusion metal oxide semiconductor structure and method |
-
1994
- 1994-08-31 JP JP06206415A patent/JP3137840B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013254857A (en) * | 2012-06-07 | 2013-12-19 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3137840B2 (en) | 2001-02-26 |
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