JP3201719B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a method of manufacturing a semiconductor device and its <br/>, and particularly to a power semiconductor device used for a power converter integrated circuit.

[0002]

2. Description of the Related Art In recent years, with an increase in the breakdown voltage of a power IC, an SOI (Sil) which can completely separate elements from each other by an insulating layer has been developed.
Attention has been focused on a power semiconductor device using an icon on insulator (icon) structure. Conventionally, as one type of power semiconductor device of this type, a lateral double-diffused MOS field-effect transistor as shown in FIG.
SFET (Lateral Double Diffu)
(sed MOSFET) is known. Here, FIG.
8A is a plan view of the LDMOSFET, and FIG.
18A is a sectional view taken along line XX ′ of FIG. 18A, and FIG. 18C is a sectional view taken along line YY ′ of FIG.

In this LDMOSFET, an N-type semiconductor layer 3 is formed on one surface of a semiconductor substrate 1 made of single crystal silicon via an insulating layer (so-called buried oxide film) 2, and on the main surface side of the semiconductor layer 3. N type (N ^{+ type} ) in the semiconductor layer 3
The drain region 4 and the P-type well region 5 are formed apart from each other, and an N-type (N ^{+ type} ) source region 6 is formed on the main surface side in the well region 5. Here, the drain region 4 and the well region 5 are formed apart from each other by such a distance that a predetermined breakdown voltage can be maintained. On the well region 5,
An insulating gate 7 for controlling a main current flowing in the semiconductor layer 3 between the drain region 4 and the source region 6 (for forming a so-called channel on the main surface side of the well region 5) is formed of an insulating film 8
And a drain electrode 41 on the drain electrode 4 and a source electrode (not shown) on the source region 6.
However, a gate electrode (not shown) is formed on each of the insulated gates 7. Here, the planar shape of the drain region 4 is formed into an oval shape having two linear portions whose outer circumferences are substantially parallel (similar to the planar shape of the drain electrode 41 shown in FIG. Region 6 is drain region 4
Is formed in a shape having two linear portions and two arc portions connecting the linear portions so that the distance between the LDMOSFETs is substantially constant.
ACK-shaped LDMOSFET).

Incidentally, in the above-mentioned ractrack-shaped LDMOSFET, it is necessary to increase the so-called gate width in order to flow a large current. Generally, as shown in FIG. 19, a plurality (n) of ractrack-shaped LDMOSFETs are adjacent to each other. The drain electrodes 41 _{1 to} 41 _n , the source electrode, and the gate electrode of each LDMOSFET are all connected to the main surface of the semiconductor layer 3 to form a group of LDMOSFETs that operate simultaneously, as shown in FIG. Thus, an LDMOSFET having a substantially comb-like planar shape is formed.

Here, the structure shown in FIG. 20 has the advantage that no special consideration is required for the wiring since the drain, source and gate regions are formed continuously, respectively. (For example, so-called RESURF
In order to maintain the breakdown voltage determined by the conditions, it is necessary to appropriately design the curvature of each curved portion, and therefore, the area of the unnecessary region 11 (where no element is formed) becomes large, and the area efficiency is poor. There is. Further, since the element formation region (so-called isolation island) is formed in a square shape in which the source region is inscribed, the presence of the unnecessary region 11 increases the area of the element formation region formed of the semiconductor layer 3. In addition, the parasitic capacitance formed between the semiconductor layer 3 and the semiconductor substrate 1 via the insulating layer 2 increases, and as a result, the LD
The switching time of the MOSFET becomes longer.
In contrast, the structure shown in FIG.
There is no need to consider the curvature for maintaining the breakdown voltage between the k-shaped LDMOSFETs, and since unnecessary regions are not generated, the LDM having a good area efficiency and a short switching time is used.
An OSFET can be configured.

[0006]

In the structure shown in FIG. 19, all the electrodes of each LDMOSFET need to be wired in parallel on the main surface of the semiconductor layer 3, and a circuit using a plurality of power LDMOSFETs is required. Even in a structure in which the blocks are integrated on one chip, all the electrodes of each LDMOSFET need to be wired on the main surface of the semiconductor layer 3. For this reason, the drain electrode wiring 41a electrically connected to the center electrode (the drain electrode 41 in this case) of the ractrack-shaped LDMOSFET extends to the outside (that is, so as to cross over the source region 6 and the well region 5). You. Here, the drain electrode 41 and the drain electrode wiring 4
1a is integrally formed.

[0007] However, the racetr shown in FIG.
In the ack-shaped LDMOSFET, the dimensions and concentration of the semiconductor layer 3 are designed so as to obtain a predetermined withstand voltage (although it is designed to satisfy, for example, the RESURF condition as one design standard). The drain electrode wiring 41 on the main surface of the semiconductor layer 3 via the insulating film 8.
When a is formed, the potential inside the semiconductor layer 3 is pulled below the drain electrode wiring 41a by the potential of the drain electrode wiring 41a, and as a result, the potential on the main surface of the semiconductor layer 3 is reduced as shown by a dashed line in FIG. There is a problem that the electric field is concentrated on the source region 6 side and electric field concentration occurs near the well region 5 below the insulating gate 7 to lower the breakdown voltage.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of increasing a withstand voltage with a small decrease in withstand voltage due to electric field concentration when an electrode wiring is formed, and a method of manufacturing the same. Is to do.

[0009]

According to a first aspect of the present invention, in order to achieve the above object, a semiconductor layer formed on an insulating layer is separated from the semiconductor layer on the main surface side of the semiconductor layer. A second conductivity type well region and a first conductivity type drain region, a first conductivity type source region formed in the well region, the source region and the drain region.
An insulating gate formed on the well region interposed between the region and a gate insulating film, a drain electrode formed on the drain region, a source electrode formed on the source region, a semiconductor device having a gate electrode connected to the insulated gate, a side opposite to the drain region side formed inside the insulating region of the semiconductor layer from the main surface of said semiconductor layer in said source area Or
Is extended to et the drain region end, the are those electrically connected to the drain electrode wiring to the drain electrode is characterized by comprising formed on the insulating region, the semiconductor layer below the drain electrode wiring Since the insulating region is formed, the potential of the drain electrode wiring does not disturb the distribution of the potential in the semiconductor layer, and a decrease in the withstand voltage due to the influence of the drain electrode wiring can be suppressed.

According to a second aspect of the present invention, in the first aspect of the invention, the source region, the well region, and the insulating gate are formed so as to surround the periphery of the drain region except for the insulating region. Since no insulated gate and well region are present, electric field concentration near the well region due to the influence of the potential of the drain electrode wiring does not occur, and a reduction in breakdown voltage can be suppressed.

According to a third aspect of the present invention, in the second aspect of the present invention, the insulating region is located between the main surface of the semiconductor layer and the inside of the semiconductor layer.
Since it is formed to the middle , the potential of the source is cut off.
Because it can be connected in the semiconductor layer between the edge region and the insulating layer,
It can be reliably terminated the source over scan reference potential, also under the drain electrode wiring can be suppressed decrease in breakdown voltage due to electric field concentration from being formed insulating region.

[0012] The invention of claim 4 is the invention of claim 2 or claim 3.
In the invention of the above, the insulated gate is only a predetermined length
Because it is extended , the insulating gate is
Acts as a potential source for the potential of the disconnected source region.
Since it can be connected to the easy, with cut with reliably terminate the source over scan reference potential, under drain electrode wiring insulation region
It is to decrease of breakdown voltage due to electric field concentration to which it is possible to suppress.

According to a fifth aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor layer formed on an insulating layer; a second conductivity type well region formed in the semiconductor layer on the main surface side of the semiconductor layer;
Wherein a drain region of the conductivity type, and the source region of the first conductivity type formed in the well region, the source region de
An insulated gate formed on the well region interposed between the rain region and a gate insulating film, a drain electrode formed on the drain region, and a source electrode formed on the source region; A gate electrode connected to the insulated gate; and a gate electrode formed above the well region.
An edge film and a front surface for separating each of the regions from an external device.
The element isolation region formed to the depth reaching the insulating layer
A semiconductor device comprising:
An insulating region at a portion between the well region and the drain region;
Is formed, and a drain electrically connected to the drain electrode is formed.
Rain electrode wiring is formed on the insulating region, on the insulating film, and on the insulating film.
The semiconductor device is formed so as to extend over the element isolation region , and the well region is cut by the insulating region.
The potential of the source is not continuously
So that the source reference potential can be firmly terminated
Insulation area and insulation under the drain electrode
Electric field concentration due to film and element isolation region formed
This can suppress a decrease in breakdown voltage.

According to a sixth aspect of the present invention, there is provided a semiconductor device comprising :
A semiconductor layer and a semiconductor layer on the main surface side of the semiconductor layer.
A well region of a second conductivity type formed at a distance from the first region;
A drain region of conductivity type and formed in the well region;
A source region of the first conductivity type;
A gate on the well region interposed between the rain region
An insulating gate formed through an insulating film, and the drain
A drain electrode formed on the region, and a
Connected to the source electrode formed at
Gate electrode, and each of the regions is isolated from an external device.
Element isolation formed to a depth that reaches the insulating layer
Region and from the element isolation region to the end of the drain region
An insulating region extending and formed thinner than the element isolation region;
A method of manufacturing a semiconductor device having a
An opening corresponding to the isolation region is formed and the insulating region
Photo with mask and window formed at predetermined intervals corresponding to
The element isolation region is formed by a LOCOS method using a mask.
Oxidizing the semiconductor layer until the region reaches the insulating layer
Characterized by having an acid in the insulating region.
The amount of oxygen supplied at the time of formation is smaller than the element isolation region
Therefore, the insulating region and the device isolation region, each having a different thickness,
Can be formed simultaneously, reducing the number of masks,
Shortening and cost reduction are possible.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1A shows an LDMOSF of this embodiment.
FIG. 1B is a plan view of the ET, FIG. 1B is a sectional view taken along line XX ′ of FIG. 1A, and FIG. 1C is a sectional view taken along line YY ′ of FIG.

The LDMOSFET of the present embodiment has a structure shown in FIG.
Similarly to the conventional LDMOSFET described in 1 above, a semiconductor layer 3 made of N-type silicon is formed on one surface of a semiconductor substrate 1 made of single-crystal silicon via an insulating layer (so-called buried oxide film) 2. Semiconductor layer 3 on the main surface side of
An N-type (N ^{+ -type} ) drain region 4 and a P-type well region 5 are formed separately from each other, and an N-type (N ^{+ -type} ) source region 6 is formed on the main surface side in the well region 5. Is formed.
Here, the drain region 4 and the well region 5 are formed apart from each other by such a distance that a predetermined breakdown voltage can be maintained.
On the well region 5, an insulating gate 7 for controlling a main current flowing in the semiconductor layer 3 between the drain region 4 and the source region 6 (for forming a so-called channel on the main surface side of the well region 5) is insulated. The drain region 4 formed through the film 8
A drain electrode 41 is formed thereon, a source electrode (not shown) is formed on the source region 6, and a gate electrode (not shown) is formed on the insulated gate 7.

Here, the planar shape of the drain region 4 is formed in an oval shape having two linear portions whose outer circumferences are substantially parallel, and the distance between the source region 6 and the well region 5 is substantially constant. The portion is formed around the drain region 4 except for a part. That is, the present LDMOSF
In the ET, an insulating region 13 having a thickness reaching the insulating layer 2 is formed around the lower part of the drain electrode wiring 41a in one arc portion of the racetrack shape, and the source region 6 and the well region 5 are cut at this portion. . Book LD
In the MOSFET, the thickness of the semiconductor layer 3 is small and the insulating region 1
3 is LOCOS (Local Oxidation of S)
It is made of a silicon oxide film formed by the silicon (ilicon) method, and is integrally formed with an element isolation region 12 made of a silicon oxide film formed from the main surface of the semiconductor layer 3 to the depth of the insulating layer 2 for element isolation.

Incidentally, the conventional LDMO shown in FIG.
In the SFET, since the drain electrode wiring 41a is wired above the semiconductor layer 3 via the insulating film 8, the potential of the drain electrode wiring 41a affects the peripheral semiconductor layer 3 below the drain electrode wiring 41a via the insulating film 8. In this case, the potential distribution of the semiconductor layer 3 is disturbed and electric field concentration occurs, and as a result, there is a problem that the breakdown voltage is reduced.

However, in this LDMOSFET,
Since the insulating region 13 is formed below the drain electrode wiring 41a, the potential distribution of the semiconductor layer 3 is as shown by a dashed line in FIG. 2, and the electric field concentration described in the conventional example does not occur. That is, in the LDMOSFET, since the potential of the semi <br/> conductor layer 3 is hardly affected by the potential of the drain electrode wiring 41a, the electric field concentration at the drain electrode wiring 41 down is suppressed, the withstand voltage due to electric field concentration Can be suppressed.

[0020] The plan view of the L DMOSFET of (Embodiment 2) This embodiment in FIG. 3 (a), the X-X 'cross-sectional view of FIGS. 3 (a) in FIG. 3 (b), FIG. 3
FIG. 3C is a sectional view taken along the line YY ′ of FIG. The basic configuration of the LDMOSFET of this embodiment is substantially the same as that of the first embodiment.
1a and the insulating region 13 are formed so as to be substantially perpendicular to the linear portion of the racetrack shape.

Incidentally, the LDMOSFET of the first embodiment
In this case, the angle between the well region 5 and the insulating region 13 on the main surface of the semiconductor layer 3 becomes acute, and the angle between the depletion layer (potential distribution) extending from the well region 5 and the insulating region 13 also becomes acute. In addition, the electric field at the interface between the insulating region 13 and the semiconductor layer 3 becomes higher than that in the semiconductor layer 3, and electric field concentration occurs near this interface, and the withstand voltage is slightly reduced.

On the other hand, in the present LDMOSFET, the well region 5 and the insulating region 1 are formed in the main surface of the semiconductor layer 3.
The angle formed between the semiconductor layer 3 and the semiconductor layer 3 is substantially a right angle, and the electric field distribution in this portion is substantially equal to the electric field distribution in the semiconductor layer 3. as a result,
Since the electric field concentration at the interface between the insulating region 13 and the semiconductor layer 3 is reduced, the withstand voltage is not reduced due to the electric field concentration inside the semiconductor layer 3 caused by the potential of the drain electrode wiring 41a. ) And the insulating region 13 can suppress a reduction in breakdown voltage caused by concentration of an electric field at the interface.

[0023] The plan view of the L DMOSFET of (Embodiment 3) In this embodiment in FIG. 4 (a), the X-X 'cross section of FIG. 4 (a) in FIG. 4 (b), FIG. 4
FIG. 4C shows a sectional view taken along line YY ′ of FIG. The basic configuration of the LDMOSFET of the present embodiment is substantially the same as that of the first embodiment, and is characterized in that the insulating region 13 formed simultaneously with the element isolation region 12 includes a well region 5, a source region 6, and an insulating gate 7. Is formed so as to extend to the arc portion of the drain region 4 so as not to be cut, and the drain electrode wiring 41 a is formed on the insulating region 13.

Incidentally, the LDMOSFET of the first embodiment
Now, the drain electrode wiring 4 wired on the insulating region 13
Although the electric field concentration just below 1 is suppressed and the decrease in the breakdown voltage is smaller than in the conventional example, the well region 5, the source region 6,
Since the insulating gate 7 is discontinuous in the portion where the insulating region 13 exists, the potential of the divided source cannot be completely coupled inside the insulating region 13 and the electric field concentrates near the interface between the insulating region 13 and the well region 5. However, as a result, the breakdown voltage is lower than when the drain electrode wiring 41a does not exist.

On the other hand, in the present LDMOSFET, since the discontinuous point of the well region 5 is eliminated, the potential of the source is continuously coupled in the well region 5.
Thus, the potential distribution as shown by the dashed line in FIG. 2 is obtained, and the electric field concentration near the interface between the insulating region 13 and the well region 5 does not occur. In addition, since the electric field concentration due to the drain electrode 41 also occurs in the insulating region 13, the critical electric field is higher than in the semiconductor layer 3, and the breakdown voltage is substantially the same as that when the drain electrode wiring 41a is not formed (for example, the voltage is optimized by the so-called RESURF condition). Withstand pressure).

[0026] The plan view of the L DMOSFET of the present embodiment (Embodiment 4) FIG. 6 (a), the X-X 'sectional view of FIG. 6 (a) in FIG. 6 (b), 6
FIG. 6C is a sectional view taken along line YY ′ of FIG. The basic configuration of the LDMOSFET of the present embodiment is substantially the same as that of the third embodiment. The feature of the LDMOSFET is that the insulating region 13 formed simultaneously with the element isolation region 12 has the well region 5 and the source That is, the region 6 and the insulated gate 7 are extended to the straight portion of the drain region 4 so as not to be cut, and the drain electrode wiring 41 a is formed on the insulating region 13.

By the way, the LDMOSFET of the third embodiment
In this case, the angle between the well region 5 and the insulating region 13 on the main surface of the semiconductor layer 3 becomes an acute angle, and the angle between the depletion layer (potential distribution) extending from the well region 5 and the insulating region 13 also becomes an acute angle. The electric field at the interface between the insulating region 13 and the semiconductor layer 3 is higher than that in the semiconductor layer 3, and electric field concentration occurs near this interface, and the withstand voltage is slightly reduced.

On the other hand, in the present LDMOSFET, the well region 5 and the insulating region 1 are formed in the main surface of the semiconductor layer 3.
The angle formed between the semiconductor layer 3 and the semiconductor layer 3 is substantially a right angle, and the electric field distribution in this portion is substantially equal to the electric field distribution in the semiconductor layer 3. as a result,
Since the electric field concentration at the interface between the insulating region 13 and the semiconductor layer 3 is reduced, the withstand voltage is not reduced due to the electric field concentration inside the semiconductor layer 3 caused by the potential of the drain electrode wiring 41a. ) And the insulating region 13 can suppress a reduction in breakdown voltage caused by concentration of an electric field at the interface.

[0029] The plan view of (Embodiment 5) L DMOSFET of the embodiment in FIG. 7 (a), the X-X 'sectional view of FIG. 7 (a) in FIG. 7 (b), FIG. 7
FIG. 7C shows a sectional view taken along the line YY ′ of FIG. The basic configuration of the LDMOSFET according to the present embodiment is substantially the same as that of the first embodiment, and is characterized in that the insulating region 13 is formed to a predetermined depth in the semiconductor layer 3 so as not to reach the insulating layer 2. 13 is formed on the drain electrode wiring 41a.

Incidentally, the LDMOSFET of the first embodiment
Now, the drain electrode wiring 4 wired on the insulating region 13
Although the electric field concentration just below 1 is suppressed and the decrease in the breakdown voltage is smaller than in the conventional example, the well region 5, the source region 6,
Since the insulating gate 7 is discontinuous in the portion where the insulating region 13 exists, the potential of the divided source cannot be completely coupled inside the insulating region 13 and the electric field concentrates near the interface between the insulating region 13 and the well region 5. However, as a result, the breakdown voltage is lower than when the drain electrode wiring 41a does not exist.

However, in this LDMOSFET,
The well region 5, the source region 6, and the insulating gate 7 are discontinuous at the insulating region 13, but a gap 18 made of the semiconductor layer 3 is formed between the insulating region 13 and the insulating layer 2. Therefore, both ends of the cut source region 6 are adjacent to each other via the gap 18, and the potential of the source is coupled in the gap 18, so that the potential distribution of the semiconductor layer 3 is shown by a dashed line in FIG. As a result, the occurrence of electric field concentration near the interface between the well region 5 and the insulating region 13 is suppressed. Also, since the electric field concentration due to the drain electrode wiring 41a occurs in the insulating region 13, the critical electric field is higher than in the semiconductor layer 3 and the breakdown voltage is substantially the same as when the drain electrode wiring 41a is not formed (for example, so-called RESURF
Withstand voltage optimized by the conditions) can be obtained.

[0032] The plan view of the L DMOSFET of the present embodiment (Embodiment 6) FIG. 9 (a), the X-X 'sectional view of FIG. 9 (a) in FIG. 9 (b), 9
FIG. 9C is a sectional view taken along line YY ′ of FIG. The basic configuration of the LDMOSFET of the present embodiment is substantially the same as that of the fifth embodiment.
That is, it is formed so as to be substantially perpendicular to the straight portion of the track shape. Here, a gap 18 made of the semiconductor layer 3 exists between the insulating region 13 and the insulating layer 2 as in the fifth embodiment.

Incidentally, the LDMOSFET of the fifth embodiment
In this case, the angle between the well region 5 and the insulating region 13 on the main surface of the semiconductor layer 3 becomes an acute angle, and the angle between the depletion layer (potential distribution) extending from the well region 5 and the insulating region 13 also becomes an acute angle. The electric field at the interface between the insulating region 13 and the semiconductor layer 3 is higher than that in the semiconductor layer 3, and electric field concentration occurs near this interface, and the withstand voltage is slightly reduced.

On the other hand, in the present LDMOSFET, the well region 5 and the insulating region 1 are formed in the main surface of the semiconductor layer 3.
The angle formed between the semiconductor layer 3 and the semiconductor layer 3 is substantially a right angle, and the electric field distribution in this portion is substantially equal to the electric field distribution in the semiconductor layer 3. as a result,
Since the electric field concentration at the interface between the insulating region 13 and the semiconductor layer 3 is reduced, the withstand voltage is not reduced due to the electric field concentration inside the semiconductor layer 3 caused by the potential of the drain electrode wiring 41a. ) And the insulating region 13 can suppress a reduction in breakdown voltage caused by concentration of an electric field at the interface.

(Embodiment 7) The present embodiment relates to a method of manufacturing an LDMOSFET according to Embodiments 5 and 6,
A method for simultaneously forming an element isolation region 12 formed to a depth reaching the insulating layer 2 as shown in FIG. 10 and an insulating region 13 formed to a part of the semiconductor layer 3 without reaching the insulating layer 2 will be described.

In the manufacturing method of this embodiment, a photomask 20 as shown in FIG. 12A is used as a mask in the LOCOS step. 12A and 12B, reference numeral 22 denotes a mask portion, and reference numeral 21 denotes a window portion. In the portion for forming the insulating region 13 in the mask portion 22, the mask portion 22 'and the window portion 21' are formed at a predetermined interval in parallel with each other as shown by a portion D in FIG. 1
The supply amount of oxygen to the semiconductor layer 3 is smaller than that of the window portion 21 for forming the semiconductor layer 2. For this reason, LO
By appropriately selecting the oxidation time of the COS oxidation step, the insulating region 13 and the element isolation region 12 can be formed simultaneously. Here, the window width H ₂ of the window portion 21 ′ and the mask width H ₁ of the mask portion 22 ′ in a portion D in the drawing are the oxide films (that is, the insulating regions 13) formed below each window portion 21. It is designed to connect with each other.

For example, when the semiconductor layer 3 having a thickness of 1 μm is completely oxidized by the pyrogenic oxidation method, it takes about 20 hours at 1100 ° C. including a margin.
In this case, in a region for forming the element isolation region 12, the window width of the window portion 21 is set to a window width (for example, 8 μm) capable of supplying a sufficient oxygen for the LOCOS oxide film to reach the insulating layer 2 under the above-described oxidation conditions. As described above, in the region for forming the insulating region 13, the supply of oxygen to the semiconductor
Window width H such that the COS oxide film stops in the middle of semiconductor layer 3
₂ (e.g., 4 [mu] m) To a mask width H ₁ of the mask portion 22 'adjacent the LOCOS oxide film leads width (e.g. 1.5 [mu] m) in the insulating region 13 and the isolation by using a photomask 20 Region 12 can be formed. Here, the sectional shape of the insulating region 13 is shown in FIG.
The thickness of the insulating region 13 is reduced in the portion covered by the mask portion 22 '.

As described above, according to the manufacturing method of this embodiment, LOCOS oxide films having different thicknesses can be simultaneously formed, so that the number of photomasks can be reduced.
The process can be shortened and the cost can be reduced. The plan view of the L DMOSFET of the present embodiment (Embodiment 8) FIG. 13 (a), the the X-X 'cross-sectional view shown in FIG. 13 (a) in FIG. 13 (b),
FIG. 13C is a sectional view taken along line YY ′ of FIG.

The basic structure of the present LDMOSFET is substantially the same as that of the fifth embodiment, and is characterized in that the insulated gate 7 overlaps the insulating region 13 below the drain electrode wiring 41a by a predetermined length. It has been extended. In the present LDMOSFET, the insulating gate 7 extended to the insulating region 13 functions as a so-called field plate, and the field potential of the insulating gate 7 more effectively reduces the source potential.
8, the source reference potential can be firmly terminated, and electric field concentration due to the drain electrode wiring 41a also occurs in the insulating region 13, so that the critical electric field is higher than in the semiconductor layer 3 and the withstand voltage is further improved. (For example, LDMOSF with a withstand voltage of about 500 volts)
In the case of ET, the withstand voltage is improved by about 50 volts by extending the insulating gate 7 to the insulating region 13 by about 5 μm).

[0040] The plan view of the L DMOSFET of this embodiment (Embodiment 9) FIG. 15 (a), the the X-X 'cross-sectional view shown in FIG. 15 (a) in FIG. 15 (b),
FIG. 15C is a sectional view taken along the line YY ′ of FIG.
The basic configuration of this LDMOSFET is substantially the same as that of the eighth embodiment.
It is formed so as to be substantially perpendicular to the straight portion of the track shape, and the drain electrode wiring 41a is formed thereon. Here, as in the eighth embodiment, the insulating gate 7 extends so as to overlap the insulating region 13 by a predetermined length.

Incidentally, the LDMOSFET of the eighth embodiment
In this case, the angle between the well region 5 and the insulating region 13 on the main surface of the semiconductor layer 3 becomes an acute angle, and the angle between the depletion layer (potential distribution) extending from the well region 5 and the insulating region 13 also becomes an acute angle. The electric field at the interface between the insulating region 13 and the semiconductor layer 3 is higher than that in the semiconductor layer 3, and electric field concentration occurs near this interface, and the withstand voltage is slightly reduced.

On the other hand, in the present LDMOSFET, the well region 5 and the insulating region 1 are formed in the main surface of the semiconductor layer 3.
The angle formed between the semiconductor layer 3 and the semiconductor layer 3 is substantially a right angle, and the electric field distribution in this portion is substantially equal to the electric field distribution in the semiconductor layer 3. as a result,
Since the electric field concentration at the interface between the insulating region 13 and the semiconductor layer 3 is reduced, the withstand voltage is not reduced due to the electric field concentration inside the semiconductor layer 3 caused by the potential of the drain electrode wiring 41a. ) And the insulating region 13 can suppress a reduction in breakdown voltage caused by concentration of an electric field at the interface.

[0043] The plan view of the L DMOSFET of this embodiment (Embodiment 10) FIG. 16 (a), the the X-X 'cross-sectional view shown in FIG. 16 (a) in FIG. 16 (b),
FIG. 16C is a sectional view taken along the line YY ′ of FIG.
The basic configuration of the present LDMOSFET is substantially the same as that of the first embodiment, except that the insulating gate 7 extends so as to overlap the insulating region 13 by a predetermined length (for example, 5 μm).

Therefore, in the present LDMOSFET, even if there is no region formed of the semiconductor layer 3 between the source regions 6 separated by the insulating region 13, the source potential is more effectively increased by the field plate effect of the insulating gate. Since the source potential can be connected in the insulating region 13, the source reference potential can be more securely terminated, and the electric field concentration due to the drain electrode wiring 41 a also occurs in the insulating region 13, so that the critical electric field is higher than in the semiconductor layer 3. It is high and the withstand voltage can be further improved (for example, in the case of an LDMOSFET with a withstand voltage of about 500 volts, the withstand voltage is improved by about 50 volts by extending the insulating gate 7 to the insulating region 13 by about 5 μm).

[0045] The plan view of (Embodiment 11) L DMOSFET of the embodiment in FIG. 17 (a), the X-X 'cross-sectional view shown in FIG. 17 (a) in FIG. 17 (b),
FIG. 17C is a sectional view taken along the line YY ′ of FIG.
The basic configuration of the present LDMOSFET is substantially the same as that of the tenth embodiment.
It is formed so as to be substantially perpendicular to the straight part of the track shape, and the drain electrode wiring 41a is formed thereon. Here, the insulated gate 7 is used in the tenth embodiment.
Similarly to the above, it extends so as to overlap the insulating region 13 by a predetermined length.

Incidentally, the LDMOSFE of the tenth embodiment
At T, the angle between the well region 5 and the insulating region 13 on the main surface of the semiconductor layer 3 is acute, and the angle between the depletion layer (potential distribution) extending from the well region 5 and the insulating region 13 is also acute. In addition, the electric field at the interface between the insulating region 13 and the semiconductor layer 3 becomes higher than that in the semiconductor layer 3, and electric field concentration occurs near this interface, and the withstand voltage is slightly reduced.

On the other hand, in the present LDMOSFET, the well region 5 and the insulating region 1 are formed in the main surface of the semiconductor layer 3.
The angle formed between the semiconductor layer 3 and the semiconductor layer 3 is substantially a right angle, and the electric field distribution in this portion is substantially equal to the electric field distribution in the semiconductor layer 3. as a result,
Since the electric field concentration at the interface between the insulating region 13 and the semiconductor layer 3 is reduced, the withstand voltage is not reduced due to the electric field concentration inside the semiconductor layer 3 caused by the potential of the drain electrode wiring 41a. ) And the insulating region 13 can suppress a reduction in breakdown voltage caused by concentration of an electric field at the interface.

[0048]

According to the first aspect of the present invention, the insulating region formed from the main surface of the semiconductor layer to the inside of the semiconductor layer is formed in the source region.
Drain from the side opposite to the drain region side in the region
Is extended to area end, since electrically connected to a drain electrode wiring drain electrode is formed on the insulating region, the semiconductor layer below the drain electrode wiring by being formed insulating region There is an effect that the potential of the drain electrode wiring does not disturb the distribution of the potential in the semiconductor layer, and a decrease in withstand voltage due to the influence of the drain electrode wiring can be suppressed.

According to a second aspect of the present invention, in the first aspect, the source region, the well region, and the insulating gate are formed so as to surround the periphery of the drain region except for the insulating region. Insulating gates and well regions do not exist, electric field concentration near the well region due to the influence of the potential of the drain electrode wiring does not occur, and a reduction in breakdown voltage can be suppressed.

According to a third aspect of the present invention, in the second aspect of the present invention, the insulating region extends from the main surface of the semiconductor layer in the semiconductor layer.
Since it is formed to the middle , the potential of the source is cut off.
Because it can be connected in the semiconductor layer between the edge region and the insulating layer,
It can be reliably terminated the source over scan reference potential, also under the drain electrode wiring has an effect that it is possible to suppress the decrease in breakdown voltage due to electric field concentration from being formed insulating region.

The invention of claim 4 is the invention of claim 2 or claim 3.
In the invention of the above, the insulated gate is only a predetermined length in the insulating region.
Because it is extended , the insulating gate is
Acts as a potential source for the potential of the disconnected source region.
Because it can be connected to the easy, with cut with reliably terminate the source over scan reference potential, under drain electrode wiring insulation region
There is an effect that a reduction in breakdown voltage due to electric field concentration to which it it is possible to suppress.

According to a fifth aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor layer formed on an insulating layer; a second conductivity type well region formed in the semiconductor layer on the main surface side of the semiconductor layer;
Wherein a drain region of the conductivity type, and the source region of the first conductivity type formed in the well region, the source region de
An insulated gate formed on the well region interposed between the rain region and a gate insulating film, a drain electrode formed on the drain region, and a source electrode formed on the source region; A gate electrode connected to the insulated gate; and a gate electrode formed above the well region.
An edge film and a front surface for separating each of the regions from an external device.
The element isolation region formed to the depth reaching the insulating layer
A semiconductor device comprising:
An insulating region at a portion between the well region and the drain region;
Is formed, and a drain electrically connected to the drain electrode is formed.
Rain electrode wiring is formed on the insulating region, on the insulating film, and on the insulating film.
It is formed over the element isolation region,
The well area is not cut by the insulating area and
Semiconductor potential can be continuously connected by the semiconductor layer.
The source reference potential can be firmly terminated,
Insulation area and insulation film and device isolation under drain electrode
Since the region is formed, reduction of the breakdown voltage due to electric field concentration
There is an effect that it can be suppressed .

According to a sixth aspect of the present invention , the semiconductor device is formed on an insulating layer.
A semiconductor layer and a semiconductor layer on the main surface side of the semiconductor layer.
A well region of a second conductivity type formed at a distance from the first region;
A drain region of conductivity type and formed in the well region;
A source region of the first conductivity type;
A gate on the well region interposed between the rain region
An insulating gate formed through an insulating film, and the drain
A drain electrode formed on the region, and a
Connected to the source electrode formed at
Gate electrode, and each of the regions is isolated from an external device.
Element isolation formed to a depth that reaches the insulating layer
Region and from the element isolation region to the end of the drain region
An insulating region extending and formed thinner than the element isolation region;
A method of manufacturing a semiconductor device having a
An opening corresponding to the isolation region is formed and the insulating region
Photo with mask and window formed at predetermined intervals corresponding to
The element isolation region is formed by a LOCOS method using a mask.
Oxidizing the semiconductor layer until the region reaches the insulating layer
Characterized by having an acid in the insulating region.
The amount of oxygen supplied at the time of formation is smaller than the element isolation region
Therefore, the insulating region and the device isolation region, each having a different thickness,
Can be formed simultaneously, reducing the number of masks,
This has the effect of enabling shortening and cost reduction .

[Brief description of the drawings]

FIG. 1A is a plan view showing a first embodiment,
(B) is a sectional view taken along line XX 'of (a), and (c) is a sectional view of Y of (a).
It is -Y 'sectional drawing.

FIG. 2 (a) is a potential distribution of a main part A of the above,
(B) is an explanatory view of a potential distribution of the main part B of the above.

FIG. 3A is a plan view showing a second embodiment,
(B) is a sectional view taken along line XX 'of (a), and (c) is a sectional view of Y of (a).
It is -Y 'sectional drawing.

FIG. 4A is a plan view showing a third embodiment,
(B) is a sectional view taken along line XX 'of (a), and (c) is a sectional view of Y of (a).
It is -Y 'sectional drawing.

FIG. 5 is an explanatory diagram of a potential distribution of a main part A of the above.

FIG. 6A is a plan view showing a fourth embodiment,
(B) is a sectional view taken along line XX 'of (a), and (c) is a sectional view of Y of (a).
It is -Y 'sectional drawing.

FIG. 7A is a plan view showing a fifth embodiment,
(B) is a sectional view taken along line XX 'of (a), and (c) is a sectional view of Y of (a).
It is -Y 'sectional drawing.

FIG. 8 (a) is a potential distribution of a main part A of the above,
(B) is an explanatory view of a potential distribution of the main part B of the above.

FIG. 9A is a plan view showing a sixth embodiment,
(B) is a sectional view taken along line XX 'of (a), and (c) is a sectional view of Y of (a).
It is -Y 'sectional drawing.

10A is a plan view of a semiconductor device according to a seventh embodiment, FIG. 10B is a sectional view taken along line XX ′ of FIG. 10A, and FIG. 10C is a sectional view taken along line YY ′ of FIG. is there.

FIG. 11 is an enlarged view of a main part A of the above.

FIG. 12A is an explanatory view of a photomask used for manufacturing the same as the above, and FIG. 12B is an enlarged view of a main part D of FIG.

FIG. 13A is a plan view showing Embodiment 8;
(B) is a sectional view taken along line XX 'of (a), and (c) is a sectional view of Y of (a).
It is -Y 'sectional drawing.

FIG. 14A is a diagram showing a potential distribution of a main part A of the above,
(B) is an explanatory view of a potential distribution of the main part B of the above.

FIG. 15A is a plan view showing Embodiment 9;
(B) is a sectional view taken along line XX 'of (a), and (c) is a sectional view of Y of (a).
It is -Y 'sectional drawing.

FIG. 16A is a plan view showing a tenth embodiment,
(B) is a sectional view taken along line XX 'of (a), and (c) is a sectional view of Y of (a).
It is -Y 'sectional drawing.

FIG. 17A is a plan view showing an eleventh embodiment,
(B) is a sectional view taken along line XX 'of (a), and (c) is a sectional view of Y of (a).
It is -Y 'sectional drawing.

FIG. 18A is a plan view showing a conventional example, and FIG.
Is a cross-sectional view taken along the line XX ′ of (a), and (c) is a line YY ′ of (a).
It is sectional drawing.

FIG. 19 is a schematic plan view showing another conventional example.

FIG. 20 is a schematic plan view showing another conventional example.

21 is an explanatory diagram of a potential distribution of a main part A in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating layer 3 Semiconductor layer 4 Drain region 5 Well region 6 Source region 7 Insulating gate 8 Insulating film 12 Element isolation region 13 Insulating region 41 Drain electrode 41a Drain electrode wiring

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuji Suzuki 1048 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Works, Ltd. Inventor ▲ Taka ▼ Hitoshi No 1048, Kazuma, Kadoma, Osaka Pref., Matsushita Electric Works, Ltd. (72) Inventor Takashi Kishida 1048, Kadoma, Oji, Kadoma, Osaka Pref. 1048 Kadoma Kadoma, Matsushita Electric Works, Ltd. (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 29/786 H01L 21/336

Claims (6)

(57) [Claims] 1. A semiconductor layer formed on an insulating layer, and a second conductivity type well region and a first conductivity type drain region formed separately in the semiconductor layer on a main surface side of the semiconductor layer. A source region of the first conductivity type formed in the well region, an insulated gate formed on the well region interposed between the source region and the drain region via a gate insulating film, A semiconductor device comprising: a drain electrode formed on the drain region; a source electrode formed on the source region; and a gate electrode connected to the insulated gate. the formed inside the insulating region of the semiconductor layer and the drain region side in the source <br/> area is extended from the opposite side to the de <br/> rain area end, electrically to said drain electrode Connected to The semiconductor device drain electrode wiring is characterized by comprising formed on the insulating region. 2. The semiconductor device according to claim 1, wherein the source region, the well region, and the insulating gate are formed so as to surround the drain region except for the insulating region. 3. The semiconductor device according to claim 1 , wherein the insulating region is semiconductive from a main surface of the semiconductor layer.
3. The semiconductor device according to claim 2 , wherein the semiconductor device is formed halfway in the body layer . 4. An insulating gate extends a predetermined length into an insulating region.
The semiconductor device according to claim 2 , wherein the semiconductor device is provided. 5. A semiconductor layer formed on an insulating layer, and a well region of a second conductivity type and a drain region of a first conductivity type formed separately in the semiconductor layer on the main surface side of the semiconductor layer. A source region of the first conductivity type formed in the well region, an insulated gate formed on the well region interposed between the source region and the drain region via a gate insulating film, A drain electrode formed on the drain region, a source electrode formed on the source region, and a gate electrode connected to the insulated gate ;
An insulating film formed above the well region;
Reaches the insulating layer to isolate the region from external devices
Semiconductor device having element isolation region formed to depth
Wherein the well region in the semiconductor layer and the well region
An insulating region is formed at a portion between the drain region and the drain region.
Electrical-connected drain electrode wiring to the drain electrodes thereof
On the insulating region, on the insulating film, on the element isolation region,
A semiconductor device characterized by being formed over a semiconductor device. 6. A semiconductor layer formed on an insulating layer;
Formed at a distance from the main surface of the semiconductor layer in the semiconductor layer.
Well region of the second conductivity type and drain of the first conductivity type
Region and a first conductivity type source formed in the well region.
Source region, and between the source region and the drain region.
Formed on the well region interposed by a gate insulating film.
Formed on the insulated gate and the drain region
Drain electrode, and a saw formed on the source region.
A gate electrode connected to the insulated gate,
An insulating layer for isolating each of the regions from an external device;
An element isolation region formed to a depth reaching
An element extending from an isolation region to an end of the drain region;
Semiconductor with insulating region formed thinner than isolation region
A method of manufacturing a body device, the method comprising:
Opening is formed and corresponds to the insulating region.
Using a photomask with windows formed at predetermined intervals
The element isolation region is formed in the insulating layer by the LOCOS method.
It has a step of oxidizing the semiconductor layer until it reaches
A method for manufacturing a semiconductor device.