JPH085562Y2 - 表面実装部品 - Google Patents
表面実装部品Info
- Publication number
- JPH085562Y2 JPH085562Y2 JP1989058262U JP5826289U JPH085562Y2 JP H085562 Y2 JPH085562 Y2 JP H085562Y2 JP 1989058262 U JP1989058262 U JP 1989058262U JP 5826289 U JP5826289 U JP 5826289U JP H085562 Y2 JPH085562 Y2 JP H085562Y2
- Authority
- JP
- Japan
- Prior art keywords
- horizontal
- horizontal portion
- mold resin
- lead body
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000011347 resin Substances 0.000 claims description 22
- 229920005989 resin Polymers 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 229910000679 solder Inorganic materials 0.000 description 17
- 238000005476 soldering Methods 0.000 description 9
- 230000000630 rising effect Effects 0.000 description 6
- 238000000465 moulding Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989058262U JPH085562Y2 (ja) | 1989-05-19 | 1989-05-19 | 表面実装部品 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989058262U JPH085562Y2 (ja) | 1989-05-19 | 1989-05-19 | 表面実装部品 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0349U JPH0349U (en, 2012) | 1991-01-07 |
| JPH085562Y2 true JPH085562Y2 (ja) | 1996-02-14 |
Family
ID=31583712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989058262U Expired - Fee Related JPH085562Y2 (ja) | 1989-05-19 | 1989-05-19 | 表面実装部品 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH085562Y2 (en, 2012) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60145825U (ja) * | 1984-03-06 | 1985-09-27 | 株式会社 六▲よう▼社 | 袋吊り下げ具 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57176751A (en) * | 1981-04-22 | 1982-10-30 | Toshiba Corp | Semiconductor device |
| JPS59145554A (ja) * | 1984-02-03 | 1984-08-21 | Hitachi Ltd | 複数個の端子を有する電子部品 |
| JPS6371551U (en, 2012) * | 1986-10-29 | 1988-05-13 | ||
| JPS63151058A (ja) * | 1986-12-16 | 1988-06-23 | Matsushita Electronics Corp | 樹脂封止型半導体装置 |
-
1989
- 1989-05-19 JP JP1989058262U patent/JPH085562Y2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0349U (en, 2012) | 1991-01-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |