JPH0850166A - Semiconductor inspection device - Google Patents

Abstract

PURPOSE:To provide an inspection device which is enhanced in speed, and can be developed in a short period at relatively low cost. CONSTITUTION:This device has a pattern generator 1 having a test pattern program stored therein, and a processing means 3 for reading, decoding and executing the test pattern program stored in the pattern generator 1 in parallel through a control means 2. Further, it has a memory device 5 which preliminarily stores, when the test pattern program is not executed in an address order but discontinuously executed because a command such as jump command is contained, the address before the discontinuation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor inspection device.

[0002]

2. Description of the Prior Art Referring to FIGS. 4 and 5,
A conventional semiconductor inspection device will be described. FIG. 4 is a flow chart in the case of performing a function inspection of the semiconductor device, and FIG. 5 is a configuration diagram of the semiconductor inspection device.

When performing a function test of a semiconductor device with a conventional semiconductor test device, as shown in the flow of FIG. 4, in order to execute a command for one address of a pattern program, the command is read, the command is decoded, and the command is read. The instructions are executed in order.

The structure and operation for executing this flow will be described. As shown in FIG. 5, the CPU or the instruction is read from the test pattern program stored in the pattern generator 1 one by one address via the control circuit 2. The circuit 3 reads the instruction, and the CPU or the circuit 3 that decodes and executes the instruction decodes the instruction and then instructs the measurement circuit 4 to execute the instruction.
Further, the CPU or the circuit 3 for reading, decoding and executing the instruction determines the address to be executed next by feeding back the decoded instruction content to the pattern generator 1.

[0005]

In the conventional semiconductor inspection apparatus, even if there are a plurality of instructions to be processed, it is necessary to perform the above processes one by one. Therefore, when inspecting a semiconductor device that operates at a very high frequency, that is, a so-called high-speed operation, in order to guarantee a high-speed operation, use an inspection device that generates a high-frequency signal,
Thereby, the comparison judgment was performed.

However, many semiconductor inspection devices that generate high frequency signals are very expensive at present, and it takes a long time to develop and produce such inspection devices. there were.

In view of the above problems, it is an object of the present invention to provide an inspection apparatus capable of inspecting a high-speed operation semiconductor device, cheaper than the conventional one, and capable of being developed and produced in a short period of time. To do.

[0008]

In order to achieve the above object, a semiconductor inspection apparatus of the first invention controls a pattern generator storing a test pattern program and a test pattern program stored in the pattern generator. Via means, read in parallel, decrypt,
When the test pattern program includes instructions such as a jump instruction and is executed discontinuously without being executed in the address order, the storage device prestores the addresses in which the jump instructions and the like are described. When the address stored in the device is read into the processing means, the instruction described in the jump destination address is read and processed as the next parallel processing.

The semiconductor inspection apparatus according to the second aspect of the present invention reads the pattern generator storing the test pattern program and the test pattern program stored in the pattern generator in parallel via the control means and decodes them. If the processing means to be executed and the test pattern program are executed discontinuously without being executed in the order of addresses including instructions such as jump instructions, the address immediately before the address in which the jump instructions are described and the address of the jump destination When a pre-jump address stored in the storage device is read into the processing means, the instruction described in the jump destination address using the stored contents of the storage device as the next parallel processing. Is read and processed.

[0010]

As described above, by providing the storage device for storing the execution address order of the pattern program,
It is possible to avoid the processing disturbance due to the discontinuous change of the execution address when the instruction is read.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. In the present invention, in order to perform a plurality of instruction processings at high speed, the instruction processing which has been performed one by one in the prior art is processed in parallel by using the inspection device shown in FIG.
As a result, high-speed processing is realized.

FIG. 1 is a diagram showing a processing cycle when parallel processing of a plurality of instructions is performed by using the semiconductor inspection apparatus according to one embodiment of the present invention, and FIG. 2 is a parallel processing performed by using a conventional semiconductor inspection apparatus. FIG. 3 is a diagram of a processing cycle in the case, and FIG. 3 is a configuration diagram of a semiconductor inspection apparatus in one embodiment of the present invention.

In FIG. 1, "read" indicates an instruction read cycle, "solution" indicates an instruction decode cycle, and "actual" indicates an instruction execution cycle. All these cycles have the same length.

The system 1, system 2, and system 3 show three instruction processing systems, each of which performs processing in the same cycle as that of the conventional semiconductor inspection apparatus of reading an instruction, decoding an instruction, and executing an instruction. These processing systems start operations in the order of 1, 2 and 3 by the length of the instruction read cycle, and operate in parallel, so that the pattern program is apparently executed as shown in system 4. You can At this time,
In the system 1, the system 2, and the system 3, when the system 1 reads the instruction at the address k, the system 2 reads the instruction at the address (k + 1), and the system 3 reads the instruction at the address (k + 2). Further, thereafter, the system 1 repeats the instruction at the address (k + 3) in the order of reading. In this way, when the description order of the pattern program and the order of the addresses to be executed match, parallel processing can be performed without any problem.

However, when the pattern program is not described according to the execution address but the execution address sequence is discontinuously described by, for example, a subroutine, a loop, or a jump instruction, the following problem occurs. There is. FIG. 2 shows a processing cycle in which processing is performed using a conventional semiconductor inspection apparatus in such a case.

If the system 1 reads the instruction at the address k, the system 2 reads the instruction at the address (k + 1), and the system 3 reads the instruction at the address (k + 2). If the instruction read by the system 1 is a jump instruction to the address n, the system 2 must read the instruction at the address n and the system 3 at the address (n + 1) again after decoding the jump instruction of the system 1. , And the system 2'and system 3 ', respectively, and the processing timing is shifted by the amount of re-reading. Therefore, as shown in the system 4, the disturbance appears in the entire instruction processing cycle.

FIG. 3 shows the configuration of the semiconductor inspection apparatus of the present invention for avoiding this. In the figure, the same components as in the prior art are designated by the same reference numerals and the description thereof will be omitted. The present embodiment is different from the conventional one in that a storage device 5 is newly provided. This memory device 5 is an address where the execution address order changes discontinuously among the pattern programs described in the above discontinuous address (address) order when the semiconductor inspection device once reads the pattern program. The immediately preceding address (for example, the address describing the jump instruction) is stored in advance. The storage device may be, for example, a cache memory or a file on a hard disk.

With this configuration, when the CPU or the circuit 3 for reading, decoding, and executing an instruction reads the instruction from the pattern generator 1, the storage device 5 sends the stored address value to the control circuit 2. The control circuit 2 prevents the disturbance in the entire processing cycle when the sent address value is the address currently accessed by the CPU or the circuit 3 for reading an instruction.
The address of the jump destination is read from the instruction content described in this address (in this case, the jump instruction), and control is performed so that the next processing system can immediately access the address of the jump destination (after the discontinuous change). The CPU or the circuit 3 for reading the instruction reads the instruction from the address accessed by the control circuit 2.

By operating in this way, it is possible to avoid the re-reading of the instruction as in the conventional case and avoid the disturbance of the entire processing cycle, and apparently the high-speed processing as shown in the system 4 of FIG. 1 becomes possible. Moreover, as shown in FIG. 3, since it can be realized by simply adding the storage device 5 as compared with the conventional configuration, it is possible to inexpensively develop and produce the inspection device itself in a short period of time.

In this embodiment, the address in which the jump instruction is described is stored in the storage device. However, the present invention is not limited to this, and the address immediately before the address in which the jump instruction is described is stored. You may stay. However, in this case, the jump destination may not be known. Therefore, it is preferable to store the jump destination address in the storage device in advance and read both the addresses before and after the jump from the storage device. . Further, even when the address describing the jump instruction is stored as in the present embodiment, the address of the jump destination may also be stored in the storage device and used.

[0021]

By using the semiconductor inspection apparatus of the present invention, it becomes possible to inspect semiconductor devices operating at high speed.
Further, since this inspection device can be realized by adding a slight improvement to the conventional inspection device, it can be relatively inexpensively developed and produced in a short period of time.

[Brief description of drawings]

FIG. 1 is a diagram of a processing cycle for executing a pattern program of a semiconductor inspection device according to the present invention.

FIG. 2 is a diagram for explaining the disturbance of the processing cycle when the pattern programs are not described in the order of execution addresses.

FIG. 3 is a schematic view of a semiconductor inspection device of the present invention.

FIG. 4 is a diagram showing a processing cycle at the time of executing a pattern program of a conventional semiconductor inspection device.

FIG. 5 is a schematic diagram of a conventional semiconductor inspection device.

[Explanation of symbols]

1 pattern generator 2 control circuit 3 circuit for reading, decoding and executing CPU or instruction 4 measurement circuit 5 storage device

Claims (2)

[Claims] 1. A pattern generator that stores a test pattern program, and a processing unit that reads, decodes, and executes the test pattern program stored in the pattern generator in parallel via a control unit.
When the test pattern program includes instructions such as jump instructions and is executed discontinuously without being executed in the order of the addresses, the test pattern program is provided with a storage device in which the addresses in which the jump commands and the like are described are stored in advance, and stored in the storage device. The semiconductor inspection device, wherein when the read address is read into the processing means, the instruction described in the jump destination address is read and processed as the next parallel processing. 2. A pattern generator that stores a test pattern program, and a processing unit that reads, decodes, and executes the test pattern program stored in the pattern generator in parallel via a control unit.
When the test pattern program includes instructions such as jump instructions and is executed discontinuously without being executed in the order of the addresses, the address immediately before the address in which the jump instructions are described and the address of the jump destination are stored in advance. When a pre-jump address stored in the storage device is read into the processing means, the instruction described in the jump destination address using the stored contents of the storage device as the next parallel processing is provided. A semiconductor inspection device characterized by reading and processing.