JPH05257686A - Instruction cache circuit - Google Patents

Abstract

PURPOSE:To shorten an execution time of a condition branch instruction by constituting the circuit so that an address tag for executing a cache index can be referred to independently from an address tag for executing a cache index for an instruction prefetch processing. CONSTITUTION:In the case where a decoded instruction is a branch instruction, a branch destination address is calculated by an address calculating circuit 110. In the case this branch instruction is an unconditional branch, the branch destination address is sent to a prefetch address generating circuit 106, and immediately, switching of an instruction fetch address is executed. Subsequently, in the case where the branch instruction is a conditional branch, the branch destination address generated by the address calculating circuit 110 is decided as to be hit/mishit of a cache by a tag memory 101 and a hit deciding circuit 102. In the case of being a hit, read-out of an instruction word is executed from a cache data memory 107 at the time point when a branch in a branch condition deciding circuit 111 is decided definitely.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction cache circuit, and more particularly to an instruction cache circuit in an information processing device for pipeline control.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration example of a conventional instruction cache circuit.

The prefetch address output from the prefetch address circuit 106 for generating the fetch address of the instruction word is supplied to the address tag memory 131 and the cache data memory 107. The tag information read from the address tag memory 131 is compared with a part of the prefetch address supplied from the prefetch address generation circuit 106 in the hit determination circuit 132.

When the cache is hit, the content read from the cache data memory 107 which is referred to in parallel with the address tag memory of the prefetch address generation circuit 106 is stored in the prefetch queue 108. The contents of the prefetch queue 108 are sequentially taken out, and the instruction decoding circuit 109 decodes the instruction word to execute the instruction operation.

Although the instruction word prefetch operation and the instruction execution are usually performed asynchronously, when the branch instruction is executed, the instruction flow is switched and the prefetch address is switched to the branch destination address.

In this operation, the address calculation circuit 110 calculates the branch destination address from the content of the instruction word decoded by the instruction decode circuit 109, and the prefetch
This is performed by transferring to the address generation circuit 106. The instruction word prefetch operation continues from the address thus switched.

[0007]

In this instruction cache circuit, when the information processing device performs pipeline control, particularly when the number of pipeline stages is deep,
The timing at which the branch condition of the conditional branch instruction is determined by the determination circuit 111 is the address calculation circuit 110 of the branch destination address.
Often it will be later than the timing determined by. For this reason, in the prefetch address generation circuit 106, regarding the instruction prefetch operation, whether to continue the non-branching side or switch to the branch destination side must be performed when the branch condition is undetermined.

When the branch side is selected, since fetching of the branch side instruction is started in the state where the non-branch side instruction remains in the queue, there is a problem that control after the branch condition is fixed becomes complicated. On the other hand, if the fetching of the non-branching side is continued, there is a problem that the fetching of the branch target instruction is delayed after the branch condition is determined.

[0009]

The circuit of the present invention is a cache for performing a cache search for a prefetch address of an instruction word following an instruction being executed in an instruction cache circuit in an information processing device for prefetching an instruction word. The tag memory means, the hit determination means, the cache tag memory means for performing a cache search for the instruction word of the branch destination address of the conditional branch instruction, and the hit determination means are independently provided.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

The instruction fetch address output from the prefetch address generation circuit 106 is supplied to the address tag memory 103, the cache data memory 107, and the bit determination circuit 104.

When the instruction fetch target address hits the cache, the contents read from the cache data memory 107 are stored in the prefetch queue 108. When there is a miss in the cache, the block load request generation circuit 105 outputs a load request to the external memory system 112, and the returned data is stored in the cache data memory 107 and also in the prefetch queue 108. ..

The instruction words stored in the prefetch queue 108 are sequentially sent to the instruction decoding circuit 109, and the instruction words are decoded.

If the decoded instruction is a branch instruction, the address calculation circuit 110 calculates the branch destination address. If this branch instruction is an unconditional branch, the branch destination address is the prefetch address generation circuit 1
Then, the instruction fetch address is switched immediately.

Next, the case where the branch instruction is a conditional branch will be described. In the case of an information processing device that executes an instruction under pipeline control, the timing for determining the branch condition is often delayed from the timing for determining the branch destination address of the conditional branch instruction. Now, the prefetch address generation circuit 10
In 6, the generation of the address on the non-branching side is continued.

The branch destination address generated by the address calculation circuit 110 is the tag memory 101 and the hit determination circuit 10.
At 2, the cache hit or miss hit is determined. If there is a hit, when the branch in the branch condition determination circuit 111 is confirmed, the cache data memory 10
The instruction word is read from 7. On the other hand, in the case of a mishit, the hit determination circuit 102 notifies the block load request generation circuit 105 that the block load request generation circuit 105 notifies the external memory system 112.
A block load request is output.

There is a difference in control method depending on whether the timing of outputting the block load request is before or after the decision of the branch condition in the address calculation circuit 110, but in the present invention, either may be used. Absent. In the method of issuing the block load request before the condition is fixed, the data returned from the external memory system 112 will be ignored if the branch condition is not satisfied.

FIG. 2 shows another embodiment of the present invention. In the embodiment of FIG. 1, two address tag memories 103 for normal instruction word prefetching and two address tag memories 101 for branch destination address index are provided independently, but in the present embodiment, the address tag memory 121 is provided. Is realized with one 2-port memory. Other operations are the same as those in the first embodiment described above.

[0020]

As described above, according to the present invention, when a conditional branch instruction is executed, the address tag which performs the cache index of the instruction word of the branch destination address performs the cache index for the normal instruction prefetching process. By making it possible to refer to the address tag independently, it is possible to judge the cache hit or miss hit of the branch target instruction word, and output the block load request to the external memory at an early timing, and to improve the execution time of the conditional branch instruction. It has the effect that it can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of another embodiment of the present invention.

FIG. 3 is a block diagram of a conventional configuration example.

[Explanation of symbols]

101, 103, 121, 131 Address tag memory 102, 104, 132 Hit determination circuit 105 Block load request generation circuit 106 Prefetch address generation circuit 107 Cache data memory 108 Prefetch queue 109 Instruction decode circuit 110 Address calculation circuit 111 Branch condition determination circuit 112 External memory system

Claims (2)

[Claims] 1. An instruction cache circuit in an information processing apparatus for prefetching an instruction word, comprising: cache tag memory means for performing a cache search of a prefetch address of an instruction word following an instruction being executed; and hit determining means thereof. An instruction cache circuit having cache tag memory means for performing a cache search for an instruction word of a branch destination address of a conditional branch instruction and hit determining means thereof independently. 2. The instruction cache circuit according to claim 1, wherein the two cache tag memory means are realized by a memory having a plurality of read ports.