JPH08339986A - Wiring-structure forming method with connection-hole forming process - Google Patents

Abstract

PURPOSE: To provide a wiring-structure forming method whereby a highly reliable connection-hole can be formed by an easy process. CONSTITUTION: In a wiring-structure forming method with a process wherein a wiring 2 is formed on a substrate and a connection-hole with the wiring 2 is formed, a material layer for forming the wiring 2 is formed on the substrate, and on the upper layer thereof, a material layer for forming a cap layer 4 is formed, and further, this cap layer 4 is formed in the form of a forward taper, and then, a patterning for forming the wiring 2 is performed, and moreover, the connection-hole is formed to the wiring 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a wiring structure having a step of forming connection holes. INDUSTRIAL APPLICABILITY The present invention can be used in the field of various electronic materials and the like having a wiring structure having a step of forming a connection hole, and can be used, for example, as a method for forming a wiring structure in manufacturing a semiconductor device.

[0002]

2. Description of the Related Art The wiring of a semiconductor integrated circuit is being miniaturized, but the alignment accuracy between layers (interlayers) of a lithography apparatus for patterning (so-called reduction projection exposure apparatus called a stepper) Are said to be approaching their limits.

Conventionally, for alignment, for example, a contact hole pattern is 0.2 μm from a wiring pattern _.
A thickening pattern called a "cushion" was provided in the underlying wiring pattern so that it can be covered even if it is misaligned by about m.
Even if there is a gap between the patterns, the gap is absorbed in the thickened portion, and the connection is guaranteed. However, this "cushion" pattern limits the miniaturization of the contact pitch. At the same time, with the miniaturization, it becomes difficult to resolve the "cushion" pattern itself.

For this reason, a technique called overlapless contact has been actively developed.

This overlapless contact technology eliminates the "cushion" pattern from the wiring pattern, and even if the misalignment with the via hole pattern occurs, the contact hole etching does not come off the wiring or stops on the wiring. It was developed for the purpose of doing.

As such an improved technique, for example, as shown in FIG. 7, after forming a metal wiring 2 ', for example, an Al wiring, a sidewall 1a is formed on the sidewall by an insulating material, and an interlayer film 5'made of SiO ₂ is formed. There is a method for processing the via contact with respect to the condition using a high selection ratio of SiO ₂ and the third wall material. According to this, even if the via contact pattern is misaligned, the hole can be stopped by the sidewall 1a like the via hole 3 shown in FIG. 7B.

However, the width of the side wall 1a cannot be made so thick, and since the side wall 1a has a slope, it is etched into a groove having a high aspect ratio as shown by reference numeral 1b in FIG. 8 (a). Often progresses. Via hole 3 having such a groove 1b
Even if is embedded with a conductive material, the embedding becomes defective. For example, as shown in FIG. 8B, when blanket tungsten (hereinafter also referred to as Blk-W) 9a is embedded through the adhesion layer 8a, Blk-as shown by reference numeral 9b in FIG. 8B. W filling failure occurs.

As another method, there is also a method of opening the via contact in a forward taper and narrowing the bottom of the hole to cover the misalignment. However, in this method, it is necessary to make the diameter of the hole bottom extremely small, such as 0.1 μm, so there is a problem in that ohmic contact can be obtained from all the millions of via contacts.

It is conceivable to form the entire wiring pattern of Al or the like thickly by lithography so that the stepper can cover the misalignment, but the resolution of the space and the depth of focus DOF (Depth of Focus) margin are lost. It is difficult to adopt the means.

It is desired to develop a method for solving these problems, realizing the process in an easy process, and inexpensively, that is, forming the overlapless via hole by a method which does not increase the equipment investment and the number of processes.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the prior art, and provides a method of forming a wiring structure having a connection hole forming step capable of forming a highly reliable connection hole by an easy process. The purpose is to do.

[0012]

According to the present invention, there is provided a wiring structure forming method including a step of forming a wiring on a substrate and forming a connection hole for connecting to the wiring.
A wiring forming material layer and a cap layer forming material layer are formed on the wiring forming material layer, the cap layer is formed into a tapered shape, patterning is performed to form wiring, and a connection hole is formed for this wiring. A method of forming a wiring structure, which comprises a step of forming a connection hole, which achieves the above object.

In this case, the wiring material is an aluminum-based material, and in etching the aluminum-based material,
The cap layer portion may be processed using a gas having a Cl ₂ gas flow rate ratio of 20% or less.

Further, the wiring material is an aluminum-based material, and in the etching of the aluminum-based material, Br
The cap layer portion can be processed by using a gas containing 10% or more of a gas containing the above.

[0015]

According to the present invention, since the cap layer forming material layer is formed on the wiring forming material layer and the upper layer thereof, and the cap layer is formed in a taper shape, the patterning for forming the wiring is performed. The taper shape expands the lower part, and thus the wiring becomes thicker than the mask pattern such as the resist pattern by the taper downward spread. Therefore, by doing this, you can afford this spread,
With respect to the subsequent opening of the connection hole (via hole), the connection hole is prevented from coming off from the wiring.

[0016]

EXAMPLES Examples of the present invention will be described in detail below. However, needless to say, the present invention is not limited by the following examples.

Example 1 In this example, the present invention is applied to a method of forming a wiring structure including a step of forming a connection hole in a semiconductor device having a miniaturized and integrated Al wiring. Please refer to FIG. 1 to FIG.

In this embodiment, the wiring 2 is formed on the substrate 1, and the connection hole 3 for connecting to the wiring 2 is formed (FIG. 3). Then, the wiring forming material layer 2a and the cap layer forming material layer 4a are formed on the wiring forming material layer 2a (FIG. 1), and the cap layer 4 is formed in a tapered shape (forward taper shape) as shown in FIG.
The wiring is patterned to form a connection hole in the wiring (FIG. 3).

More specifically, this embodiment is an embodiment of the present invention for forming a via hole of a semiconductor device, particularly a VLSI, and covers misalignment of a stepper without providing a cushion pattern for misalignment. In order to achieve this, the Al wiring Blk-W plug cap layer 4 (Ti
The N layer) was processed into a forward taper of 45 ° or more (FIG. 2), and a via hole was opened thereon (FIG. 3). In this embodiment, the forward taper angle is 46 °, but
The angle of 45 ° or more is set so that the wiring width (here, the Al line width) is thickened by 0.1 μm on each side.

This embodiment will be described more specifically below.

Transistors, capacitors and PolyS
A laminated film having the following structure is deposited by sputtering as a first layer Al wiring on the substrate 1 on which the i wiring and the W plug have been formed. TiN / Al-0.5% Cu / TiN / Ti = 100/500/20/20 nm The formed TiN layer is a cap layer forming material layer, which is indicated by reference numeral 4a. The Al-Cu layer is a wiring forming material layer, which is indicated by reference numeral 2a. Reference numerals 71 and 72 denote a TiN layer and a Ti layer, respectively, which form a barrier layer.

By the photolithography technique,
An Al wiring forming pattern is formed with a photoresist. The resist pattern is shown by reference numeral 6. At this time, the pattern has a minimum space of 0.4 μm, and a cushion for misalignment between the via hole and the Al wiring pattern is not provided (FIG. 1). In FIG. 1, 10a and 10b are poly S, respectively.
The i layer and the silicide (especially W silicide) layer form a polysilicide gate structure. Reference numeral 11 is a W plug for making contact with the diffusion layer of the underlying Si substrate 1, which is a CVD-SiO that is the interlayer insulating film 5.
It is formed in _two layers.

Next, the Al wiring 2 is processed by the μ-wave plasma Al etcher using the resist pattern 6 formed above as a mask. The etching conditions were the following two-step conditions. First step gas flow rate BCl ₃ / Cl ₂ = 160/40 sccm Pressure 1067 Pa RF power 100 W (2 MHz) Etching time 20 sec (Time required for TiN layer etch-off on 200 mm wafer) Second step gas flow rate BCl ₃ / Cl ₂ = 80 / 120 sccm Pressure 1067 Pa RF power 100 W (2 MHz) Etching time 100 sec (corresponding to 40% over-etching for the entire film on a 200 mm wafer) 1st and 2nd step Common conditions μ-wave magnetron current 350 mA Substrate temperature 20 ° C

As described above, in the present embodiment, in the first step, the Al-based material was etched under the condition of using the gas having the Cl ₂ flow rate ratio of 20% or less. By processing under these conditions, the uppermost cap layer forming material layer 4a made of TiN is processed into a forward taper shape having an angle of about 46 ° with respect to the vertical surface, and the wiring 2 below it is formed of Al-.
The 0.5% Cu / TiN / Ti layer becomes almost vertical (FIG. 2). That is, as shown in FIG. 2, the cap layer 4 made of TiN has a forward taper shape with an angle of 44 ° with respect to the substrate surface. (It is conceivable that the polymer 41 formed on the side wall performs a protective function to cause such tapering.)

Due to the forward taper of the TiN layer (cap layer 4), the wiring 2 is formed in a shape thicker by 0.1 μm on each side from the resist pattern. However, here, since the minimum space is 0.4 μm, there is no problem in insulation between the wirings 2.

After post-treatment such as carbon polymer removal (resist removal), PT as an insulating film 5a is formed thereon.
EOS-SiO ₂ is deposited to 100 nm, O ₃ -TEOS-SiO ₂ is deposited to 600 nm as a buried insulating film 5 b, and C is deposited.
Planarization polishing is performed by MP (Chemical Mechanical Polish). P-TEOS is formed on top of this as an interlayer insulating film 5c.
After depositing —SiO ₂ to a thickness of 500 nm, a via hole pattern 60 is formed by photolithography with an alignment deviation of 0.2 μm or less with respect to the Al wiring pattern.

Next, a via hole is processed by the magnetron SiO ₂ etching apparatus under the following conditions (FIG. 3).

Even if the resist pattern indicated by reference numeral 60 in FIG. 3 deviates from the center of the Al wiring 2 by about L ₁ = 0.2 μm, the TiN layer as the cap layer 4 is processed so as to be wide. The via hole does not come off from the wiring 2.

According to the present embodiment, it is possible to form the overlapless via hole without increasing the number of steps, new capital investment, and narrowing the process margin.

Example 2 In this example, as in Example 1, after the sputtering of the Al wiring and the mask formation of the wiring pattern are completed, the Al wiring is etched under the following two-step conditions. Please refer to FIG. 4 to FIG. First step gas flow rate BCl ₃ / Cl ₂ / HBr = 40/120/40 sccm Pressure 1067 Pa RF power 100 W (2 MHz) Etching time 15 sec (TiN layer 60 nm etch-off equivalent) Second step gas flow rate BCl ₃ / Cl ₂ = 80 / 120 sccm pressure 1067 Pa RF power 100 W (2 MHz) etching time 110 sec (corresponding to 40% over-etching) 1st and 2nd step common conditions μ-wave magnetron current 350 mA substrate temperature 20 ° C

As described above, in this example, the Al-based material was etched under the condition that the gas containing Br (here, HBr) was added at 10% or more in the first step.
When processed under this condition, the T attached by the first step
The taper angle of the iN layer is 63 ° with respect to the vertical plane, and the forward tapered cap layer 4 is formed by this, and then the vertical processing is performed in the second step, so that even the thinnest portion has the L-shape shown in FIG. ₂ = 40 nm TiN layer remains. In the present embodiment, the thickening width of the wiring 2 due to the taper was 0.1 μm on each side. Reference numeral 41 is a polymer attached to the tapered side wall.

After performing the post-treatment, as in Example 1,
Interlayer insulating film formation and via hole processing are performed (FIG. 6).
In FIG. 6, reference numerals corresponding to those in the first embodiment are attached.

In the first embodiment, in the worst case, TiN (cap layer 4) at the bottom of the via hole is partially removed (see FIG. 3),
A portion where ohmic contact cannot be made may occur, but in the case of the second embodiment, T forming the cap layer 4 is formed.
At least 40 nm of the iN layer remains (Fig. 5),
Ohmic contact can be obtained over the entire surface of the hole. In addition,
Similar results can be obtained in Example 1 by increasing the thickness of the TiN layer, but in that case, there must be a margin in the Al etching to resist selection ratio.

[0034]

According to the method for forming a wiring structure having the step of forming the connection hole of the present invention, the connection hole having a high reliability can be formed by the simple process.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the steps of Example 1 in order (1).

FIG. 2 is a sectional view showing the steps of Example 1 in order (2).

3A to 3C are sectional views showing steps of Example 1 in order (3).

FIG. 4 is a sectional view showing the steps of Example 2 in order (1).

5A to 5C are sectional views showing the steps of Example 2 in order (2).

6A to 6C are sectional views showing the steps of Example 2 in order (3).

FIG. 7 is a diagram showing a conventional technique.

FIG. 8 is a diagram showing a problem of the conventional technique.

[Explanation of symbols]

 1 Substrate 2a Wiring forming material layer (Al-based material) 2 Wiring 3 Connection hole 4a Cap layer forming material layer (TiN) 4 Cap layer

Claims (3)

[Claims] 1. A method for forming a wiring structure, which comprises a step of forming a wiring on a substrate and forming a connection hole for connecting to the wiring, wherein a wiring forming material layer and a cap layer are formed on the wiring forming material layer on the substrate. A wiring structure having a step of forming a connection hole, characterized in that a material layer is formed, a cap layer is formed in a tapered shape, patterning is performed to form a wiring, and a connection hole is formed in the wiring. Forming method. 2. A wiring material is an aluminum-based material, and the cap layer portion is processed by using a gas having a Cl ₂ gas flow rate ratio of 20% or less in etching the aluminum-based material. A method for forming a wiring structure, comprising the step of forming a connection hole according to claim 1. 3. The wiring material is an aluminum-based material, and the cap layer portion is processed by using a gas under the condition that 10% or more of a gas containing Br is added in etching the aluminum-based material. Item 2. A method for forming a wiring structure, comprising the step of forming a connection hole according to Item 1.