JPH10199972A - Method of forming wiring structure, and wiring structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of forming wiring structure which can embed suitably wiring material into a connection hole, when the connection hole is shifted from a lower layer wiring. SOLUTION: A trench 15 for lower layer wiring is formed in a lower layer insulating film 14 having an etching stopper layer 12 and an upper layer 13, in such a manner that the bottom part of the trench becomes deeper than the surface of the etching stopper layer 12. Wiring layer material is embedded in the trench 15 for lower layer wiring, and a lower layer wiring 18 is formed. An upper layer insulating film 19 is formed on the lower layer insulating film 14, covering the lower layer wiring 18. A connection hole 21, connected with the lower layer wiring 18, is formed by etching the upper layer insulating film 19. Under the condition that the selection ratio to the insulating material for forming the etching stopper layer 12 can be obtained, the upper layer insulating film 19 is etched, and a trench 22 for upper layer wiring, which is continuously connected with the connection hole 21, is formed. Wiring material is embedded into the connection hole 21 and the trench 22 for upper layer wiring, and an upper layer wiring 24 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring structure for forming an upper wiring in a trench wiring structure on a lower wiring, and a wiring structure obtained by the method.

[0002]

2. Description of the Related Art Along with the high integration of VLSIs, various studies have been made to realize miniaturization of internal wiring. For example, trench wiring technology has realized the miniaturization of wiring and multi-layering relatively easily. It is being actively studied as a possible technology. The groove wiring technique is to form a predetermined groove in an interlayer insulating film in advance, and then to form an Al in the groove by a sputter reflow method, a CVD method, or the like.
Alternatively, the wiring material is deposited and deposited while embedding a wiring material such as Cu, and thereafter, the wiring material deposited on a portion other than the groove by a CMP method or the like is removed to leave the wiring material in the groove. It is considered that such a trench wiring technique is promising especially when a wiring is formed by Cu which is difficult to be etched by RIE. On the other hand, in the case of forming a multilayer wiring structure, conventionally, the line width of the flat wiring portion is made thicker only at the connection portion with the connection hole in consideration of misalignment at the overlapping portion between the flat wiring portion and the connection hole which occurs at the time of photoresist. And give them extra time.

[0003]

However, as the degree of integration increases, it is required to increase the degree of integration of wiring, and in order to meet this, the margin for the misalignment is reduced as much as possible. Attempts have been made to eliminate them or not at all. This is no exception in the trench wiring structure.

If the margin for misalignment is reduced or eliminated, for example, as shown in FIG. 5A, when a connection hole 1 for an upper wiring (not shown) is formed,
Due to misalignment of the resist pattern 2 in the photoresist process, the connection hole 1 may be formed to be displaced from the lower wiring 3. If the connection holes 1 are formed in such a manner that the connection holes 1 are shifted from each other, for example, at the time of etching the opening of the connection holes 1, due to a variation in the etching amount or over-etching, as shown in FIG. There is a case where the lower insulating film 4 on the side is deeply shaved and a deep hole 1a is formed in the connection hole 1.

If the connection hole 1 is formed in this manner, for example, when the Al alloy is buried later by a reflow process, as shown in FIG.
An embedded shape defect may occur in the upper Al alloy 6. This is because in the case of the reflow treatment, it is necessary to connect the Al alloy 5 with one layer, but if the deep hole 1a is formed in the connection hole 1 as described above, the Al alloy 6 is formed at the hole 1a. As a result, Al
This is because the alloy 6 cannot be buried in a sufficient state. It should be noted that the above-described variation in the amount of etching is usually eliminated when a wafer is subjected to an etching process, because a variation occurs between a central portion and an outer peripheral portion of the wafer or a variation occurs between wafers to be processed. It is extremely difficult.

Even if the amount of etching is sufficiently controlled to prevent the formation of the hole 1a as shown in FIG. The contact area between the contact hole and the bottom of the connection hole 1 is reduced, and disadvantages such as an increase in wiring resistance and deterioration of electromigration resistance occur.

Further, in order to employ the above-described trench wiring technique, a connection hole 1 is formed as shown in FIG. 5A, and then an upper insulating film (not shown) is formed on the lower insulating film 4. When a groove (not shown) communicating with the connection hole 1 is formed in the upper insulating film, the inside of the connection hole 1 is also etched by the etching for forming the groove, and the bottom of the connection hole 1 is excessively dug. As a result, a deep hole 1a is formed as shown in FIG.

The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce or eliminate a margin for misalignment. Provided is a method of forming a wiring structure that can satisfactorily embed a wiring material into a connection hole, and also prevents an increase in wiring resistance and deterioration of electromigration resistance, and a wiring structure obtained by such a method. Is to do.

[0009]

Means for Solving the Problems Claim 1 of the present invention
In the method for forming a wiring structure described above, on the lower wiring in the lower insulating film, an upper wiring in a trench wiring structure electrically connected to the lower wiring through a conductive material in a connection hole formed in the upper insulating film. In the forming method, an etching stopper layer made of one insulating material is formed on a substrate, and then an upper layer made of an insulating material different from the one insulating material is formed thereon, and a lower insulating film is formed. A step of forming a lower wiring groove in the lower insulating film such that a bottom surface thereof is deeper than a surface of the etching stopper layer; and forming a lower wiring by embedding a wiring material in the lower wiring groove. A step of forming an upper insulating film on the lower insulating film while covering the lower wiring, a step of etching the upper insulating film to form a connection hole communicating with the lower wiring, Etching the upper insulating film under conditions that allow a selectivity with the insulating material forming the stopper layer to form an upper wiring groove communicating with the connection hole; and forming the upper wiring groove in the connection hole and the upper wiring. Forming an upper layer wiring by embedding a wiring material in the groove.

According to this method of forming a wiring structure, an etching stopper layer is formed in the lower insulating film so as to be located above the bottom surface of the lower wiring, and a selectivity between the etching stopper layer and the insulating material forming the etching stopper layer is formed. Since the upper insulating film is etched under the condition that the upper wiring can be removed and the upper wiring groove communicating with the connection hole is formed, even when the connection hole is formed so as to be shifted from above the lower wiring, particularly when the upper wiring groove is formed. Even if the inside of the connection hole is etched by the above etching, this etching stops at the etching stopper layer, so that a deep hole is not formed in the obtained connection hole because the side wall side of the lower wiring is cut deep. Further, when the connection hole is formed so as to be shifted from the lower wiring, the wiring material embedded in the connection hole contacts the side wall surface of the lower wiring on the etching stopper layer at the shifted position. Therefore, a sufficient contact area is secured between the upper wiring and the lower wiring made of the wiring material.

In the wiring structure according to the present invention, on the lower wiring in the lower insulating film, the wiring is electrically connected to the lower wiring via a conductive material in a connection hole formed in the upper insulating film. A wiring structure in which an upper wiring is formed in a trench wiring structure, wherein the lower insulating film includes an etching stopper layer made of one insulating material and an insulating material different from the one insulating material formed thereon. The lower wiring is formed such that the bottom surface thereof is at a position deeper than the surface of the etching stopper layer, and the connection hole formed in the upper insulating film is A part of the bottom part communicates with the upper surface of the lower wiring, and the remaining part is formed at the side of the lower wiring so as to communicate with the etching stopper layer, and the upper insulating film communicates with the connection hole. Grooves formed It is, that the upper layer wiring is formed by wire material is embedded in the upper layer wiring groove and the connection hole and the solutions of the problems.

According to this wiring structure, a part of the bottom of the connection hole communicates with the upper surface of the lower wiring, and the remaining part is formed on the side of the lower wiring so as to communicate with the etching stopper layer. The upper wiring formed by embedding the wiring material in the connection hole comes into contact with the side wall surface of the lower wiring in the remaining portion of the connection hole, and therefore, a sufficient contact area between the upper wiring and the lower wiring becomes large. Secured.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on a method for forming a wiring structure. 1 (a) to 1 (d) and 2 (a) to 2 (c) are views showing a first embodiment of a method for forming a wiring structure according to the present invention. In these figures, reference numeral 10 denotes a substrate. . The substrate 10 is obtained by subjecting a semiconductor substrate such as a silicon wafer to a predetermined LSI process.

In the first embodiment, first, a lower layer 11 having a thickness of 700 nm is formed by depositing SiO ₂ on a substrate 10 by a plasma CVD method or the like.
P-SiN is deposited on the lower layer 11 by VD to form an etching stopper layer 12 having a thickness of 100 nm, and SiO ₂ is deposited again on the etching stopper layer 12 by a plasma CVD method or the like, and the thickness is reduced. An upper layer 13 having a thickness of 200 nm is formed, thereby forming a lower insulating film 14 including a lower layer 11, an etching stopper layer 12, and an upper layer 13.
Get.

Next, a known photolithography technique,
1 using reactive etching (RIE) technology
As shown in (b), the lower wiring groove 15 is formed in the lower insulating film 14.
To form At this time, the lower wiring groove 15 is formed such that the bottom surface thereof is deeper than the surface of the etching stopper layer 12. Specifically, in this example, at a depth of about 500 nm from the surface of the lower insulating film 14,
That is, about 300 from the surface of the etching stopper layer 12.
nm. In addition, regarding the etching of the lower insulating film 14, the upper layer 13 made of SiO ₂ ,
The etching stopper layer 12 made of SiN and the lower layer 11 made of SiO ₂ were performed in this order under the following conditions. Etching condition of upper layer 13 (SiO ₂ ) Gas; CHF ₃ / O ₂ = 75/8 sccm RF power; 1200 W pressure; 7 Pa Etching condition of etching stopper layer 12 (SiN) Gas: CHF ₃ / O ₂ = 75/35 sccm RF Power; 600 W pressure; 5 Pa Etching conditions for lower layer 11 (SiO ₂ ) Gas; CHF ₃ / O ₂ = 75/8 sccm RF power; 1200 W pressure; 7 Pa

Next, as shown in FIG. 1C, a wiring material 16 is buried in the lower wiring groove 15. Here, when embedding the wiring material 16, prior to this, the DC
A base metal material 17 to be an adhesion layer is formed on the inner surface of the lower wiring groove 15 by the magnetron sputtering method under the following conditions. In this example, Ti is used for the lower layer and TiN is used for the upper layer.
An N / Ti laminated film is formed. Ti film formation conditions DC power; 6 kW Process gas; Ar 100 sccm pressure; 0.4 Pa Film formation temperature; 200 ° C. Film thickness: 20 nm TiN film formation conditions DC power: 12 kW Process gas: Ar 20 sccm, N ₂ 70 scc
m pressure; 0.4 Pa film forming temperature; 200 ° C. film thickness;

Thereafter, an Al—Cu alloy is formed under the following conditions by DC magnetron sputtering, and then the substrate is heated to reflow the Al—Cu alloy under the following conditions. A wiring material 16 made of an Al-Cu alloy is embedded on a film made of a metal material 17. Al-Cu film forming conditions DC power; 15 kW Process gas; Ar (100 sccm) pressure; 0.4 Pa Film forming temperature; 200 ° C. Film thickness: 1.5 μm Reflow condition temperature; 500 ° C. time; 1 min gas; Ar surface gas pressure; In this example, the process from the sputter deposition to the reflow was performed in a high vacuum atmosphere including the substrate transfer.

Next, the CMP method (chemical mechanical polishing method)
Thus, the wiring material 16 and the underlying metal material 17 above the lower wiring groove 15 are polished and removed under the following conditions, and as a result, the wiring material 16 is placed in the lower wiring groove 15 as shown in FIG. Main wiring 16a made of
Is formed. In this example, the lower wiring 18 is formed in a fine wiring with a substantially constant width without providing a margin for misalignment occurring at the time of photoresist with respect to a connection hole for electrical connection to an upper wiring described later. Is formed. CMP conditions Polishing pressure: 100 g / cm ² Number of revolutions: Platen 30 rpm, polishing head 30 rpm Slurry: NH ₄ OH base (containing fumed silica) Slurry flow rate: 100 cc / min Temperature: 25 to 30 ° C.

Next, SiO ₂ is deposited on the lower insulating film 14 by a plasma CVD method or the like, and the upper insulating film 1 is covered with the lower wiring 18 as shown in FIG.
9 is formed to a thickness of about 1000 nm. Subsequently, a resist pattern 20 having an opening pattern 20a is formed immediately above the lower wiring 18 by a known photoresist technique and lithography technique. At this time, as shown in FIG. 2A, the opening pattern 20a of the resist pattern 20 is formed so as to be shifted from a position immediately above the lower wiring 18 due to an alignment limit or the like during photolithography.

Then, using the resist pattern 20 thus formed as a mask, the upper insulating film 19 is etched by reactive ion etching (RIE).
A connection hole 21 is formed as shown in FIG. Then, as described above, since the opening pattern 20 a of the resist pattern 20 is formed so as to be displaced from the position immediately above the lower wiring 18, the obtained connection hole 21 has a part of the bottom portion on the upper surface of the lower wiring 18. The connection is established, and the rest is shifted to the side of the lower wiring 18. At this time, in the present embodiment, the etching of the upper insulating film 19 made of SiO ₂ is performed under the condition that a sufficient selection ratio can be obtained with the etching stopper layer 12 made of SiN. Therefore, the etching becomes over-etching, and FIG.
As shown in (b), even if the remaining portion of the connection hole 21 is dug deep, the bottom of the remaining connection hole 21 stops at the surface of the etching stopper layer 12. After that, the resist pattern 20 is removed.

Next, a resist pattern (not shown) having a wiring groove pattern (not shown) communicating with the connection hole 21 is formed by a known photoresist technique and lithography technique, and then the resist pattern is used as a mask. Then, the upper insulating film 19 is formed under the same conditions as the etching for forming the connection holes 21 as described above, and as shown in FIG.
The upper wiring groove 22 extending in the same direction as the above is formed. When the upper wiring groove 22 is formed in this manner, the connection hole 21 is formed.
In the location where is formed, the bottom is subjected to excessive etching due to the formation of the connection hole 21. Since part of the connection hole 21 communicates with the upper surface of the lower wiring 18 and the remainder communicates with the etching stopper layer 12, the upper insulating film 19 remaining in the connection hole 21 is almost completely removed. However, in the connection hole 21, the upper-layer wiring groove 22 is formed without further etching.

Next, the connection hole 2 was formed by Ar sputtering etching.
A natural oxide film (not shown) on the surface of the lower wiring 18 at one bottom is removed, and further, Ti, Ti is deposited by DC magnetron sputtering under the same conditions as for the formation of the base metal material 17.
A base metal material 23 of TiN is formed. Subsequently, the wiring material is deposited and reflowed by DC magnetron sputtering under the same conditions as the filming and reflow processing of the wiring material 16, and the film is buried in the upper layer wiring groove 22, and is further processed under the same conditions. Polishing by the CMP method was performed, and FIG.
As shown in (1), an upper layer wiring 24 is formed in the upper layer wiring groove 22 to obtain a wiring structure 25.

The wiring structure 25 thus obtained is
According to an embodiment of the present invention described in claim 7 of the present invention, a part of the bottom of the connection hole 21 is formed in the lower wiring 18.
The upper layer wiring 24 formed in the connection hole 21 is formed by connecting the upper layer wiring 24 formed in the connection hole 21 to the upper surface of the connection hole 21 and the remaining portion is formed on the side of the lower layer wiring 18 so as to communicate with the etching stopper layer 12. The remaining portion 21 comes into contact with the side wall surface of lower wiring 18, and therefore, although connection hole 21 is formed shifted from lower wiring 18,
A sufficient contact area between the upper wiring 24 and the lower wiring 18 can be ensured. Therefore, according to the wiring structure 25, the upper layer wiring 24 is formed without providing a margin for the misalignment occurring at the time of the photoresist with respect to the connection hole 21 and having a substantially constant and fine width. Since a sufficient contact area is ensured between the wiring 18 and the lower wiring 18, it is possible to suppress inconveniences such as an increase in wiring resistance and deterioration of electromigration resistance.

In the method of forming the wiring structure 25, the etching stopper layer 12 is formed in the lower insulating film 14 so as to be located above the bottom surface of the lower wiring 18, and the etching stopper layer 12 is formed. The upper insulating film 19 is etched under the condition that a selection ratio can be obtained with the insulating material to be formed to form the connection hole 21 and the upper wiring groove 22 communicating with the connection hole 21. Even if they are formed shifted, even if the inside of the connection hole 21 is etched by the etching for forming the connection hole 21 and further the etching for forming the upper layer wiring groove 22, the etching is performed by the etching stopper layer 12. Stop. Therefore, a deep hole is not formed in the obtained connection hole 21 due to the side wall side of the lower layer wiring 18 being deeply cut as in the conventional case, so that the subsequent reflow processing of the wiring material 16 is performed favorably. Therefore, the embedding failure of the wiring material 16 can be reliably prevented, and high wiring reliability can be ensured.

FIG. 4 is a view showing a modification of the wiring structure of the present invention. The difference between the wiring structure 30 shown in FIG. 4 and the wiring structure 25 shown in FIG. 3 is that the wiring structure shown in FIG. 3
0 indicates the base metal material 1 formed in the lower wiring groove 15.
7 is that the portion facing the connection hole 21 is removed. That is, in this example, after the connection hole 21 is formed as shown in FIG. 2A and the bottom of the connection hole 21 is made to communicate with the etching stopper layer 12, or after the upper wiring groove 22 is formed, the connection hole is formed. Prior to embedding the wiring material in the hole 21 and the upper wiring groove 22, the underlying metal material 17 exposed in the connection hole 21 is removed by wet etching or the like. When part of the base metal material 17 (portion exposed in the connection hole 21) is removed in this manner, the upper wiring 24 embedded in the connection hole 21 is thereafter removed.
However, on the side wall surface of the lower wiring 18, conduction is made to the lower wiring 18 only through the base metal material 23 on the connection hole 21 side, so that the resistance therebetween is further reduced. Therefore,
In the wiring structure 30, since the resistance between the upper wiring 24 and the lower wiring 18 can be further reduced, it is possible to more reliably suppress an increase in wiring resistance and a deterioration in electromigration resistance.

In the above-described embodiment, the reflow method is used as a processing method for embedding the wiring material. However, a high-pressure reflow method may be used instead, and a high-temperature sputtering method or a CVD method may be used. It is also possible. An example of a series of film formation and reflow conditions when the high-pressure reflow method is employed will be described below. Ti film formation conditions DC power; 6 kW Process gas; Ar (100 sccm) pressure; 0.4 Pa Film formation temperature: 400 ° C. TiN film formation conditions DC power: 12 kW Process gas; Ar / N ₂ = 20/70 sccm pressure; 0.4 Pa Film forming temperature: 400 ° C. Al-Cu film forming conditions DC power: 15 kW Process gas; Ar (100 sccm) pressure: 0.4 Pa Film forming temperature: 400 ° C. High pressure reflow condition Process gas: Ar pressure: 70 MPa Reflow time: 1 min Substrate temperature ; 450 ° C

Further, in the above embodiment, the SiN film is used as the etching stopper layer. However, the present invention is not limited to this, and the organic low dielectric material, specifically, polyallyl ether (trade name: flare) [Allied Signal Co., Ltd.]), a layer made of benzocyclobutene (BCB), polyparaxylylene (parylene), or the like can be used. Further, in the above embodiment, the lower insulating film 14 has a three-layer structure including the lower layer 11, the etching stopper layer 12, and the upper layer 13, but the lower insulating film 14 includes the etching stopper layer 12 and the upper layer 13. Therefore, it may have a two-layer structure or a structure of four or more layers.

The depth of the lower wiring groove 15 is not particularly limited as long as it is made to be deeper than the surface of the etching stopper layer 12, but the depth of the lower surface of the etching stopper layer 12 is not limited. (Position from the surface of the lower insulating film 14) is preferably about 0.1 to 0.5 of the depth of the lower wiring groove 15. Because
If it is less than 0.1, if the connection hole 21 is formed shifted from the lower wiring 18, a sufficient contact area between the shifted upper wiring 24 and the side wall surface of the lower wiring 18 cannot be secured. If the thickness exceeds 0.5, when the connection hole 21 is formed so as to be shifted from the lower wiring 18, the shifted portion becomes relatively deep, so that the embedding property of the upper wiring 24 is reduced.

In the above embodiment, a TiN / Ti laminated film is formed as the film made of the underlying metal material 17, but instead, for example, a Ti single layer film, a TiN single layer film,
Alternatively, it may be formed by a laminated film of Ti / TiN / Ti or the like, and further may be formed by a TiW single-layer film, a W single-layer film, or a laminated film thereof. further,
Although an Al-Cu alloy was used as the wiring material 16 for forming the lower wiring 18 and the wiring material for forming the upper wiring 24, these wiring materials are not limited thereto, and for example, Al-Si, Al-Si-C
u, Al-Ge or the like can be used.
Metals such as Ag and Cu, and alloys such as Cu-Zr can also be used.

[0030]

As described above, according to the method of forming a wiring structure of the present invention, an etching stopper layer is formed in a lower insulating film so as to be located above the bottom surface of a lower wiring, and the insulating film for forming the etching stopper layer is formed. Since the upper insulating film is etched under the condition that a selectivity can be obtained with the material to form the upper wiring groove communicating with the connection hole, the connection hole is formed so as to be shifted from above the lower wiring. Even if the inside of the connection hole is etched by the etching at the time of forming the use groove, this etching stops at the etching stopper layer, so that a deep hole is formed in the obtained connection hole by the side wall side of the lower wiring being deeply cut. Can be prevented. Therefore, it is possible to satisfactorily embed the wiring material into the connection holes and the upper layer wiring groove later, thereby forming a wiring structure having high wiring reliability. In addition, according to this method, it is not necessary to form a margin for misalignment at the time of photoresist for the above-described reason.
Multilayering can be further promoted, which can contribute to high integration of VLSI and the like.

In the wiring structure of the present invention, a part of the bottom of the connection hole communicates with the upper surface of the lower wiring, and the remaining part is formed at the side of the lower wiring so as to communicate with the etching stopper layer. Thus, the upper layer wiring formed by embedding the wiring material in the connection hole can be brought into contact with the side wall surface of the lower layer wiring at the remaining portion of the connection hole, whereby sufficient space can be provided between the upper layer wiring and the lower layer wiring. A contact area can be ensured, so that inconveniences such as an increase in wiring resistance and deterioration of electromigration resistance can be suppressed.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views of a main part for explaining an embodiment of a method for forming a wiring structure according to the present invention in the order of steps.

FIGS. 2A to 2C are diagrams showing an embodiment of a method for forming a wiring structure according to the present invention in the order of steps, and FIGS.
5 is a side sectional view of a main part for describing a step that follows the step shown in FIG.

FIG. 3 is a side sectional view showing a main part of an embodiment of a wiring structure according to the present invention.

FIG. 4 is a sectional side view of a main part showing a modification of the wiring structure of the present invention.

5 (a) to 5 (d) are cross-sectional side views of main parts for describing problems in a conventional method for forming a wiring structure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Substrate 12 Etching stopper layer 13
Upper layer 14 Lower layer insulating film 15 Lower layer wiring groove 16 Wiring material 17 Base metal material 18 Lower layer wiring 19 Upper insulating film 21 Connection hole 22 Upper wiring groove 23 Base metal material 24 Upper wiring 25, 30 Wiring structure

Claims (9)

[Claims] An upper wiring is formed on a lower wiring in the lower insulating film via a conductive material in a connection hole formed in the upper insulating film, the groove wiring structure electrically communicating with the lower wiring.
A method of forming a wiring structure, comprising: forming an etching stopper layer made of an insulating material on a base, forming an upper layer made of an insulating material different from the one insulating material on the etching stopper layer, Forming a film, forming a lower wiring groove in the lower insulating film such that the bottom surface thereof is deeper than the surface of the etching stopper layer, and embedding a wiring material in the lower wiring groove to form a lower layer. Forming a wiring, forming an upper insulating film on the lower insulating film while covering the lower wiring, and forming a connection hole communicating with the lower wiring by etching the upper insulating film. Etching the upper insulating film under the condition that a selectivity can be obtained with the insulating material forming the etching stopper layer;
A wiring structure comprising: a step of forming an upper layer wiring groove communicating with the connection hole; and a step of forming an upper layer wiring by embedding a wiring material in the connection hole and the upper layer wiring groove. Formation method. 2. The method according to claim 1, wherein the step of embedding a wiring material in the upper wiring groove is performed by a reflow method or a high-pressure reflow method. 3. The method according to claim 1, wherein the etching stopper layer is made of SiN or an organic low dielectric material. 4. The method for forming a wiring structure according to claim 3, wherein the step of embedding a wiring material in the upper wiring groove is performed by a reflow method or a high-pressure reflow method. 5. When forming a lower wiring by embedding a wiring material in the lower wiring groove, a base metal material to be an adhesion layer is first formed on the inner surface of the lower wiring groove, and then the wiring material is embedded. When forming an upper layer wiring by embedding a wiring material in the connection hole and the upper layer wiring groove, when the connection hole is formed in a state communicating with a side portion of the lower layer wiring, the connection is performed. 2. The method for forming a wiring structure according to claim 1, wherein the film made of the base metal material exposed in the hole is removed. 6. The method for forming a wiring structure according to claim 5, wherein the process of embedding a wiring material in the upper wiring groove is performed by a reflow method or a high-pressure reflow method. 7. An upper wiring in a trench wiring structure electrically connected to the lower wiring via a conductive material in a connection hole formed in the upper insulating film, on the lower wiring in the lower insulating film. Wherein the lower insulating film comprises: an etching stopper layer made of one insulating material; and an upper layer made of an insulating material different from the one insulating material formed thereon. The lower wiring is formed such that a bottom surface thereof is at a position deeper than a surface of the etching stopper layer, and a connection hole formed in the upper insulating film has a part of a bottom part formed on an upper surface of the lower wiring. And the remaining portion is formed at the side of the lower wiring so as to communicate with the etching stopper layer. In the upper insulating film, a groove for the upper wiring communicating with the connection hole is formed. In the groove and the connection hole Wiring structure characterized by comprising an upper layer wiring is formed by wire material is embedded in. 8. The wiring structure according to claim 7, wherein said etching stopper layer is made of SiN or an organic low dielectric material. 9. The lower wiring comprises a base metal film formed on the inner surface of the lower wiring groove and serving as an adhesion layer, and a main wiring buried on the base metal film. 8. The wiring structure according to claim 7, wherein a base metal film is removed from a portion facing the substrate.