JPH0833871B2 - DMA control device - Google Patents

Description

DETAILED DESCRIPTION [Overview] In a data processing device having a CPU, data can be directly transferred at high speed between a storage device and an input / output device during a period in which the CPU relinquishes the exclusive right of the system bus. Regarding a DMA control device for controlling a DMA to be transferred, at least a storage device is connected for the purpose of enabling a single transfer between two independent system buses without complicating the configuration of the data processing device. DMA data transfer on the first system bus and at least an input / output device connected to the second system bus independent of the first system bus and on one system bus and across both system buses In the DMA controller for controlling the storage device, at the time of a single transfer from the storage device to the input / output device across both system buses, a first address is added to the storage device. A rest strobe signal, a first data strobe signal, and a first read / write signal instructing a read are output to the first system bus, and a second data strobe signal is output to the input / output device. A second read / write signal for instructing read is output to the second system bus, and to the input / output device during a single transfer from the input / output device to the storage device across both system buses. A second data strobe signal and a second read / write signal for instructing a write are output to the second system bus, and a first address strobe signal and a first data strobe are sent to the storage device. A signal and a first read / write signal for instructing writing.
It is configured to output on the system bus of.

[Industrial applications]

The present invention relates to a DMA (Direct Memory Access) control device, and in particular, in a data processing device having a CPU (Central Processing Unit), between a storage device and an input / output device while the CPU relinquishes the exclusive right of the system bus. The present invention relates to a DMA control device for controlling a DMA that directly transfers data at high speed without going through the CPU.

[Conventional technology]

Traditionally, when transferring data between devices connected to system buses that are independent of each other, usually first-in-first-out (FIFO) or dual-port random access memory (RAM) is used. ing. However, even in such a data processing device having two independent system buses, in order to perform higher-speed data transfer, DMA over two system buses is performed.
Realization of transfer is desired.

As a conventional data processing device capable of performing a DMA transfer across two system buses, there is a device shown in FIG. In the figure, a system bus 100 includes a CPU 101 and a DMA controller.
102, memory 103, and I / O (input / output) interface 104
Are connected to form a first system. A CPU 111, a DMA controller 112, a memory 113, and an I / O interface 114 are connected to the system bus 110 to form a second system. FIFO10 is connected between the system buses 100 and 110.
5,115 are provided. The FIFO 105 is for message communication between the CPUs 101 and 111, and the FIFO 115 is for data transfer between the system buses 100 and 110.

For example, when performing DMA data transfer from the memory 113 to the memory 103, first, the DMA controller 112 acquires the right to use the system bus 110 from the CPU 111, and transfers the data from the memory 113 to the FI.
Write to FO115. The DMA control device 102 acquires the right to use the system bus from the CPU 101 in response to the transfer request from the FIFO 115, and writes the data from the FIFO 115 into the memory 103.

In this conventional device, two DMA control devices 102, 112 and 2 are used.
It is necessary to provide two FIFOs 105 and 115. But FIFO10
Since 5,115 are bidirectional, the number of peripheral circuits such as a controller for controlling the FIFOs 105, 115 is large. or,
The DMA data transfer between the system buses 100 and 110 is performed via the FIFO 115, and the DMA control devices 102 and 112 are handshaking with the FIFO 115, so that the data transfer efficiency is low. Further, single transfer across the two system buses 100, 110 is not possible.

Therefore, a method of controlling DMA data transfer between two system buses by one DMA control device can be considered. However, since the conventional DMA control device is originally configured to control DMA transfer on one system bus, control signals such as read / write signals necessary for DMA transfer are connected to one system bus. It can be output only to the device. Thus DM over two independent system buses
In order to perform the A transfer, it is necessary to provide a control circuit for outputting a control signal required for the DMA transfer on the two system buses in the two system bus circuits.

[Problems to be solved by the invention]

In the case of a conventional data processing device using two DMA control devices, there has been a problem that single transfer cannot be performed across two independent system buses. Also, one
In the case of a data processing device using a DMA control device, in order to perform a single transfer across two independent system buses, two control circuits having a complicated circuit configuration for outputting a control signal required for DMA transfer are provided. Since it has to be provided between the system buses, there has been a problem that the configuration of the data processing device becomes complicated.

It is an object of the present invention to provide a DMA controller capable of enabling single transfer between two independent system buses without complicating the configuration of the data processing device.

[Means for solving problems]

FIG. 1 is a diagram for explaining the principle of the present invention. 1,3 in the figure
Is an independent system bus, 2 is a storage device connected to the system bus 1, 3 is an input / output device connected to the system bus 1, and 5 controls DMA transfer on one system bus and across both system buses It is a DMA controller.

[Action]

Both system buses from storage device 2 to input / output device 4
At the time of single transfer over 1,3, the first address strobe signal AS1 and the first data strobe signal DS1 and the first read / write signal R / W1 for instructing the read to the storage device 2 are set to the first A second read / write signal R / W that outputs to the system bus 1 and instructs the input / output device 2 to read the second data strobe signal DA2.
2 and 2 are output on the second system bus 3. On the other hand, in the case of a single transfer from the input / output device 4 to the storage device 2 across both system buses 3, 1, the second input / output device 4 is connected
Of the data strobe signal DS2 and the second read / write signal R / W2 for instructing the write to the second system bus 3, and to the storage device 2 the first address strobe signal AS1 and the first address strobe signal AS1. Data strobe signal DS1 and a first read / write signal R / W1 for instructing a write
Output to the system bus 1 of.

Therefore, single transfer between two independent system buses can be performed without complicating the configuration of the data processing device.

〔Example〕

FIG. 2 shows a main part of a data processing device to which an embodiment of the present invention is applied. In the figure, reference numerals 11 and 12 denote system buses independent of each other, each of which includes an address bus, a data bus and a control bus. Reference numerals 13 and 14 are a memory and an input / output device connected to the system bus 11, and reference numerals 15 and 16 are a memory and an input / output device connected to the system bus 12, respectively. The DMA controller (hereinafter referred to as DMAC) 17 is directly connected to the system bus 11,12.
Connected to the control bus. The DMAC 17 is connected to the address buses of the system buses 11 and 12 via the bidirectional buffer 18 and to the data buses of the system buses 11 and 12 via the bidirectional buffer 19. Therefore, DMA
The C17 outputs an address to the system bus 11 or 12 by supplying a control signal for switching on / off of the buffer 18 and a control signal for switching the transfer direction of the signal. The output direction of the address is with respect to the bus having the memory for performing the transfer. Similarly, DMAC17
Provides a control signal for switching the buffer 19 on / off and a control signal for switching the signal transfer direction, thereby enabling data transfer between the system buses 11 and 12. The CPUs connected to the system buses 11 and 12 are not shown.

First, the operation in the case of single transfer on the same system bus will be described. Here, for convenience of description, a single transfer on the system bus 11 from the memory 13 to the input / output device 14 will be described as an example. FIG. 3 shows the main part of the data processing device for explaining the operation in this case.

In FIG. 3, when the DMAC 17 receives a transfer request from the input / output device 14, it outputs the transfer address to the memory 13 via the address bus of the system bus 11 and outputs the address strobe signal AS1 and the data strobe signal DS1. Lead /
The transfer is started by outputting the write signal R / W1 and the memory 13 via the control bus of the system bus 11.
At the same time, a confirmation (acknowledge) signal AC from the DMAC17
K is output to the input / output device 14 via the control bus. The input / output device 14 is controlled by using the control signal output to the memory 13. That is, the read / write signal R / W1 for the memory 13 from the control bus of the system bus 11 is inverted by the inverter INV and supplied to the input / output device 14.
The transfer is completed by the data complete signal DC from the memory 13.
1 is notified by being supplied to the DMAC 17 via the control bus of the system bus 11.

The timing of various signals in this case is shown as case I in FIG. 4A and 4B show the system clock signal CLK and the transfer address ADR, respectively. FIGS. 4C to 4F show signals AS1, DS1, R / W1 and DC1, respectively. FIG. 4 (L) shows the confirmation signal ACK.

Although detailed description is omitted, the memory 15 to the input / output device 16
The timings of various signals in the case of a single transfer on the system bus 12 are shown as case II in FIG.
AS2, DS2, R / W2, DC2 are DMAC17 respectively in the figure (G) to (J).
Address strobe signal, data strobe signal, read / write signal, and data complete signal output from the memory bus to the memory 15 via the control bus of the system bus 12.

In the above description, the DMAC 17 outputs the confirmation signal to the input / output devices 14 and 16, but next, in addition to this, the input / output devices 14 and 16 have a ready (ready) signal output function. The operation in this case will be described. Figure 5 shows the memory
FIG. 6 is a diagram for explaining a single transfer from 13 to the input / output device 14, and FIG. 6 is a diagram for explaining a single transfer from the input / output device 16 to the memory 15.

For a single transfer from memory 13 to I / O device 14,
As shown in Fig. 5, the transfer address is under the control of DMAC17.
ADR is output from the DMAC17 to the memory 13 and the DMAC17
The signals AS1, DS1, R / W1 are supplied from the memory 13 to the memory 13. DS1 and R / W1 are supplied to the input / output device 14, and a confirmation signal ACK is further supplied to the input / output device 14. This allows the data from the memory 13 to
Transferred to 14. After that, the memory 13 is DMAC as shown in
The data complete signal DC1 is output to 17 and the I / O device 14 outputs the ready signal IOREADY to the DMAC 17. The timing of various signals in this case is shown as case III in FIG. Incidentally, FIG. 4 (K) shows the ready signal IOREADY. In this case, the DMAC 17 sees the data complete signal DC1 and the ready signal IOREADY at the same time and ends the transfer.

In case of single transfer from I / O device 16 to memory 15,
As shown in FIG. 6, the transfer address is under the control of DMAC17.
ADR is output from the DMAC17 to the memory 15, and the DMAC17
The signals AS2, R / W2 are supplied from the memory 15 to the memory 15. Furthermore, DMAC
R / W2 is supplied from 17 to the input / output device 16 and the confirmation signal ACK is supplied. As a result, the data from the input / output device 16 is transferred to the memory 15 as indicated by. next,
As shown by, the input / output device 16 outputs the ready signal IOREADY to the DMAC 17. After that, the DMAC17 turns on the ready signal I
When OREADY comes in, the data strobe signal DS2 is supplied to the memory 15 as shown by, and the memory 15 outputs the data complete signal DS2 to the DMAC 17 as shown by.
The timing of various signals in this case is as shown in Case IV in FIG.
As shown. In this case, the DMAC 17 ends the transfer when the data complete signal DC2 comes in from the memory 15.

Although the data strobe signal of the input / output device 14 (16) differs depending on the data processing device, for example, the confirmation signal ACK and the read / write signal R / W / (R / W
2) Generate from and.

Next, the operation in the case of single transfer across two system buses will be described. Here, for convenience of explanation, the system buses 11 and 12 from the memory 13 to the input / output device 16 are shown.
A single transfer between will be described as an example. FIG. 7 shows the main part of the data processing device for explaining the operation in this case. In the figure, when the DMAC 17 receives a transfer request from the input / output device 16, the transfer address ADR is output to the memory 13 via the address bus of the system bus 11 and the buffer 18, and the DMAC 17 receives the address strobe signal AS1. The data strobe signal DS1 and the read / write signal R / W1 instructing the read are output to the memory 13 via the control bus of the system bus 11. At the same time, the confirmation signal ACK is supplied from the DMAC 17 to the input / output device 16 via the control bus of the system bus 12. Further, the DMAC 17 outputs the data strobe signal DS2 and the read / write signal R / W2 instructing the read to the input / output device 16 via the control bus of the system bus 12. As a result, the data from the memory 13 is transferred to the data bus of the system bus 11, the buffer 19 and the system bus 12.
Is single-transferred to the input / output device 16 via the data bus.

The buffer 18 is DMA when transferring the transfer address ADR.
It is turned on by C17 to switch the transfer direction from the system bus 12 to the system bus 11 and control it.
Needless to say, is turned on by the DMAC 17 during data transfer and the transfer direction is switched from the system bus 11 to the system bus 12.

The timing of various signals in this case is shown as case V in FIG. In the figure, the same signals as those in FIG. 4 are designated by the same reference numerals.

In the above case, the timing of various signals when the input / output device 16 outputs the ready signal IOREADY to the DMAC 17 is shown as a case VII in FIG. Case V
For II, DMAC17 is ready signal IO from I / O device 16
The READY and the data complete signal DC1 from the memory 13 are simultaneously observed to end the transfer.

Next, the system bus 1 from the input / output device 14 to the memory 15
Taking a single transfer between 1 and 12 as an example, the operation in this case will be described with reference to FIG. 9 showing the main part of the data processing device. In the figure, when the DMAC 17 receives the transfer request from the input / output device 14, the data strobe signal DS1 and the read / write signal R / W1 instructing the write are sent to the input / output device 14 via the control bus of the system bus 11. Output to. At the same time, the transfer address ADR is output to the memory 15 via the address bus of the system bus 12 and the buffer 18, and the DMAC 17 also reads / writes the address strobe signal AS2, the data strobe signal DS2, and the write instruction signal. R / W2 is output to the memory 15 via the control bus of the system bus 12. Furthermore, confirmation signal AC from DMAC17
K is supplied to the input / output device 14 via the control bus of the system bus 11. As a result, the data from the input / output device 14 is single-transferred to the memory 15 via the data bus of the system bus 11, the buffer 19, and the data bus of the system bus 12.

In this case, the transfer direction when the buffers 18 and 19 are turned on is controlled by the DMAC 17 to switch from the system bus 11 to the system bus 12.

The timing of various signals in this case is as shown in the case in FIG.
Shown as VI.

In the above case, the timing of various signals when the input / output device 14 outputs the ready signal IOREADY to the DMAC 17 is shown as a case VIII in FIG. In case VIII, the DMAC 17 sends the ready signal IOREADY from the I / O device 14.
When the input comes, the data strobe signal DS2 to the memory 15 is activated and the data complete signal DC2 from the memory 15 is seen to complete the transfer.

Next, an embodiment of the terminal control unit of the DMAC 17 that generates and outputs the various control signals will be described with reference to FIG. The terminal control unit generally includes a control information control unit 43, a register 44, a decoder 45, a transfer information generation unit 46, and an output signal generation unit 47. The control information control unit 43 uses the internal address bus 41 of the DMAC 17.
The information set timing sequencer 48 connected to
Latch circuit 49 connected to internal data bus 42 of DMAC17
And a programmable logic array (PLA) 50 for creating transfer information.

The timing sequencer 48 controls the latch timing of the latch circuit 49 based on the address information from the internal address bus 41, and the PLA 50 performs the single transfer or the like based on the transfer information obtained from the internal data bus 42 via the latch circuit 49. Information about various control signals used for is created and stored in the register 44. The transfer information from the internal data bus 42 includes whether the source is the memory 13 on the system bus 11 side, the transfer is a single transfer, and so on.
The information output from A50 includes, for example, information indicating whether the address strobe signal AS1 is activated. On the other hand, the transfer information generation unit 46 generates and outputs other transfer information and supplies it to the decoder 45. As a result, the decoder 45
Based on the information from the register 44 and the transfer information generation unit 46, it outputs information about various control signals according to the transfer mode. The output signal generator 47 uses the information from the decoder 45 to control the various control signals AS1, AS1 according to the timing of the clock signal.
It outputs DS1, R / W1, AS2, DS2, R / W2, ACK and control signals for controlling buffers 18 and 19.

According to this embodiment, for example, the DMAC 17 to the system bus 11
It does not say that the control signal output to the system bus 12 is used to generate the control signal output to the DMAC.
Reference numeral 17 generates a control signal dedicated to each system bus 11 and 12. Therefore, it is not necessary to control the devices connected to the respective system buses 11 and 12 by a complicated control circuit, particularly when performing a single transfer across the system buses 11 and 12.

In the case of single transfer across the system buses 11 and 12, the data strobe signals DS1 and DS2 are output to the corresponding system buses 11 and 12, respectively. In the case of single transfer on the same system bus, as described above, the data strobe signal to the input / output device is generated from the read / write signal and the confirmation signal from the DMAC 17, for example. However, as is clear from FIG. 8, in cases V and VI, the same data strobe signal from the DMAC 17 can be used as DS1 and DS2. As a result, the circuit configuration for generating the data strobe signal at the time of single transfer across the two system buses can be simplified.

Further, as is clear from FIG. 8, in cases V to VIII,
The same read / write signal from DMAC17 can be used as R / W1 and R / W2. As a result, it is possible to simplify the circuit configuration for generating the read / write signal for single transfer across the two system buses. Further, at the time of single transfer on the same system bus, since the read / write signal for the memory is inverted by the inverter and supplied to the input / output device, no special circuit such as a selector for controlling the input / output device is required.

Although the present invention has been described with reference to the embodiments, the present invention can be variously modified according to the gist of the present invention, and these modifications are not excluded from the present invention.

〔The invention's effect〕

According to the present invention, during a single transfer across two independent system buses, the address strobe is output only to the memory, the data strobe signal is output on both system buses, and the read / write signals are also output on both system buses. Since it is output above, single transfer can be performed across two system buses without complicating the configuration of the data processing device, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a block diagram showing a main part of a data processing device to which an embodiment of the present invention is applied, and FIG. 3 is for explaining a single transfer on the same system bus. FIG. 4 is a timing chart for explaining a single transfer on the same system bus, and FIGS. 5 and 6 are single diagrams on the same system when an input / output device outputs an enable signal. FIG. 7 is a block diagram for explaining a transfer, FIG. 7 is a block diagram for explaining a single transfer across two system buses, and FIG. 8 is a timing chart for explaining a single transfer over two system buses. FIG. 9 is a block diagram for explaining a single transfer across two system buses, FIG. 10 is a block diagram showing an embodiment of the terminal control unit of the DMAC, and FIG. 11 is 2 Is a block diagram showing a conventional data processing apparatus which performs DMA transfer across the system bus. 1 to 10, 1 is a first system bus, 2 is a storage device, 3 is a second system bus, 4 is an input / output device, 5 is a DMA control device, 11, 12
Is a system bus, 13 and 15 are memories, 14 and 16 are input / output devices,
17 is a DMAC, 18 and 19 are bidirectional buffers, 41 is an internal address bus, 42 is an internal data bus, 43 is a control information control unit, 44 is a register, 45 is a decoder, 46 is a transfer information generation unit, and 47 is an output signal. A generator, 48 is a timing sequencer, 49 is a latch circuit, 50 is a PLA, and INV is an inverter.

Claims (2)

[Claims] 1. A second system bus (1) to which at least a storage device (2) is connected and a second system bus (1) to which at least an input / output device (4) is connected and which is independent of the first system bus. In the DMA controller (5) connected to the system bus (3) and controlling the DMA data transfer on one system bus and across both system buses, the storage device (2) to the input / output device (4) To the storage device during a single transfer across both system buses (1,3) to the first address strobe signal (AS
1), a first data strobe signal (DS1), and a first read / write signal (R / W1) for instructing a read are output to the first system bus (1) and the input / output device To the second system bus (3) by outputting a second data strobe signal (DS2) and a second read / write signal (R / W2) for instructing read to the input / output device ( The second data strobe signal (DS2) to the input / output device during a single transfer from 4) to the storage device (2) across both system buses (3, 1)
Second read / write signal (R / W2) to instruct write and write
And are output to the second system bus (3),
A first address strobe signal (AS
1), a first data strobe signal (DS1), and a first read / write signal (R / W1) for instructing a write are output onto the first system bus (1).
Control device. 2. The DMA controller according to claim 1, wherein the first and second read / write signals (R / W1, R / W2) are signals of the same polarity.