JPH08330352A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH08330352A
JPH08330352A JP7133699A JP13369995A JPH08330352A JP H08330352 A JPH08330352 A JP H08330352A JP 7133699 A JP7133699 A JP 7133699A JP 13369995 A JP13369995 A JP 13369995A JP H08330352 A JPH08330352 A JP H08330352A
Authority
JP
Japan
Prior art keywords
cavity
cap
substrate
semiconductor chip
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7133699A
Other languages
Japanese (ja)
Other versions
JP2699929B2 (en
Inventor
Katsuhiko Suzuki
勝彦 鈴木
Katsunobu Suzuki
克信 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7133699A priority Critical patent/JP2699929B2/en
Publication of JPH08330352A publication Critical patent/JPH08330352A/en
Application granted granted Critical
Publication of JP2699929B2 publication Critical patent/JP2699929B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To provide a highly reliable package having low thermal resistance and temperature cycle resisting property at low cost. CONSTITUTION: A flip chip is connected to a glass epoxy substrate 1 by soldering, and the inside of a chip pad and the substrate are adhered by heat conductive and thermoplastic resin. Also, the cap 7 of a metal or glass epoxy substrate is adhered using heat conductive and thermoplastic resin, and the circumference of the cap 7 is adhesively sealed by heat conductive and thermoplastic resin.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
樹脂回路基板を用いたフリップチップ型の半導体装置に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a flip chip type semiconductor device using a resin circuit board.

【0002】[0002]

【従来の技術】従来のフリップチップ構造の半導体装置
の第1例として、特開平4−234139号公報の「半
導体チップの基板への直接取り付け法」に記載された図
4(A),(B),(C),(D),(E)の各断面図
を参照して、製造方法を説明する。まず図6(A)で
は、半導体チップ28の主表面上の各電極に、半田バン
プ又はポリイミドーシロキサン金の複合材バンプ24が
形成され、別途挿入材19が用意される。ここで、ポリ
マー挿入材19の製造方法は、200乃至250μm厚
のシリコンなどの熱可塑性誘電体エラストマー、熱可塑
性誘電体ポリマー、またはポリイミドとシロキサンなど
の共重合体、あるいはその他の様々なポリマー及び共重
合体のシートを用意し、このシートの片面には弱い接着
剤16を塗布し、さらに保護シート14で覆い、反対面
には逆に強い接着剤15を塗布する。次に、このシート
に半導体チップ28のパンプ24の配列ピッチとバンプ
径にあわせて、打ち抜き又はレーザ照射により孔13を
あける。この孔13のあいた保護シート14とポリマー
挿入材19とを半導体チップ28と同じ大きさにカット
し、(B)に示すように、シート面の強い接着剤15の
塗布面をチップ面にあわせて接着する。この時、シート
にあけた孔13は半導体チップ28の半田バンプ4に嵌
合するように位置決めする。
2. Description of the Related Art As a first example of a conventional semiconductor device having a flip-chip structure, FIGS. 4A and 4B described in "Direct attachment method of semiconductor chip to substrate" of Japanese Patent Laid-Open No. 4-234139. ), (C), (D), and (E) are cross-sectional views to describe the manufacturing method. First, in FIG. 6A, solder bumps or polyimide-siloxane gold composite material bumps 24 are formed on each electrode on the main surface of the semiconductor chip 28, and an insert material 19 is prepared separately. Here, the method for manufacturing the polymer insertion material 19 includes a thermoplastic dielectric elastomer such as silicon having a thickness of 200 to 250 μm, a thermoplastic dielectric polymer, a copolymer such as polyimide and siloxane, or various other polymers and copolymers. A polymer sheet is prepared, a weak adhesive 16 is applied to one side of the sheet, further covered with a protective sheet 14, and a strong adhesive 15 is applied to the opposite side. Next, holes 13 are formed in this sheet by punching or laser irradiation in accordance with the arrangement pitch of the pumps 24 of the semiconductor chip 28 and the bump diameter. The protective sheet 14 having the holes 13 and the polymer insertion material 19 are cut to the same size as the semiconductor chip 28, and the surface of the sheet having the strong adhesive 15 applied is aligned with the chip surface as shown in FIG. To glue. At this time, the holes 13 formed in the sheet are positioned so as to fit the solder bumps 4 of the semiconductor chip 28.

【0003】このシートの各孔13内には、共重合ポリ
イミドーシロキサンなどの熱可塑性ポリマーに導電性微
細金属を混合して形成される複合ペースト30が、スク
リーン印刷により生め込まれている。次に(C)に示す
様に、保護シート14を剥離して、弱い接着層16を露
出させる。(D)では、回路基板23のペーストバンプ
に対してチップパッド上に塗布したペーストを位置決め
している状態である。次の(E)では、基板23とチッ
プ28とに圧力を加えて接合した状態である。
In each hole 13 of this sheet, a composite paste 30 formed by mixing a conductive fine metal with a thermoplastic polymer such as copolymerized polyimide-siloxane is formed by screen printing. Next, as shown in (C), the protective sheet 14 is peeled off to expose the weak adhesive layer 16. In (D), the paste applied on the chip pads is positioned with respect to the paste bumps of the circuit board 23. In the next step (E), pressure is applied to the substrate 23 and the chip 28 to join them.

【0004】次に従来のフリップチップ構造の半導体装
置の第2例として、特開平3−12942号公報の「半
導体装置の封止方法および半導体チップ」に記載された
図5(A),(B),(C)を参照して、説明する。ま
ず図5(A)において、半導体ウエハ状態の半導体チッ
プ28にレジストを塗布・露光・現像をしてチップ電極
26の部分を開口させる。次に、半田メッキを施し半田
バンプ24を電極26上に形成する。その後、スピンコ
ートにより熱可塑性樹脂29を塗布し、加熱仮硬化させ
る。この状態で、半導体ウエハをダイシシンし、半導体
チップ28が用意される。この半導体チップ28を回路
基板23に接続する方法を説明する図5(B)におい
て、ホットプレート21上に置かれた回路基板23に、
ボンディングツール20で吸着した前記半導体チップ2
8を対向させ、フリップチップボンダで半田バンプ24
と基板電極22とを位置合わせする。次に、図5(C)
に示すようにボンディングツール20を下降させ、基板
電極22にチップ電極26を接触させ加圧する。ホット
プレート21の温度は、半田4が溶融する温度まで上昇
させ溶融接続する。
Next, as a second example of a conventional semiconductor device having a flip-chip structure, FIGS. 5A and 5B described in "Sealing Method of Semiconductor Device and Semiconductor Chip" in Japanese Patent Laid-Open No. 3-12942. ), (C). First, in FIG. 5A, a resist is applied, exposed, and developed on the semiconductor chip 28 in the state of a semiconductor wafer to open the portion of the chip electrode 26. Next, solder plating is applied to form solder bumps 24 on the electrodes 26. After that, the thermoplastic resin 29 is applied by spin coating and is temporarily cured by heating. In this state, the semiconductor wafer is diced and the semiconductor chip 28 is prepared. 5B for explaining a method of connecting the semiconductor chip 28 to the circuit board 23, the circuit board 23 placed on the hot plate 21 is
The semiconductor chip 2 adsorbed by the bonding tool 20
8 facing each other, and solder bumps 24 with a flip chip bonder.
And the substrate electrode 22 are aligned. Next, FIG. 5 (C)
As shown in, the bonding tool 20 is lowered to bring the chip electrode 26 into contact with the substrate electrode 22 and pressurize it. The temperature of the hot plate 21 is raised to a temperature at which the solder 4 is melted, so that the solder 4 is melted and connected.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上述し
た従来の第1例については、200〜250μmの厚さ
の熱可塑性ポリマーシートの孔13に熱可塑性ポリイミ
ドーシロキサン/金の複合材が充填されており、また回
路基板23の電極との電気的接続は、半導体チップ28
のポリマー挿入材19に付着されている弱い接着剤16
によって圧接接続されているだけであるので、接触抵抗
が温度サイクル等によって経時変化する心配があり、接
続上の信頼性が低下する心配がある。
However, in the first conventional example described above, the holes 13 of the thermoplastic polymer sheet having a thickness of 200 to 250 μm are filled with the thermoplastic polyimide-siloxane / gold composite material. And the electrical connection with the electrodes of the circuit board 23 is made by the semiconductor chip 28.
Adhesive 16 adhered to the polymer insert 19 of
Since the pressure resistance is only connected by pressure welding, there is a concern that the contact resistance may change over time due to a temperature cycle or the like, and the reliability of the connection may deteriorate.

【0006】またチップ28の取り外しは、加熱しなが
らポリマーシートの基板23との接着面から剥離は可能
と思われが、孔13に充填した熱硬化性ポリイミドーシ
ロキサン/金の複合材の破壊状態面が、基板電極面から
均一に剥がれないとモジュールの再生が難しくなる。
It is considered that the chip 28 can be removed from the surface of the polymer sheet which is adhered to the substrate 23 by heating, but the broken state of the thermosetting polyimide-siloxane / gold composite material filled in the hole 13 is removed. If the surface is not evenly peeled from the substrate electrode surface, it will be difficult to regenerate the module.

【0007】また、上述した従来の第2例については、
チップ電極26に半田24が付着されているが半田面を
含めてチップ全面に熱可塑性樹脂29が塗布されてい
る。この構造では加熱接続する時に基板電極22とチッ
プ電極(半田)26との間に樹脂29が挟み込まれて完
全な接続ができず接続されても接続抵抗にバラツキが生
じるという心配がある。
Regarding the above-mentioned second conventional example,
Although the solder 24 is attached to the chip electrode 26, the thermoplastic resin 29 is applied to the entire surface of the chip including the solder surface. In this structure, when the heating connection is performed, the resin 29 is sandwiched between the substrate electrode 22 and the chip electrode (solder) 26, and a perfect connection cannot be made. Even if the resin 29 is connected, the connection resistance may vary.

【0008】さらに、上述した従来の第1,第2例共に
回路基板の適切な材料が記載されとらず、この材料に何
を選ぶかによって、電極接続部が温度サイクル等の熱応
力試験で破壊する恐れがある。この理由は、例えば基板
材料にガラスエポキシを使用するとこの熱膨脹係数が2
00×10-7、半導体チップが24×10-7であり、基
板とチップの間隙に前述した樹脂またはポリマーシート
を挟んだ程度では、温度サイクル等の応力発生により電
極接続部の破壊発生があり、信頼性維持ができない。
Further, in the above-mentioned first and second conventional examples, an appropriate material for the circuit board is not described. Depending on what is selected for this material, the electrode connection portion is destroyed in a thermal stress test such as a temperature cycle. There is a risk of The reason for this is that when glass epoxy is used as the substrate material, the coefficient of thermal expansion is 2
00 × 10 -7 , the semiconductor chip is 24 × 10 -7 , and if the resin or polymer sheet described above is sandwiched in the gap between the substrate and the chip, the electrode connection part may be destroyed due to stress such as temperature cycle. , Reliability cannot be maintained.

【0009】また、半導体チップの保護としては、樹脂
コーティングした程度のものであり、耐湿性の確保なら
び放熱性を改善した低熱抵抗の半導体装置の供給が望ま
れている。
Further, as protection of the semiconductor chip, it is desired to supply a semiconductor device having a low thermal resistance, which is only to the extent of being coated with a resin, and which secures moisture resistance and improves heat dissipation.

【0010】以上のような諸問題点に鑑み、本発明は次
の課題を揚げる。
In view of the above problems, the present invention has the following problems.

【0011】(1)半導体チップの主表面上の電極と回
路基板上の対向電極との電気的及び機械的接続状態を良
好にすること。
(1) To improve the electrical and mechanical connection between the electrode on the main surface of the semiconductor chip and the counter electrode on the circuit board.

【0012】(2)温度サイクル等によって、接続部分
の接触抵抗が増大したり、接合力が低下したりしないよ
うにすること。
(2) To prevent the contact resistance of the connecting portion from increasing and the joining force from decreasing due to temperature cycle or the like.

【0013】(3)半導体チップの取り外し及び再度の
接続が容易に行えるようにすること。
(3) To facilitate removal and reconnection of the semiconductor chip.

【0014】(4)接続部分によって、接続抵抗にバラ
ツキが生じず、一様に接続されること。
(4) The connection resistance should not vary and the connection should be uniform.

【0015】(5)温度サイクル等の熱応力試験で、接
続部分が破壊されないようにすること。
(5) In a thermal stress test such as a temperature cycle, prevent the connecting portion from being destroyed.

【0016】(6)耐湿性を確保し、放熱性も改善する
こと。
(6) To secure moisture resistance and improve heat dissipation.

【0017】(7)低熱抵抗の構造とすること。(7) The structure should have a low thermal resistance.

【0018】(8)熱膨脹差の大きな材料を用いても、
バンプ接続部分が破壊されないようにすること。
(8) Even if a material having a large difference in thermal expansion is used,
Make sure the bump connection is not destroyed.

【0019】(9)接続部分の信頼性を向上し、もって
半導体装置としての信頼性を高めること。
(9) To improve the reliability of the connection portion, and thus to improve the reliability of the semiconductor device.

【0020】[0020]

【課題を解決するための手段】本発明の第1の半導体装
置の構成は、絶縁性基板の裏面に凹状のキャビティを形
成し、前記キャビティの周囲の前記裏面に外部バンプ又
は外部リードピンを形成し、前記キャビティの底面と半
導体チップの主表面とが第1の樹脂で固着され、前記外
部バンプ又は外部リードピンと電気的に接続されかつ前
記キャビティの底面に形成された内部バンプと前記半導
体チップの電極とが半田接続され、前記半導体チップの
裏面とキャップとが第2の樹脂で固着され、前記キャッ
プと前記キャビティとが第3の樹脂で固着されているこ
とを特徴とする。
According to the first semiconductor device of the present invention, a concave cavity is formed on the back surface of an insulating substrate, and external bumps or external lead pins are formed on the back surface around the cavity. An inner bump formed on the bottom surface of the cavity and an electrode of the semiconductor chip, the bottom surface of the cavity being fixed to the main surface of the semiconductor chip with a first resin, being electrically connected to the external bump or the external lead pin Are solder-connected, the back surface of the semiconductor chip and the cap are fixed with a second resin, and the cap and the cavity are fixed with a third resin.

【0021】特に前記キャビティの底面が、放熱メタル
となっていることを特徴とし、さらに前記放熱メタルと
前記キャップとが同一材料からなることを特徴とする。
In particular, the bottom surface of the cavity is made of a heat radiation metal, and the heat radiation metal and the cap are made of the same material.

【0022】また特に前記キャビティの底面に多数の放
熱ビアが形成されていることを特徴とする。
In particular, a large number of heat radiation vias are formed on the bottom surface of the cavity.

【0023】本発明の第2の半導体装置の構成は、絶縁
性基板の主表面に内部バンプを形成し、前記基板の裏面
に、前記内部バンプと電気的に接続された外部バンプ又
は外部リードピンを形成し、キャップの裏面に凹状のキ
ャビティを形成し、前記キャビティの底面と半導体チッ
プの裏面とが第1の樹脂で固着され、前記半導体チップ
の主表面の電極と前記内部バンプとが半田接続され、前
記半導体チップの主表面と前記基板とが第2の樹脂で固
着され、前記キャップのキャビティの周端と前記基板と
が第3の樹脂で固着されていることを特徴とする。
According to the second semiconductor device of the present invention, internal bumps are formed on the main surface of the insulating substrate, and external bumps or external lead pins electrically connected to the internal bumps are formed on the back surface of the substrate. Forming a concave cavity on the back surface of the cap, the bottom surface of the cavity and the back surface of the semiconductor chip are fixed with a first resin, and the electrodes on the main surface of the semiconductor chip and the internal bumps are solder-connected. The main surface of the semiconductor chip and the substrate are fixed with a second resin, and the peripheral edge of the cavity of the cap and the substrate are fixed with a third resin.

【0024】前記第1又は第2の構成の半導体装置にお
いて、特に前記第1,第2,第3の樹脂が共通した熱可
塑性樹脂であることを特徴とし、またキャップの素材と
して、銅又はアルミニウムあるいはガラスエポキシ樹脂
が使用されていることも特徴とする。
In the semiconductor device having the first or second structure, particularly, the first, second, and third resins are common thermoplastic resins, and the cap material is copper or aluminum. Alternatively, it is also characterized in that glass epoxy resin is used.

【0025】[0025]

【実施例】本発明の第1の実施例を示す図1の断面図を
参照すると、この実施例のカラスエポキシ基板1の構造
は、基板の裏面の略中央にチップ搭載部2となる凹状の
キャビティを設け、このキャビティの周辺には、他の回
路基板1と接続するための半田バンプ4が多数設けらて
いる。この半田バンプ4の代わりに、後述する図3のリ
ードピン5を設けても良い。LSIの半導体チップ8の
搭載部2のキャビティ底面には、このチップ8の電極に
各々対向する内部の半田バンプ3が設けられている。キ
ャビティの内部バンプ3は、基板1の裏面の半田バンプ
4と、電気的に各々接続されるように、基板1の内部に
は配線パターンがあり、ホールを介して外部バンプ4ま
で導出されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the sectional view of FIG. 1 showing a first embodiment of the present invention, the structure of a glass epoxy substrate 1 of this embodiment has a concave shape which is to be a chip mounting portion 2 substantially at the center of the back surface of the substrate. A cavity is provided, and a large number of solder bumps 4 for connecting to another circuit board 1 are provided around the cavity. Instead of the solder bumps 4, lead pins 5 of FIG. 3 described later may be provided. On the bottom surface of the cavity of the mounting portion 2 of the semiconductor chip 8 of the LSI, internal solder bumps 3 facing the electrodes of the chip 8 are provided. The internal bumps 3 of the cavity have a wiring pattern inside the substrate 1 so as to be electrically connected to the solder bumps 4 on the back surface of the substrate 1, and are led out to the external bumps 4 through the holes. .

【0026】キャップ7は、基板1と同じ材料であるガ
ラスエポキシ基板を用いる。熱可塑性樹脂接着剤9とし
て商品名「スティスティックス」を、このキャップ7の
上面に接着する。チップ8の主表面のうち周辺電極を除
いた内面に、シート状の同じ接着剤9を接着しておく。
また、キャップ7の周辺にも同じ接着剤を塗布してお
く。次の工程で、前記ガラスエポキシ基板1の半田バン
プ3と半導体チップ8の電極とをフリップチップボンダ
により位置合わせした後、窒素雰囲気中で半田を加熱溶
融し、さらに、上記接着剤9をすべて軟化させ接着す
る。この作業により、チップ8の電極と基板1のバンプ
3が接続され、基板1の面とチップ8は熱伝導接着剤で
接着され、キャップ7の周辺は、基板1のキャビティの
内側面で封止されている。前記ガラスエポキシ基板1の
チップ接続部は、多数の放熱ビア11が設けられてい
る。この放熱ビア11は、0.2乃至0.3mmφのド
リル穴にCuメッキをしたものである。
As the cap 7, a glass epoxy substrate which is the same material as the substrate 1 is used. As the thermoplastic resin adhesive 9, a product name "Stix" is adhered to the upper surface of the cap 7. The same sheet-shaped adhesive 9 is adhered to the inner surface of the main surface of the chip 8 excluding the peripheral electrodes.
Also, the same adhesive is applied around the cap 7. In the next step, after the solder bumps 3 of the glass epoxy substrate 1 and the electrodes of the semiconductor chip 8 are aligned by the flip chip bonder, the solder is heated and melted in a nitrogen atmosphere, and the adhesive 9 is all softened. Let it adhere. By this operation, the electrodes of the chip 8 and the bumps 3 of the substrate 1 are connected, the surface of the substrate 1 and the chip 8 are bonded with a heat conductive adhesive, and the periphery of the cap 7 is sealed with the inner surface of the cavity of the substrate 1. Has been done. The chip connection portion of the glass epoxy substrate 1 is provided with a large number of heat radiation vias 11. The heat radiation via 11 is a drill hole of 0.2 to 0.3 mmφ plated with Cu.

【0027】まず、この放熱ビア全面に、75乃至12
5μm厚のシート状で熱伝導性が良好な可塑性樹脂の接
着剤9を仮接着し、次にチップ8を接着し、次にキャッ
プ7の中央にシート状熱伝導性熱可塑性樹脂接着剤9を
仮接着しておく。このキャップ7を、前記半導体チップ
8の裏面から被せるように、回路基板3の周辺とキャッ
プ7周辺を上述した通り、位置決めしながら加熱接着す
る。チップ8と基板1との間隙の樹脂9により、温度サ
イクル時に発生する応力を半減する構造である。このよ
うにして、第1の実施例の半導体装置が完成する。この
キャップ7は、チップ8の裏面とキャップ7周辺とに同
一の接着材料で接着され、気密封止が保たれ、バンプ接
続部の熱応力の緩和にも寄与している。尚、半導体チッ
プの電極レイアウトは、4辺に配置した単列又は千鳥状
の複数列とする。
First, 75 to 12 are formed on the entire surface of the heat dissipation via.
A sheet-shaped heat conductive thermoplastic resin adhesive 9 having a thickness of 5 μm, which is made of a plastic resin having a good thermal conductivity, is temporarily adhered, and then the chip 8 is adhered. Temporarily adhere. The periphery of the circuit board 3 and the periphery of the cap 7 are heat-bonded while positioning as described above so that the cap 7 is covered from the back surface of the semiconductor chip 8. The resin 9 in the gap between the chip 8 and the substrate 1 reduces the stress generated during the temperature cycle by half. Thus, the semiconductor device of the first embodiment is completed. The cap 7 is adhered to the back surface of the chip 8 and the periphery of the cap 7 with the same adhesive material to keep airtightness and contributes to alleviation of thermal stress in the bump connecting portion. The electrode layout of the semiconductor chip is a single row arranged in four sides or a plurality of staggered rows.

【0028】本発明の第2実施例を示す図2の断面図を
参照すると、この実施例は、上述した第1の実施例との
違いについてのみ説明する。この実施例のガラスエポキ
シ基板1のキャビティに、放熱ビア11の代わりとし
て、放熱メタル12が用いられ、基板1を貫通して取付
けている。またキャップ7も、放熱メタル12と熱膨脹
係数が同じ素材か又は極めて近い材料がよい。例えばこ
の材料としては、銅(熱膨脹係数160乃至170×1
-7、熱伝導率403W/M/K)、またはアルミニウ
ム(熱膨脹係数203×10-7、熱伝導率236W/M
/K)が好ましい。この材料組み合わせにおいても、製
造方法は第1の実施例と同じである。
Referring to the cross-sectional view of FIG. 2 showing a second embodiment of the present invention, this embodiment will only describe the differences from the first embodiment described above. In the cavity of the glass epoxy substrate 1 of this embodiment, a heat radiating metal 12 is used instead of the heat radiating via 11, and is attached through the substrate 1. Further, the cap 7 is also preferably made of a material having a thermal expansion coefficient the same as or very close to that of the heat dissipation metal 12. For example, this material may be copper (coefficient of thermal expansion 160 to 170 × 1).
0 -7 , thermal conductivity 403 W / M / K, or aluminum (coefficient of thermal expansion 203 × 10 -7 , thermal conductivity 236 W / M)
/ K) is preferred. Also in this material combination, the manufacturing method is the same as that of the first embodiment.

【0029】この構造の熱放散は、放熱メタル12側と
半導体チップ8裏面側とに分散されるので、極めて低熱
抵抗が可能であり、大出力のパワートランジスタが使用
できる。例えば、充分なる大きさの外付けヒートシンク
(図示せず)を取り付けたと仮定すると、1〜2℃/W
の低熱抵抗のパッケージの実現も可能である。また、半
田バンプ3の接続部の熱応力による破壊はなく、放熱メ
タル12とキャップ7との熱膨脹係数が近いので、加熱
・収縮による膨脹は両面で同様の膨脹・伸縮を行う。こ
の結果、半田バンプ3の剪断応力を最小限にする事が出
来る。
Since the heat dissipation of this structure is distributed to the heat dissipation metal 12 side and the rear surface side of the semiconductor chip 8, extremely low heat resistance is possible and a high output power transistor can be used. For example, assuming that an external heat sink (not shown) of a sufficient size is attached, 1-2 ° C./W
It is also possible to realize a package with low thermal resistance. Further, since there is no breakage due to the thermal stress at the connection portion of the solder bump 3 and the thermal expansion coefficient of the heat radiating metal 12 and the cap 7 are close to each other, expansion due to heating / contraction causes similar expansion / contraction on both sides. As a result, the shearing stress of the solder bump 3 can be minimized.

【0030】本発明の第3の実施例は、上述した第2の
実施例で示した図2と構造及び製造方法上は共通してい
るが、第2の実施例と相違する点は、キャップ7の材質
としてガラスエポキシ基板を用いている事である。半田
バンプ3の熱応力による破壊は、第1,第2の実施例と
同様な原理により、応力を最小限に抑える効果がある。
The third embodiment of the present invention has the same structure and manufacturing method as FIG. 2 shown in the above-mentioned second embodiment, but is different from the second embodiment in that the cap is different. It means that a glass epoxy substrate is used as the material of 7. The destruction of the solder bumps 3 due to the thermal stress has an effect of minimizing the stress according to the same principle as in the first and second embodiments.

【0031】本発明の第4の実施例は、第1の実施例の
構造及び製造方法と共通するが、この実施例のキャップ
7の材質が、ガラスエポキシではなく、銅またはアルミ
ニウムを用いている。ガラスエポキシ基板1等は、第1
の実施例と共通している。
Although the fourth embodiment of the present invention is common to the structure and manufacturing method of the first embodiment, the material of the cap 7 of this embodiment is copper or aluminum instead of glass epoxy. . The glass epoxy substrate 1 etc. is the first
It is common with the embodiment of.

【0032】本発明の第5の実施例を示す図3を参照す
ると、この実施例は、半導体チップがフェースダウン構
造となっており、上述した第1乃至大4の実施例のフェ
ースアップ構造と相違している。
Referring to FIG. 3 showing a fifth embodiment of the present invention, in this embodiment, the semiconductor chip has a face-down structure, and the face-up structure of the first to fourth embodiments described above is used. It's different.

【0033】この実施例は、リードピン5が使用されて
いるが、この他に図1の如く球状あるいは半球状のバン
プであってよい。キャップ6の略中央部には、凹状のキ
ャビティが形成され、第1の実施例の樹脂9と共通した
樹脂が、半導体チップ8の裏面とキャビティとの間及び
半導体チップ8の主表面と基板1との間に、使用され
る。
Although the lead pin 5 is used in this embodiment, it may be a spherical or hemispherical bump as shown in FIG. A concave cavity is formed substantially in the center of the cap 6, and the resin common to the resin 9 of the first embodiment is used between the back surface of the semiconductor chip 8 and the cavity and between the main surface of the semiconductor chip 8 and the substrate 1. Used between.

【0034】キャップ6は、基板1の方形平面と共通し
た寸法を有し、この材料として銅またはアルミニウム等
の金属を用い、放熱性を改善している。このキャップ6
は、ガラスエポキシ樹脂であってもよい。基板1等の材
料は、上述した第1の実施例と共通する。
The cap 6 has the same dimensions as the rectangular plane of the substrate 1, and a metal such as copper or aluminum is used as this material to improve heat dissipation. This cap 6
May be a glass epoxy resin. The material of the substrate 1 and the like is the same as that of the first embodiment described above.

【0035】以上の通り、本発明の各実施例によれば、
半導体チップ8は、両面から特に同一材料で挟まれてお
り、温度サイクルの熱膨脹・収縮に対して、チップ8が
基板1に追従するため、バンプ接続部の応力の緩和に寄
与する。また発熱部から直接基板とキャップとに伝達さ
れるので、熱抵抗が低く、放熱効果が高い。また、使用
した熱可塑性樹脂9は、エポキシ樹脂よりも水分の透過
性が少ないので、耐湿性が向上する。また、リペア性
は、接着作業温度よりも若干高くして引き剥がすことに
より、簡単に剥離することができるため、著しく向上す
る。
As described above, according to each embodiment of the present invention,
The semiconductor chip 8 is sandwiched by the same material from both sides, and the chip 8 follows the substrate 1 with respect to thermal expansion / contraction of the temperature cycle, which contributes to alleviation of stress at the bump connection portion. Further, since the heat is directly transmitted from the heat generating portion to the substrate and the cap, the heat resistance is low and the heat radiation effect is high. Further, since the thermoplastic resin 9 used has a lower moisture permeability than the epoxy resin, the moisture resistance is improved. Further, the repairability is remarkably improved because it can be easily peeled off by peeling the repairability slightly higher than the bonding work temperature.

【0036】[0036]

【発明の効果】以上説明したように、本発明によれば、
半導体チップと膨脹係数が大幅に異なる材料をバンプ接
続した時に、熱膨脹差によりバンプ接続部の破壊を防止
する効果と、大発熱量の半導体チップからの放熱を効率
的に行い低熱抵抗で高信頼性の半導体装置を供給する効
果が得られ、さらに基板にベアチップ実装する上でバン
プの破壊がなく、温度サイクルの耐性が向上し、チップ
表面からの放熱性も向上し、10℃/W以下の耐湿性も
向上し、セラミックパッケージに近い耐湿性を有する等
の効果が得られ、上述した各課題がことごとく達成され
る。
As described above, according to the present invention,
When bump-bonding a material whose coefficient of expansion is significantly different from that of the semiconductor chip, the effect of preventing damage to the bump connection part due to the difference in thermal expansion, and efficient heat dissipation from the semiconductor chip with a large heat generation, low thermal resistance and high reliability The effect of supplying the semiconductor device described above is obtained, bumps are not broken when mounted on a substrate as a bare chip, temperature cycle resistance is improved, heat dissipation from the chip surface is also improved, and moisture resistance of 10 ° C / W or less is achieved. The properties are also improved, and the effects such as having moisture resistance close to that of a ceramic package are obtained, and the above-mentioned respective problems are all achieved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1,第4の実施例の半導体装置を示
す断面図である。
FIG. 1 is a sectional view showing a semiconductor device according to first and fourth embodiments of the present invention.

【図2】本発明の第2,第3の実施例の半導体装置を示
す断面図である。
FIG. 2 is a sectional view showing a semiconductor device of second and third embodiments of the present invention.

【図3】本発明の第5の実施例を示す断面図である。FIG. 3 is a sectional view showing a fifth embodiment of the present invention.

【図4】(A)乃至(E)は従来の第1例の半導体装置
の製造方法を工程順に示す断面図である。
4A to 4E are cross-sectional views showing, in the order of steps, a method for manufacturing a conventional semiconductor device according to a first example.

【図5】(A)乃至(C)は従来の第2例の半導体装置
の製造方法を工程順に示す断面図である。
5A to 5C are cross-sectional views showing, in the order of steps, a method for manufacturing a conventional semiconductor device according to a second example.

【符号の説明】[Explanation of symbols]

1 配線基板 2 チップ搭載部 3,4,24 半田バンプ 5 リードピン 6,7 キャップ 8,28 半導体チップ 9,29 熱可塑性樹脂 11 放熱ビア 12 放熱メタル 13 孔 14 保護シート 15,16 接着剤 19 ポリマー挿入剤 20 ボンディングツール 22 基板電極 21 ホットプレート 23 回路基板 26 チップ電極 30 複合ペースト 1 Wiring board 2 Chip mounting part 3,4,24 Solder bump 5 Lead pin 6,7 Cap 8,28 Semiconductor chip 9,29 Thermoplastic resin 11 Heat dissipation via 12 Heat dissipation metal 13 Hole 14 Protection sheet 15,16 Adhesive 19 Polymer insertion Agent 20 Bonding tool 22 Substrate electrode 21 Hot plate 23 Circuit board 26 Chip electrode 30 Composite paste

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板の裏面に凹状のキャビティを
形成し、前記キャビティの周囲の前記裏面に外部バンプ
又は外部リードピンを形成し、前記キャビティの底面と
半導体チップの主表面とが第1の樹脂で固着され、前記
外部バンプ又は外部リードピンと電気的に接続されかつ
前記キャビティの底面に形成された内部バンプと前記半
導体チップの電極とが半田接続され、前記半導体チップ
の裏面とキャップとが第2の樹脂で固着され、前記キャ
ップと前記キャビティとが第3の樹脂で固着されている
ことを特徴とする半導体装置。
1. A concave cavity is formed on the back surface of an insulating substrate, an external bump or an external lead pin is formed on the back surface around the cavity, and the bottom surface of the cavity and the main surface of the semiconductor chip are first. An internal bump, which is fixed by a resin, is electrically connected to the external bump or the external lead pin and is formed on the bottom surface of the cavity and the electrode of the semiconductor chip is soldered, and the back surface of the semiconductor chip and the cap are 2. A semiconductor device characterized in that it is fixed with a second resin, and the cap and the cavity are fixed with a third resin.
【請求項2】 前記キャビティの底面が、放熱メタルと
なっている請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein a bottom surface of the cavity is a heat dissipation metal.
【請求項3】 前記放熱メタルと前記キャップとが同一
材料からなる請求項1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the heat dissipation metal and the cap are made of the same material.
【請求項4】 前記キャビティの底面に、多数の放熱ビ
アが形成されている請求項1記載の半導体装置。
4. The semiconductor device according to claim 1, wherein a large number of heat dissipation vias are formed on the bottom surface of the cavity.
【請求項5】 絶縁性基板の主表面に内部バンプを形成
し、前記基板の裏面に、前記内部バンプと電気的に接続
された外部バンプ又は外部リードピンを形成し、キャッ
プの裏面に凹状のキャビティを形成し、前記キャビティ
の底面と半導体チップの裏面とが第1の樹脂で固着さ
れ、前記半導体チップの主表面の電極と前記内部バンプ
とが半田接続され、前記半導体チップの主表面と前記基
板とが第2の樹脂で固着され、前記キャップのキャビテ
ィの周端と前記基板とが第3の樹脂で固着されているこ
とを特徴とする半導体装置。
5. An internal bump is formed on the main surface of an insulating substrate, an external bump or an external lead pin electrically connected to the internal bump is formed on the back surface of the substrate, and a concave cavity is formed on the back surface of the cap. The bottom surface of the cavity and the back surface of the semiconductor chip are fixed by a first resin, the electrodes on the main surface of the semiconductor chip and the internal bumps are solder-connected, and the main surface of the semiconductor chip and the substrate are formed. Are fixed by a second resin, and the peripheral edge of the cavity of the cap and the substrate are fixed by a third resin.
【請求項6】 前記第1,第2,第3の樹脂は共通した
熱可塑性樹脂である請求項1又は5記載の半導体装置。
6. The semiconductor device according to claim 1, wherein the first, second and third resins are common thermoplastic resins.
【請求項7】 前記キャップの素材として、銅又はアル
ミニウムあるいはガラスエポキシ樹脂が使用されている
請求項1又は5記載の半導体装置。
7. The semiconductor device according to claim 1, wherein copper, aluminum, or glass epoxy resin is used as a material of the cap.
JP7133699A 1995-05-31 1995-05-31 Semiconductor device Expired - Lifetime JP2699929B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7133699A JP2699929B2 (en) 1995-05-31 1995-05-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7133699A JP2699929B2 (en) 1995-05-31 1995-05-31 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH08330352A true JPH08330352A (en) 1996-12-13
JP2699929B2 JP2699929B2 (en) 1998-01-19

Family

ID=15110825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7133699A Expired - Lifetime JP2699929B2 (en) 1995-05-31 1995-05-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2699929B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6265772B1 (en) 1998-06-17 2001-07-24 Nec Corporation Stacked semiconductor device
WO2001065602A1 (en) * 2000-02-28 2001-09-07 Hitachi Chemical Co., Ltd. Wiring board, semiconductor device, and method of manufacturing wiring board
JP2001313467A (en) * 2000-02-21 2001-11-09 Ngk Spark Plug Co Ltd Wiring board
US6520821B1 (en) 1998-05-18 2003-02-18 Nec Corporation Device package and device encapsulation method
CN107946250A (en) * 2017-12-20 2018-04-20 中科院微电子研究所昆山分所 A kind of method for packing of semiconductor chip and semiconductor chip
CN111354683A (en) * 2018-12-21 2020-06-30 深南电路股份有限公司 Chip substrate and manufacturing method thereof, packaged chip and packaging method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4480818B2 (en) * 1999-09-30 2010-06-16 株式会社ルネサステクノロジ Semiconductor device

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JPS62249429A (en) * 1986-04-23 1987-10-30 Hitachi Ltd Semiconductor device
JPH04369846A (en) * 1991-03-25 1992-12-22 Matsushita Electric Works Ltd Method of mounting semiconductor device

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JPS62249429A (en) * 1986-04-23 1987-10-30 Hitachi Ltd Semiconductor device
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US6828728B2 (en) 1998-05-18 2004-12-07 Samsung Sdi Co., Ltd. Device package with hermetically sealed cap
US7224119B2 (en) 1998-05-18 2007-05-29 Samsung Sdi Co., Ltd. Device package with a thermoplastic encapsulation cap and device encapsulation method
US6929523B2 (en) 1998-05-18 2005-08-16 Samsung Sdi Co., Ltd. Device package with hermetically sealed cap and device encapsulation method
US6520821B1 (en) 1998-05-18 2003-02-18 Nec Corporation Device package and device encapsulation method
KR100395037B1 (en) * 1998-05-18 2003-08-19 닛폰 덴키 가부시끼 가이샤 Device package and device encapsulation method
US6265772B1 (en) 1998-06-17 2001-07-24 Nec Corporation Stacked semiconductor device
JP2001313467A (en) * 2000-02-21 2001-11-09 Ngk Spark Plug Co Ltd Wiring board
JP4685979B2 (en) * 2000-02-21 2011-05-18 日本特殊陶業株式会社 Wiring board
JP2001244365A (en) * 2000-02-28 2001-09-07 Hitachi Chem Co Ltd Wiring board, semiconductor device and method of manufacturing wiring board
WO2001065602A1 (en) * 2000-02-28 2001-09-07 Hitachi Chemical Co., Ltd. Wiring board, semiconductor device, and method of manufacturing wiring board
US7704799B2 (en) 2000-02-28 2010-04-27 Hitachi Chemical Co., Ltd. Method of manufacturing wiring substrate
CN107946250A (en) * 2017-12-20 2018-04-20 中科院微电子研究所昆山分所 A kind of method for packing of semiconductor chip and semiconductor chip
CN107946250B (en) * 2017-12-20 2024-04-09 昆山微电子技术研究院 Semiconductor chip and packaging method thereof
CN111354683A (en) * 2018-12-21 2020-06-30 深南电路股份有限公司 Chip substrate and manufacturing method thereof, packaged chip and packaging method thereof

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