TWI393192B - Fabricating process of a chip package structure - Google Patents

Description

Chip package structure process

The present invention relates to a wafer package structure process, and more particularly to a wafer package structure process utilizing at least two B-stage adhesive layers to bond a substrate.

As the input/output contacts of integrated circuits increase, wafer packaging technology becomes more diverse. This is due to the fact that the flip chip interconnection technology minimizes the size of the chip package and reduces the signal transmission path and the like. The most common chip package structures employing flip chip interconnect technology include chip package structures such as Flip Chip Ball Grid Arrays and Flip Chip Pin Grid Arrays.

The flip chip interconnect technology employs a method of defining an array of regions by providing a plurality of pads on the active surface of the wafer and forming a plurality of bumps on the pads, respectively. Next, the wafer is flipped over to connect the solder bumps of the wafer and the plurality of contact pads disposed on a carrier such as a circuit substrate, respectively. Thus, the wafer is electrically connected by bumps and mechanically coupled to the carrier. Additionally, the wafer can be electrically connected to the external electronic device through the internal circuitry of the carrier. Generally, there are several types of bumps, such as solder bumps, gold bumps, copper bumps, conductive polymer bumps, polymer bumps, and the like.

1 is a schematic cross-sectional view of a chip package structure having polymer bumps. Referring to FIG. 1 , the chip package structure 100 includes a first substrate 110 , a plurality of polymer bumps 120 , a wafer 130 , and a solder 140 . First substrate 110 There is a surface 110a on which a plurality of contact pads 112 are disposed. The wafer 130 has an active surface 130a on which a plurality of pads 132 are disposed. The polymer bumps 120 made of a polymer material having conductive properties are respectively disposed between the contact pads 112 and the pads 132 to electrically connect the substrate 110 and the wafer 130. Since the polymer bumps 120 do not adhere to the contact pads 112, the solder 140 is required to fix the polymer bumps 120 on the substrate 110. The surface A of the solder 140 is attached to the contact pad 112, and the surface B thereof is attached to the polymer bump 120. Therefore, when the chip package structure is subjected to an external force or thermal stress (not shown), the solder 140 is detached from the contact pads 112, and the polymer bumps 120 will no longer be electrically connected to the contact pads 112. Obviously, the reliability of the chip package structure 100 is low.

The present invention provides a wafer package structure process with improved reliability.

The invention provides a wafer package structure process. First, a first substrate having a plurality of first pads and a second substrate having a plurality of second pads are provided, and a plurality of bumps are formed on the first pads of the first substrate. A first second-order adhesive layer is formed on the first substrate and B-staged (eg, pre-cured or partially cured) to form a first B-stage adhesive layer. A second second-order adhesive layer is formed on the second substrate and B-staged to form a second B-stage adhesive layer. Then, the first substrate and the second substrate are bonded through the first B-stage adhesive layer and the second B-stage adhesive layer, so that each of the first pads is electrically connected to the corresponding second pad through one of the bumps. B-staged first second-order adhesive layer The method of bonding to the second second-order adhesive layer includes heating (thermal curing) or ultraviolet curing.

In an embodiment of the invention, the first substrate and the second substrate are both wafers.

In an embodiment of the invention, the first substrate is a carrier and the second substrate is a wafer.

In an embodiment of the invention, the first substrate is a wafer and the second substrate is a carrier.

In an embodiment of the invention, the bump is a wire bump formed by a wire bonding process or a plated bump formed by an electroplating process. These bumps are gold bumps, copper bumps or solder bumps.

In an embodiment of the invention, the first second-order adhesive layer is formed by screen printing, brushing, spraying, spin coating or dipping.

In an embodiment of the invention, the second second-order adhesive layer is formed by screen printing, brushing, spraying, spin coating or dipping.

In one embodiment of the invention, the method of forming the first B-stage adhesive layer includes forming a plurality of first second-order adhesive blocks to enclose the bumps, and B-stage (such as pre-curing or partial curing). The second-order adhesive block forms a plurality of first B-stage adhesive blocks.

In one embodiment of the invention, a method of forming a second B-stage adhesive layer includes forming a plurality of second second-order adhesive blocks on the second pads, and B-staged the second second-order adhesive blocks to form a plurality of The second B-stage adhesive block.

In an embodiment of the invention, each of the second B-stage adhesive blocks is a hollow block having an opening to expose one of the second welds respectively. pad. In another possible embodiment, when the second B-stage adhesive block is electrically conductive or non-conductive, the first B-stage adhesive layer is electrically conductive. In another embodiment, when the second B-stage adhesive block is electrically conductive or non-conductive, the first B-stage adhesive layer is non-conductive. Some conductive particles (such as silver particles, copper particles, and gold particles) are doped to the first B-stage adhesive layer or the second B-stage adhesive layer to make the first B-stage adhesive layer or the second B-stage adhesive layer conductive.

In an embodiment of the invention, the second second-order adhesive layer is completely formed on the second substrate, and the method for forming the first B-stage adhesive layer comprises forming a plurality of first second-order adhesive blocks to surround the The bumps, and B-stage the first second-order adhesive blocks to form a plurality of first B-stage adhesive blocks.

In an embodiment of the invention, in addition to the area occupied by the bumps, the first second-order adhesive layer is completely formed on the first substrate, and the method of forming the second B-stage adhesive layer includes forming on the second pads. a plurality of second second-order adhesive blocks, and B-staged second second-order adhesive blocks to form a plurality of second B-stage adhesive blocks.

In an embodiment of the invention, the constituent component of the first B-stage adhesive layer is substantially equivalent to the constituent component of the second B-stage adhesive layer. Further, the glass transition temperature (Tg) of the first B-stage adhesive layer is, for example, higher than, equal to, or lower than the glass transition temperature of the second B-stage adhesive layer.

In an embodiment of the invention, the first second-order adhesive layer and the second second-order adhesive layer are sequentially B-staged to form a first B-stage adhesive layer and a second B-stage adhesive layer.

In an embodiment of the invention, the first second-order adhesive layer and the second second-order adhesive layer are simultaneously B-staged to form the first B-stage adhesive layer and the first Two B-stage adhesive layer.

In the process of the chip package structure of the present invention, the first B-stage adhesive layer and the second B-stage adhesive layer are respectively formed on the first substrate and the second substrate, so as to be disposed between the first substrate and the second substrate. The bumps can be covered. When an external force or thermal stress acts on the chip package structure, the first B-stage adhesive layer and the second B-stage adhesive layer respectively provide support and protection, and prevent damage of the bumps, so that the reliability of the chip package structure is further obtained. Improvement.

The above described features and advantages of the present invention will be more apparent from the following description.

2A and 2B are schematic cross-sectional views showing a wafer package structure according to an embodiment of the present invention. Referring to FIG. 2A and FIG. 2B, the chip package structure 200 of the present invention includes a first substrate 210, a second substrate 220, a plurality of bumps 230a (shown in FIG. 2A) or 230b (shown in FIG. 2B). A first B-stage adhesive layer 240a and a second B-stage adhesive layer 240b. The first substrate 210 has a plurality of first pads 212. The second substrate 220 has a plurality of second pads 222 and the second substrate 220 is disposed above the first substrate 210. The bumps 230a and 230b are disposed between the first substrate 210 and the second substrate 220, wherein each of the first pads 212 is electrically connected to the corresponding second pad 222 through one of the bumps 230a and 230b. The first B-stage adhesive layer 240a is adhered to the first substrate 210. The second B-stage adhesive layer 240b is adhered between the first B-stage adhesive layer 240a and the second substrate 220. The first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b cover the bumps 230a and 230b. In addition, The constituent components of the first B-stage adhesive layer 240a may be substantially equivalent to the constituent components of the second B-stage adhesive layer 240b. As shown in FIG. 2A and FIG. 2B, the first B-stage adhesive layer 240a is adhered to the surface S1 of the first substrate 210 and the second B-stage adhesive layer 240b is adhered to the surface S2 of the second substrate 220. It should be noted that the present invention utilizes the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b to enhance the adhesion between the first substrate 210 and the second substrate 220, and can provide support and protection respectively to prevent convexity. The block is damaged, so that the reliability of the chip package structure can be improved.

As shown in FIG. 2A and FIG. 2B, in the present embodiment, the thickness of the first B-stage adhesive layer 240a is substantially equal to the thickness of the second B-stage adhesive layer 240b. However, based on actual design requirements, the thickness of the first B-stage adhesive layer 240a may also be different from the thickness of the second B-stage adhesive layer 240b.

The first substrate 210 includes a plurality of pads 212 disposed on a surface S1 thereof. The second substrate 220 is disposed above the first substrate 210 and also includes a plurality of pads 222 disposed on the surface S2 thereof. According to this embodiment, the first substrate 210 and the second substrate 220 may both be wafers. In another embodiment of the present invention, one of the first substrate 210 and the second substrate 220 is a wafer. In the present invention, the types of the first substrate 210 and the second substrate 220 are not limited. The bumps 230a and 230b are disposed between the first pad 212 and the second pad 222. In particular, the upper ends of the bumps 230a, 230b are in contact with the second pad 222 and the lower ends of the bumps 230a, 230b are in contact with the first pad 212.

In this embodiment, the bumps are the junction bumps 230a (as shown in FIG. 2A), and the junction bumps 230a may be gold junction bumps or copper junction bumps. in In another embodiment of the invention, the bumps can be plated bumps 230b (as shown in Figure 2B). The plating bump 230b can be a gold bump, a copper bump, a solder bump, or other conductive bump. Each of the bonding bumps 230a or each of the plating bumps 230b is covered by an adhesive block 240a', 240b'.

According to this embodiment, the first B-stage adhesive layer 240a includes a plurality of first B-stage adhesive blocks 240a', and the second B-stage adhesive layer 240b includes a plurality of second B-stage adhesive blocks 240b', wherein the first B-stage adhesive block 240b' The block 240a' is adhered to the surface S1 of the first substrate 210 and the second B-stage adhesive block 240b' is adhered to the surface S2 of the second substrate 210. In the present embodiment, when the second B-stage adhesive block 240a' is electrically conductive or non-conductive, the first B-stage adhesive block 240a' is electrically conductive or non-conductive. Since the first B-stage adhesive blocks 240a' are electrically insulated from each other and the second B-stage adhesive blocks 240b' are electrically insulated from each other, even the first B-stage adhesive block 240a' and the second B-stage adhesive block 240b' is electrically conductive and still prevents short circuits between the bumps 230a, 230b.

In this embodiment, the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b may be ABLESTIK's 8008 or 8008HT, and the glass transition temperature is approximately between eighty degrees Celsius and three degrees Celsius. In addition, the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b may also be SA200200, 6201, 6202C of ABLESTIK or SA-200-6, SA-200-10 provided by HITACHI Chemical CO., Ltd. The glass transition temperature is approximately between minus 40 degrees Celsius and 150 degrees Celsius. The glass transition temperature of the first B-stage adhesive layer 240a may be greater than, equal to, or less than the glass transition temperature of the second B-stage adhesive layer 240b. In addition, for example, some conductive particles (such as silver particles, copper particles, and gold particles) may be doped to the first B-stage adhesion. The layer 240a and the second B-stage adhesive layer 240b are used to increase conductivity.

3A-3D are cross-sectional views showing a wafer package structure according to another embodiment of the present invention. Please refer to FIG. 3A and FIG. 3B , except that the first B-stage adhesive layer 240 a and the second B-stage adhesive layer 240 b completely fill the gap between the bumps 230 , the chip package structure 200 ′ of the embodiment and FIG. 2A . The wafer package structure 200 of FIG. 2B is similar. In particular, the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b are both non-conductive to prevent short circuits between the bumps 230.

Referring to FIG. 3C, the chip package structure 200" of the present embodiment and the chip package structure 200' of FIG. 3A are the same as the size D1 of the first B-stage adhesive layer 240a and the size D2 of the second B-stage adhesive layer 240b. Similarly, as shown in FIG. 3C, the size D1 of the first B-stage adhesive layer 240a is smaller than the size D2 of the second B-stage adhesive layer 240b, so that the area of a portion of the first substrate 210 is not affected by the first B-stage adhesive layer 240a. Covered and exposed to the outside. The second B-stage adhesive layer 240b completely covers the surface S2 of the second substrate 220 except for the area occupied by the bumps 230, and the first B-stage adhesive layer 240a makes the first substrate 210 The surface S1 (the surrounding area) is exposed to the outside.

Referring to FIG. 3D, the chip package structure 200'' of the present embodiment is similar to the chip package structure 200" of FIG. 3C except that the first B-stage adhesive layer 240a includes a plurality of first B-stage adhesive blocks 240a'. .

4 is a cross-sectional view showing a stacked wafer package structure according to an embodiment of the present invention. Referring to FIG. 4, the stacked chip package structure 400 includes a carrier 410, a first wafer 210', a second wafer 220', a plurality of bumps 230, a first B-stage adhesive layer 240a, and a second B. Adhesive layer 240b And a plurality of bonding wires 420. The arrangement of the first wafer 210', the second wafer 220', the bump 230, the first B-stage adhesive block 240a', and the second B-stage adhesive block 240b' is substantially the same as that of Fig. 2A or 2B. In this embodiment, the first wafer 210 ′ is bonded to the carrier 410 by an adhesive layer 430 (such as epoxy resin, silver paste, die bond film (DAF), etc.) and passes through the bonding wire 420 and the carrier 410 . Electrical connection. In particular, the first wafer 210' has a wire bond pad 214 that is electrically coupled to the carrier 410 via a bond wire 420. The carrier 410 is, for example, a printed circuit board. The printed circuit board can be an FR4, FR5, BT, PI circuit board.

5 to 7 are schematic cross-sectional views showing a stacked wafer package structure according to various embodiments of the present invention. Referring to FIG. 5, the stacked chip package structure 400a includes a carrier 410, a first wafer 210', a second wafer 220', a plurality of bumps 230, a first B-stage adhesive layer 240a, and a second B. The step adhesion layer 240b and the plurality of bonding wires 420. The arrangement of the first wafer 210', the second wafer 220', the bumps 230, the first B-stage adhesive layer 240a, and the second B-stage adhesive layer 240b is substantially the same as that of FIG. 3A or FIG. 3B. The first wafer 210' is bonded to the carrier 410 by an adhesive layer 430 (such as epoxy resin, silver paste, adhesive film, etc.) and is electrically connected to the carrier 410 through the bonding wire 420. The carrier 410 is, for example, a printed circuit board. The printed circuit board can be an FR4, FR5, BT, PI circuit board. In particular, the first wafer 210' has a wire bond pad 214 that is electrically coupled to the carrier 410 via a bond wire 420. One end of the bonding wire 420 connected to the wire bonding pad 214 is covered by the first B-stage adhesive layer 240a to provide support and protection.

Please refer to FIG. 6 and FIG. 7, in the stacked type chip package structure 400b and In 400c, the first wafer 210', the second wafer 220', the bumps 230, the first B-stage adhesive layer 240a, and the second B-stage adhesive layer 240b may be arranged in the same manner as the foregoing embodiment of FIGS. 3C and 3D. Or similar. As shown in FIG. 6 and FIG. 7, the wire bonding pads 214 of the first wafer 210' are not covered by the first B-stage adhesive layer 240a or the first B-stage adhesive layer 240a' and exposed to the outside, so that the bonding wires 420 are not It will be covered by the first B-stage adhesive layer 240a or the first B-stage adhesive block 240a'.

The process of the chip package structure 200 of FIG. 2A is described below. It should be noted that the process of the chip package structure 200' of FIGS. 3A and 3B is similar to the process disclosed in FIGS. 8A through 8D. Therefore, the description of the process of the wafer package structure 200' shown in Figs. 3A and 3B is omitted.

8A-8D are cross-sectional views showing the process of the chip package structure 200 of FIG. 2A. Referring to FIG. 8A, a first substrate 210 having a plurality of first pads 212 and a second substrate 220 having a plurality of second pads 222 are provided and formed on the first pads 212 of the first substrate 210. A plurality of bumps 230. In the present embodiment, the bump 230 is a wire bump formed by a wire bonding machine and is similar to the bump 230a as shown in FIG. 2A. In another embodiment, bumps 230 are plated bumps formed by an electroplating process and are similar to bumps 230b as shown in FIG. 2B.

In this embodiment, the first substrate 210 is a carrier such as a printed circuit board, and the second substrate 220 is a wafer. The printed circuit board can be an FR4, FR5, BT, PI circuit board. In another embodiment of the present invention, the first substrate 210 and the second substrate 220 may both be wafers. In still another embodiment of the present invention, the first substrate 210 can be a wafer and the second substrate 220 can be As a carrier.

Referring to FIG. 8B and FIG. 8C, a first second-order adhesive layer X1 is formed on the first substrate 210 and B-staged (eg, pre-cured or partially cured) to form a first B-stage adhesive layer 240a. A second second-order adhesive layer X2 is formed on the second substrate 220 and cured in the B-stage to form a second B-stage adhesive layer 240b. In particular, the first second-order adhesive layer X1 and the second second-order adhesive layer X2 may be sequentially B-staged. Of course, the first second-order adhesive layer X1 and the second second-order adhesive layer X2 can be simultaneously B-staged. Since the first second-order adhesive layer X1 and the second second-order adhesive layer X2 are made of a thermosetting adhesive material having a second-order property, the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b are in the first second order. The adhesive layer X1 and the second second-order adhesive layer X2 are formed by B-stage. In the present embodiment, the heat-curable adhesive material having the second-order property may be polyacetamide, polyquinucline, benzocyclobutene or the like. In particular, the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b may be ABLESTIK's 8008 or 8008HT, and the glass transition temperature is approximately between eighty degrees Celsius and three degrees Celsius. In addition, the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b may be 6200, 6201, 6202C of ABLESTIK or SA-200-6, SA-200-10 provided by HITACHI Chemical CO., Ltd., and The glass transition temperature is approximately between minus 40 degrees Celsius and 150 degrees Celsius. The glass transition temperature of the first B-stage adhesive layer 240a is preferably higher than, equal to, or lower than the glass transition temperature of the second B-stage adhesive layer 240b. Further, for example, some conductive particles such as silver particles, copper particles, and gold particles may be doped in the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b to increase conductivity.

In addition to this, the thermosetting adhesive material having the second-order property may be electrically conductive or non-conductive, and it may be formed by screen printing, brushing, spraying, spin coating or dipping. In this step, the thermosetting adhesive material having the second-order property may be liquid or colloid to be easily spread over the first substrate 210 and the second substrate 220. The invention does not limit the type of thermosetting adhesive material.

Referring to FIG. 8D, after the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b are formed, the first substrate 210 and the second substrate 220 pass through the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b. The bonding is performed such that each of the first pads 212 is electrically connected to the corresponding second pad 222 through one of the bumps 230 . In particular, the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b are combined by re-solidification. After the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b are completely cured, a post-cure procedure is performed if necessary.

In order to ensure electrical connection between the first substrate 210 and the second substrate 220, the thickness of the first B-stage adhesive layer 240a and the thickness of the second B-stage adhesive layer 240b should be carefully controlled so that the bumps 230 can pass through. The second B-stage adhesive layer 240b is connected to the second pad 222 of the second substrate 220. In the present embodiment, the thickness of the first B-stage adhesive layer 240a is substantially equal to the thickness of the second B-stage adhesive layer 240b. However, based on actual design requirements, the thickness of the first B-stage adhesive layer 240a may also be different from the thickness of the second B-stage adhesive layer 240b.

According to the embodiment, the method for forming the first B-stage adhesive layer 240a includes forming a plurality of first second-order adhesive blocks to surround the bumps 230 and B-stage the first second-order adhesive blocks to form a plurality of first B-stage adhesives. Block 240a'. In addition, The method for forming the second B-stage adhesive layer 240b includes forming a plurality of second second-order adhesive blocks and a B-staged second second-order adhesive block on the second bonding pad 222 to form a plurality of second B-stage adhesive blocks 240b' . However, as shown in FIG. 9, the first B-stage adhesive layer 240a may be formed to completely fill the gap between the bumps 230, and the second B-stage adhesive layer 240b is completely covered except for the area occupied by the bumps 230. Surface S2 of the second substrate 210

FIG. 10 is a cross-sectional view showing a first substrate and a second substrate according to another embodiment of the present invention. In this embodiment, each of the second B-stage adhesive blocks 240b' is a hollow block having an opening A' to expose a second pad 222 of a second substrate 220, respectively. In particular, when the second B-stage adhesive block 240b' is electrically conductive or non-conductive, the first B-stage adhesive block 240a' is electrically conductive. In another embodiment, when the second B-stage adhesive block 240b' is electrically conductive or non-conductive, the first B-stage adhesive block 240a' is non-conductive.

The first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b may be formed by other methods. The present invention does not limit the pattern of the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b. The two processes are described below.

11 and 12 are schematic cross-sectional views showing a first substrate and a second substrate according to still another embodiment of the present invention. Referring to FIG. 11, in the embodiment, the second second-order adhesive layer X2 is completely formed on the second substrate 220. Further, a first second-order adhesive layer X1 having a plurality of first second-order adhesive blocks is formed to surround the bumps 230. Next, the first second-order adhesive layer X1 and the second second-order adhesive layer X2 are B-staged by heat curing or ultraviolet curing.

Referring to FIG. 12, in another embodiment of the present invention, the first second-order adhesive layer X1 completely covers the first base except for the area occupied by the bumps 230. Board 210. In addition, a second second-order adhesive layer X2 having a plurality of second second-order adhesive blocks is formed on the second pad 222 of the second substrate 220. Next, the first second-order adhesive layer X1 and the second second-order adhesive layer X2 are B-staged by heat curing or ultraviolet curing.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧ Chip package structure

110‧‧‧First substrate

110a‧‧‧ surface

112‧‧‧Contact pads

120‧‧‧Polymer bumps

130‧‧‧ wafer

130a‧‧‧Active surface

132‧‧‧ solder pads

140‧‧‧ solder

200: chip package structure

200'‧‧‧ chip package structure

200"‧‧‧ chip package structure

200'''‧‧‧ chip package structure

210‧‧‧First substrate

210’‧‧‧First wafer

212‧‧‧First pad

214‧‧‧Wire pad

220‧‧‧second substrate

220’‧‧‧second chip

222‧‧‧second solder pad

230‧‧‧Bumps

230a‧‧‧Connected bumps

230b‧‧‧Electroplated bumps

240‧‧‧Adhesive material

240a‧‧‧First B-stage adhesive layer

240a’‧‧‧First B-stage Adhesive Block

240b‧‧‧Second B-stage adhesive layer

240b’‧‧‧Second B-stage adhesive block

310‧‧‧Substrate

312‧‧‧ solder pads

320‧‧‧Bumps

320a‧‧‧Connected bumps

330‧‧‧Adhesive materials

330a‧‧‧ thermosetting adhesive block

340‧‧‧Adhesive blocks with B-order characteristics

400‧‧‧Stacked chip package structure

400b‧‧‧Stacked chip package structure

400c‧‧‧Stacked chip package structure

410‧‧‧carrier

420‧‧‧welding line

430‧‧‧Adhesive layer

A‧‧‧ surface

A’‧‧‧ Opening

B‧‧‧Surface

D1‧‧‧ size

D2‧‧‧ size

S1‧‧‧ surface

S2‧‧‧ surface

X1‧‧‧ first second-order adhesive layer

X2‧‧‧Second second adhesive layer

1 is a schematic cross-sectional view of a chip package structure having polymer bumps.

2A and 2B are schematic cross-sectional views showing a wafer package structure according to an embodiment of the present invention.

3A-3D are cross-sectional views showing a wafer package structure according to another embodiment of the present invention.

4 is a cross-sectional view showing a stacked wafer package structure according to an embodiment of the present invention.

5 to 7 are schematic cross-sectional views showing a stacked wafer package structure according to various embodiments of the present invention.

8A-8D are cross-sectional views showing the process of the chip package structure 200 of FIG. 2A.

9 and 10 illustrate a first substrate and a first embodiment of the present invention. A schematic cross-sectional view of the two substrates.

11 and 12 are schematic cross-sectional views showing a first substrate and a second substrate according to still another embodiment of the present invention.

200‧‧‧ Chip package structure

210‧‧‧First substrate

212‧‧‧First pad

220‧‧‧second substrate

222‧‧‧second solder pad

230a‧‧‧Connected bumps

240a‧‧‧First B-stage adhesive layer

240a’‧‧‧First B-stage Adhesive Block

240b‧‧‧Second B-stage adhesive layer

240b’‧‧‧Second B-stage adhesive block

S1‧‧‧ surface

S2‧‧‧ surface

Claims (21)

A chip package structure process includes: providing a first substrate having a plurality of first pads; providing a second substrate having a plurality of second pads; forming a plurality of the first pads on the first substrate a bump; forming a first second-order adhesive layer on the first substrate; B-stage the first second-order adhesive layer to form a first B-stage adhesive layer, wherein the first B-stage adhesive layer is formed The method includes: forming a plurality of first second-order adhesive blocks to surround the bumps; and B-stage the first second-order adhesive blocks to form a plurality of first B-stage adhesive blocks; forming a second substrate a second second-order adhesive layer; a B-staged second second-order adhesive layer to form a second B-stage adhesive layer; and a first B-stage adhesive layer and the second B-stage adhesive layer bonded to the first substrate and The second substrate is electrically connected to each of the first pads through one of the bumps and the corresponding second pad. The wafer package structure process of claim 1, wherein the first substrate and the second substrate are both wafers. The wafer package structure process of claim 1, wherein the first substrate is a carrier, and the second substrate is a wafer. The wafer package structure process of claim 1, wherein the first substrate is a wafer, and the second substrate is a carrier. For example, the process of wafer package structure described in claim 1 is Wherein the bump is a wire bump formed by a wire bonding machine or an electroplated bump formed by an electroplating process. The wafer package structure process of claim 1, wherein the first second-order adhesive layer is formed by screen printing, brushing, spraying, spin coating or dipping. The wafer package structure process of claim 1, wherein the second second-order adhesive layer is formed by screen printing, brushing, spraying, spin coating or dipping. The method of forming the second B-stage adhesive layer according to the method of claim 1, wherein the forming the second B-stage adhesive layer comprises: forming a plurality of second second-order adhesive blocks on the second pads; and B-staged The second second-order adhesive blocks form a plurality of second B-stage adhesive blocks. The wafer package structure process of claim 8, wherein each of the second B-stage adhesive blocks is a hollow block having an opening to expose one of the second pads, respectively. The wafer package structure process of claim 8, wherein the first B-stage adhesive blocks are electrically conductive. The wafer package structure process of claim 10, wherein the second B-stage adhesive blocks are electrically conductive. The wafer package structure process of claim 10, wherein the second B-stage adhesive blocks are non-conductive. The wafer package structure process of claim 8, wherein the first B-stage adhesive blocks are non-conductive. The wafer package structure process of claim 13, wherein the second B-stage adhesive blocks are electrically conductive. The wafer package structure process of claim 13, wherein the second B-stage adhesive blocks are non-conductive. The wafer package structure process of claim 1, wherein the second second-order adhesive layer completely covers the second substrate. The wafer package structure process of claim 1, wherein the first B-stage adhesive layer has a glass transition temperature higher than, equal to, or lower than a glass transition temperature of the second B-stage adhesive layer. The wafer package structure process of claim 1, wherein the composition of the first B-stage adhesive layer is substantially equivalent to the composition of the second B-stage adhesive layer. The wafer package structure process of claim 1, wherein the first second-order adhesive layer and the second second-order adhesive layer are sequentially B-staged to form the first B-stage adhesive layer and the second B-stage adhesive layer. The wafer package structure process of claim 1, wherein the first second-order adhesive layer and the second second-order adhesive layer are simultaneously B-staged to form the first B-stage adhesive layer and the second B-stage adhesive layer. The wafer package structure process of claim 1, wherein the method of B-staging the first second-order adhesive layer and the second second-order adhesive layer comprises heat curing or ultraviolet curing.