JP2001313467A - Wiring board - Google Patents

Wiring board

Info

Publication number
JP2001313467A
JP2001313467A JP2001043625A JP2001043625A JP2001313467A JP 2001313467 A JP2001313467 A JP 2001313467A JP 2001043625 A JP2001043625 A JP 2001043625A JP 2001043625 A JP2001043625 A JP 2001043625A JP 2001313467 A JP2001313467 A JP 2001313467A
Authority
JP
Japan
Prior art keywords
resin
wiring board
electronic component
thermal expansion
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001043625A
Other languages
Japanese (ja)
Other versions
JP4685979B2 (en
Inventor
Eiji Kodera
英司 小寺
Teruhisa Hayashi
照久 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP2001043625A priority Critical patent/JP4685979B2/en
Publication of JP2001313467A publication Critical patent/JP2001313467A/en
Application granted granted Critical
Publication of JP4685979B2 publication Critical patent/JP4685979B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which is free from cracking or breaking in resin or a wiring board body and ensures electric continuity of electronic components and inner wiring layers or the like surely and stably, in a wiring board wherein the electronic components are included in the wiring board body via the resin. SOLUTION: This wiring board is provided with an insulating wiring board body (core board) 2 having a surface 3 and a back 4, through holes 6 formed in the wiring board body 2, and chip capacitors (electronic components) 12 which are included in the through holes 6 and fixed via resin 11. Thermal expansion coefficients α1, α2, α3 of the wiring board body 2, the resin 11 and the capacitor 12 are related by a formula 1; α3<α1<=α2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、配線基板本体の内
部に電子部品を内蔵した配線基板、およびかかる配線基
板の表面上方にICチップ等の半導体素子を搭載した配
線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board having electronic components built in a wiring board main body, and a wiring board having a semiconductor element such as an IC chip mounted above the surface of the wiring board.

【0002】[0002]

【従来の技術】近年における配線基板の小型化および配
線基板内における配線の高密度化に対応するため、配線
基板の第1主面上にICチップなどの電子部品を搭載す
るだけでなく、コア基板の内部に電子部品を内蔵する配
線基板が提案されている。例えば、図5(A)に示す配
線基板50は、絶縁基板51に明けた貫通孔52にチッ
プコンデンサ53を挿入し、その両端の電極54,54
をハンダ58を介して、絶縁基板51および隣接する絶
縁層56の間に形成したランド57と接続している。貫
通孔52内に樹脂59を充填することで、上記コンデン
サ53を固着して内臓する。かかるコンデンサ53内に
は内部電極55が内設されている。
2. Description of the Related Art In order to cope with recent miniaturization of wiring boards and densification of wiring in the wiring boards, not only electronic parts such as IC chips are mounted on a first main surface of the wiring board, but also cores are mounted. 2. Description of the Related Art There has been proposed a wiring board in which electronic components are embedded inside a board. For example, in a wiring board 50 shown in FIG. 5A, a chip capacitor 53 is inserted into a through hole 52 formed in an insulating substrate 51, and electrodes 54, 54 at both ends thereof are provided.
Are connected to the lands 57 formed between the insulating substrate 51 and the adjacent insulating layer 56 via solder 58. By filling the resin 59 in the through-hole 52, the capacitor 53 is fixedly mounted. An internal electrode 55 is provided inside the capacitor 53.

【0003】また、図5(B)に示す配線基板60は、絶
縁基板61に明けた貫通孔62の一方の開口部を、予め
図示しない粘着性の仮固定膜により塞ぎ、この仮固定膜
に内部電極65を有するチップコンデンサ63を貼り付
けた状態で、貫通孔62内に樹脂69を充填し固化させ
た後、上記仮固定膜を除去したものである。上記配線基
板60は、図5(B)に示すように、上記コンデンサ63
の両端に位置する電極64,64を、予め上記絶縁基板
61とこれに隣接する絶縁層66との間に設けたランド
67,67にハンダ68を介して接続している。
In a wiring board 60 shown in FIG. 5B, one opening of a through hole 62 formed in an insulating substrate 61 is closed in advance with an adhesive temporary fixing film (not shown). In a state where the chip capacitor 63 having the internal electrode 65 is adhered, the resin 69 is filled in the through hole 62 and solidified, and then the temporary fixing film is removed. The wiring board 60 includes, as shown in FIG.
The electrodes 64, 64 located at both ends of the substrate are connected to lands 67, 67 provided in advance between the insulating substrate 61 and the insulating layer 66 adjacent thereto via solder 68.

【0004】[0004]

【発明が解決すべき課題】しかしながら、以上の配線基
板50,60では、絶縁基板51,61とその貫通孔5
2,62に充填される樹脂59,69との間、および、
樹脂59,69とこれに埋設されるコンデンサ(電子部
品)53,63との間、の少なくとも何れかにおいて、
製造過程での加熱時に熱膨張率の差により境界付近で絶
縁基板51,61や樹脂59,69に割れが生じること
がある。このため、前記ハンダ58,68が割れたり剥
離するため、電子部品53,63と配線基板50,60
内部の配線層との導通が不安定になったり断線したりす
る、という問題があった。本発明は、以上に説明した従
来の技術における問題点を解決し、配線基板本体に樹脂
を介して電子部品を内蔵する配線基板において、かかる
樹脂や配線基板本体が割れたり破損せず、上記電子部品
と内部の配線層などとの導通を確実且つ安定して取り得
る配線基板を、提供することを課題とする。
However, in the wiring boards 50 and 60 described above, the insulating boards 51 and 61 and the through holes 5 are provided.
Between the resin 59 and 69 to be filled in the second and the second 62, and
In at least one of between the resins 59 and 69 and the capacitors (electronic parts) 53 and 63 embedded therein,
During the heating in the manufacturing process, cracks may occur in the insulating substrates 51 and 61 and the resins 59 and 69 near the boundary due to the difference in the coefficient of thermal expansion. For this reason, since the solders 58 and 68 are broken or separated, the electronic components 53 and 63 and the wiring boards 50 and 60 are separated.
There has been a problem that the conduction with the internal wiring layer becomes unstable or breaks. The present invention solves the problems in the conventional technology described above, and in a wiring board in which electronic components are embedded in a wiring board body via a resin, the resin or the wiring board body is not broken or broken, It is an object of the present invention to provide a wiring board capable of reliably and stably providing conduction between a component and an internal wiring layer.

【0005】[0005]

【課題を解決するための手段】本発明は、上記課題を解
決するため、配線基板本体、樹脂、および埋設される電
子部品などの熱膨張率の関係に着目することにより、成
されたものである。即ち、本発明の第1の配線基板(請
求項1)は、表・裏面を有する絶縁性の配線基板本体
と、この配線基板本体に設けた貫通孔または凹部と、か
かる貫通孔または凹部内に内蔵され且つ樹脂を介して固
着される電子部品と、を含むと共に、上記配線基板本
体、樹脂、および電子部品の熱膨張率α1,α2,α3
(即ち、配線基板本体の熱膨張率:α1、樹脂の熱膨張
率:α2、電子部品の熱膨張率:α3とする)が数式4
の関係にある、ことを特徴とする。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention has been made by focusing on the relationship between the thermal expansion coefficients of a wiring board main body, a resin, and embedded electronic components. is there. That is, the first wiring board of the present invention (Claim 1) includes an insulating wiring board body having front and back surfaces, a through hole or a recess provided in the wiring board body, and An electronic component that is built-in and fixed through a resin, and has a coefficient of thermal expansion α1, α2, α3 of the wiring board body, the resin, and the electronic component.
(That is, the thermal expansion coefficient of the wiring board body is α1, the thermal expansion coefficient of the resin is α2, and the thermal expansion coefficient of the electronic component is α3).
Is characterized by the following relationship.

【0006】[0006]

【数4】α3<α1≦α2## EQU4 ## α3 <α1 ≦ α2

【0007】これによれば、配線基板本体の熱膨張率α
1は、電子部品の熱膨張率α3よりも大きく、且つ上記
電子部品が埋設される樹脂の熱膨張率α2と等しいかま
たはそれより小さい関係にある。このため、溶けた上記
樹脂を固化させる際や別途の位置での加熱に際し、上記
電子部品が膨張しても、配線基板本体や樹脂は更に大き
く膨張する。この結果、かかる配線基板本体の貫通孔ま
たは凹部、あるいは上記電子部品を包囲する樹脂自体が
大きくなる。従って、樹脂や配線基板本体が割れたり破
損する事態を防止できるので、電子部品と内部の配線層
との間における導通を安定して確実に取ることが可能と
なる。尚、本明細書において、熱膨張率とは、対象物の
縦・横(X−Y、配線基板の厚み方向に対する直角方向)
方向における熱膨張率を言う。
According to this, the thermal expansion coefficient α of the wiring board body is
1 is larger than the coefficient of thermal expansion α3 of the electronic component and is equal to or smaller than the coefficient of thermal expansion α2 of the resin in which the electronic component is embedded. Therefore, even when the electronic component expands when the melted resin is solidified or heated at a separate position, the wiring board body and the resin further expand significantly. As a result, the size of the through hole or the concave portion of the wiring board main body or the resin itself surrounding the electronic component increases. Accordingly, it is possible to prevent the resin or the wiring board body from being broken or damaged, so that it is possible to stably and reliably establish conduction between the electronic component and the internal wiring layer. In this specification, the coefficient of thermal expansion refers to the vertical and horizontal directions of the object (X-Y, a direction perpendicular to the thickness direction of the wiring board).
The coefficient of thermal expansion in the direction.

【0008】本発明の第2の配線基板(請求項2)は、表
・裏面を有する絶縁性の配線基板本体と、この配線基板
本体に設けた貫通孔または凹部と、かかる貫通孔または
凹部内に内蔵され且つ樹脂を介して固着される電子部品
と、上記配線基板本体の表面上方に搭載され且つ上記電
子部品と導通される半導体素子と、を含むと共に、上記
配線基板本体、樹脂、電子部品、および、半導体素子の
熱膨張率α1,α2,α3,α4(即ち、配線基板本体
の熱膨張率:α1、樹脂の熱膨張率:α2、電子部品の
熱膨張率:α3、半導体素子の熱膨張率:α4とする)
が数式5の関係にある、ことを特徴とする。
A second wiring board according to the present invention comprises an insulating wiring board main body having front and rear surfaces, a through hole or a recess provided in the wiring board main body, and an inside of the through hole or the recess. An electronic component built in and fixed through a resin, and a semiconductor element mounted above the surface of the wiring board main body and electrically connected to the electronic component, and the wiring board main body, the resin, and the electronic component And the thermal expansion coefficients α1, α2, α3, α4 of the semiconductor element (that is, the thermal expansion coefficient of the wiring board body: α1, the thermal expansion coefficient of the resin: α2, the thermal expansion coefficient of the electronic component: α3, the heat of the semiconductor element) Expansion coefficient: α4)
Is in the relationship of Expression 5.

【0009】[0009]

【数5】α4≦α3<α1≦α2[Equation 5] α4 ≦ α3 <α1 ≦ α2

【0010】これによれば、前記数式4の関係に加え、
半導体素子の熱膨張率α4は内蔵される電子部品の熱膨
張率α3と同じかそれ以下の関係にある。このため、例
えば配線基板の第1主面上に半導体素子を搭載する際の
ハンダ付け時において、半導体素子が熱膨しても電子部
品と同じかそれ以下となり、配線基板本体や電子部品を
埋設する樹脂に影響しなくなる。従って、第1主面上な
どに搭載した半導体素子と電子部品とを直にまたは内部
の配線層を介して確実且つ安定して導通できると共に、
かかる配線基板を効率良く製造することも可能となる。
[0010] According to this, in addition to the relationship of the above equation 4,
The coefficient of thermal expansion α4 of the semiconductor element is equal to or less than the coefficient of thermal expansion α3 of the built-in electronic component. For this reason, for example, when soldering when mounting the semiconductor element on the first main surface of the wiring board, even if the semiconductor element thermally expands, it becomes equal to or less than the electronic component, and the wiring board body and the electronic component are embedded. It does not affect the resin that is used. Therefore, the semiconductor element and the electronic component mounted on the first main surface or the like can be reliably and stably conducted directly or via the internal wiring layer, and
It is also possible to efficiently manufacture such a wiring board.

【0011】本発明の第3の配線基板(請求項3)は、表
・裏面を有する絶縁性の配線基板本体と、この配線基板
本体に設けた貫通孔または凹部と、かかる貫通孔または
凹部内に内蔵され且つ樹脂を介して固着される電子部品
と、上記配線基板本体の表面および裏面の少なくとも一
方の上に形成される絶縁層と、を含むと共に、上記配線
基板本体、樹脂、電子部品、および、絶縁層の熱膨張率
α1,α2,α3,α5(即ち、配線基板本体の熱膨張
率:α1、樹脂の熱膨張率:α2、電子部品の熱膨張
率:α3、絶縁層の熱膨張率:α5とする)が数式6の
関係にある、ことを特徴とする。
According to a third aspect of the present invention, there is provided an insulating wiring board body having front and rear surfaces, a through hole or a recess provided in the wiring board body, and a through hole or a recess formed in the through hole or the recess. An electronic component embedded in and fixed through a resin, and an insulating layer formed on at least one of the front surface and the back surface of the wiring substrate main body, and the wiring substrate main body, the resin, the electronic component, And the thermal expansion coefficients α1, α2, α3, α5 of the insulating layer (that is, the thermal expansion coefficient of the wiring board body: α1, the thermal expansion coefficient of the resin: α2, the thermal expansion coefficient of the electronic component: α3, the thermal expansion of the insulating layer) Ratio: α5) in the relationship of Expression 6.

【0012】[0012]

【数6】α3<α1≦α2≦α5[Equation 6] α3 <α1 ≦ α2 ≦ α5

【0013】これによれば、前記数式4の関係に加え、
絶縁層の熱膨張率α5は、樹脂の熱膨張率α2と同じか
それ以上の関係となる。このため、かかる樹脂を固化さ
せる際や別途の位置での加熱に際し、上記電子部品、配
線基板本体、および樹脂が膨張しても、絶縁層はこれら
よりも更に大きく膨張するので、かかる樹脂などの膨張
を吸収することができる。従って、樹脂や配線基板本体
が割れたり破損する事態を防止できるので、電子部品と
上記絶縁層間の配線層との間における導通を安定して確
実に取ることが可能となる。
According to this, in addition to the relation of the above-mentioned formula 4,
The coefficient of thermal expansion α5 of the insulating layer has the same or higher relationship as the coefficient of thermal expansion α2 of the resin. For this reason, when the resin is solidified or heated at a separate position, even if the electronic component, the wiring board body, and the resin expand, the insulating layer expands more than these, so that the resin or the like Can absorb swelling. Accordingly, it is possible to prevent the resin or the wiring board main body from being broken or damaged, so that it is possible to stably and reliably establish electrical conduction between the electronic component and the wiring layer between the insulating layers.

【0014】更に、前記樹脂の熱膨張率α2が、40p
pm/℃よりも小さい、配線基板も本発明に含まれる。
これによれば、前記樹脂や配線基板本体が割れたり破損
する事態を防止したり、半導体素子の膨張による配線基
板本体などへの影響を一層確実に防ぐことが可能とな
る。尚、上記熱膨張率α2は、35ppm/℃以下(望
ましくは30ppm/℃以下、より望ましくは25pp
m/℃以下、更に望ましくは20ppm/℃以下、但し
下限値は10ppm/℃以上)が一層望ましい。尚、上
記何れかの配線基板本体には、内部配線を有する絶縁基
板や、複数の絶縁板と配線とを積層した基板などの多層
基板も含まれる。且つ、これらの配線基板本体は、ガラ
スクロスやガラスフィラ入りの配線基板本体としても良
い。
Further, the coefficient of thermal expansion α2 of the resin is 40 p
A wiring board having a lower than pm / ° C. is also included in the present invention.
According to this, it is possible to prevent the resin or the wiring board main body from being cracked or damaged, and to more reliably prevent the expansion of the semiconductor element from affecting the wiring board main body. The coefficient of thermal expansion α2 is 35 ppm / ° C. or less (preferably 30 ppm / ° C. or less, more preferably 25 pp / ° C. or less).
m / ° C. or lower, more preferably 20 ppm / ° C. or lower, provided that the lower limit is 10 ppm / ° C. or higher). It should be noted that any of the above-mentioned wiring board bodies includes an insulating substrate having internal wiring and a multilayer substrate such as a substrate in which a plurality of insulating plates and wiring are laminated. Further, these wiring board bodies may be wiring board bodies containing glass cloth or glass filler.

【0015】[0015]

【発明の実施の形態】以下において本発明の実施に好適
な形態を図面と共に説明する。図1は、本発明による1
形態の配線基板1における主要部の断面を示す。配線基
板1は、配線基板本体(以下コア基板という)2と、その
表・裏面3,4上に複数の絶縁層22,23,28,2
9,34,35と、配線層20,21,26,27,3
2,33とを有する。コア基板2の表面3の上方の配線
層20,26,32および絶縁層22,28,34は、
ビルドアップ層BU1を構成し、裏面4の下方の配線層
21,27,33および絶縁層23,29,35は、ビ
ルドアップ層BU2を構成する。上記コア基板2は、ガ
ラスクロス−エポキシ樹脂の複合材からなり平面視で矩
形を呈する絶縁性の板材で、ほぼ中央に平面視がほぼ正
方形で表・裏面3,4間を貫通する貫通孔6を有する。
かかる貫通孔6内には、箱形状の電子部品ユニット10
がエポキシ樹脂を主成分とする樹脂11を介して固着さ
れ埋設・内蔵されている。尚、本実施形態では、上記樹
脂11には、熱膨張率α2が32ppm/℃の樹脂を用
いられている。
Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows one embodiment of the present invention.
2 shows a cross section of a main part in a wiring board 1 of the embodiment. The wiring board 1 includes a wiring board body (hereinafter, referred to as a core board) 2 and a plurality of insulating layers 22, 23, 28,
9, 34, 35 and wiring layers 20, 21, 26, 27, 3
2, 33. The wiring layers 20, 26, 32 and the insulating layers 22, 28, 34 above the surface 3 of the core substrate 2
The build-up layer BU1 is formed, and the wiring layers 21, 27, 33 and the insulating layers 23, 29, 35 below the back surface 4 form the build-up layer BU2. The core substrate 2 is made of a glass cloth-epoxy resin composite material, and is an insulating plate material having a rectangular shape in plan view. Having.
In the through hole 6, a box-shaped electronic component unit 10 is provided.
Are fixed and embedded via a resin 11 containing an epoxy resin as a main component. In this embodiment, a resin having a thermal expansion coefficient α2 of 32 ppm / ° C. is used as the resin 11.

【0016】上記電子部品ユニット10は、図2に示す
ように、同じ形状の8個のチップコンデンサ(電子部品)
12をエポキシ樹脂からなるモールド樹脂18により予
め一体に固着したものである。尚、かかるモールド樹脂
18には、樹脂11と同じ熱膨張率α2の32ppm/
℃の樹脂を用いる。各チップコンデンサ12の上面に
は、図2で前後方向にCuからなる一対ずつの電極14
が形成され、各チップコンデンサ12の底面にも図示し
ない電極16が同じ位置に形成されている。これら電極
14,16の上端は、上記モールド樹脂18の表・裏面
から約数10μm程度突出している。各コンデンサ12
には、例えばチタン酸バリウムを主成分とする誘電体層
とNiを主成分とする電極層とを交互に積層したセラミ
ックコンデンサが用いられる。
As shown in FIG. 2, the electronic component unit 10 includes eight chip capacitors (electronic components) having the same shape.
12 is integrally fixed in advance by a mold resin 18 made of an epoxy resin. The mold resin 18 has the same thermal expansion coefficient α2 as that of the resin 11 at 32 ppm /
Use a resin at ° C. On the upper surface of each chip capacitor 12, a pair of electrodes
Are formed on the bottom surface of each chip capacitor 12 at the same position. The upper ends of the electrodes 14 and 16 protrude from the front and back surfaces of the mold resin 18 by about several tens μm. Each capacitor 12
For example, a ceramic capacitor in which a dielectric layer mainly containing barium titanate and an electrode layer mainly containing Ni are alternately laminated is used.

【0017】図1に示すように、コア基板2の貫通孔6
の左右には、スルーホール7が穿孔され、それらの内部
に円筒状のスルーホール導体8および充填樹脂9が形成
されている。コア基板2の表・裏面3,4および樹脂1
1の表・裏面上には、公知のビルドアップ工程(サブト
ラクティブ法、フルアディティブ法、セミアディティブ
法等)により、所定パターンを有する銅製の配線層2
0,21がCuメッキにより形成されている。配線層2
0,21は、前記電子部品12の各電極14,16の上・
下端と接続されている。また、配線層20,21上に
は、エポキシ樹脂を主成分とし且つシリカなどの無機フ
ィラを含む絶縁層22,23とその上の配線層26,2
7が形成され、且つ上下の配線層20,26間や、配線
層21,27間を接続するフィルドビア導体24,25
が、銅メッキにより絶縁層22,23を貫通して形成さ
れている。尚、上記ビア導体24などが形成される前の
ビアホールの形成は、フォトリソグラフィ技術、または
レーザ(YAG、CO、エキシマなど)照射により行われ
る。また、前記各コンデンサ12の電極14,16は、そ
の真上で左右方向に連続する転換層を兼ねる配線層2
6,27を介して互いに接続される。このため、8個のコ
ンデンサ12は、並列に接続され静電容量の大きな合成
コンデンサを形成する。
As shown in FIG. 1, through holes 6 in core substrate 2 are provided.
Through holes 7 are drilled on the left and right sides of the hole, and a cylindrical through-hole conductor 8 and a filling resin 9 are formed therein. Front and back surfaces 3 and 4 of core substrate 2 and resin 1
The copper wiring layer 2 having a predetermined pattern is formed on the front and back surfaces of the substrate 1 by a known build-up process (subtractive method, fully additive method, semi-additive method, etc.).
0 and 21 are formed by Cu plating. Wiring layer 2
0 and 21 are above the electrodes 14 and 16 of the electronic component 12.
It is connected to the lower end. On the wiring layers 20 and 21, insulating layers 22 and 23 containing epoxy resin as a main component and containing an inorganic filler such as silica and wiring layers 26 and 2 thereover are provided.
7 are formed, and filled via conductors 24 and 25 connecting between the upper and lower wiring layers 20 and 26 and between the wiring layers 21 and 27 are formed.
Are formed through the insulating layers 22 and 23 by copper plating. The formation of the via hole before the formation of the via conductor 24 and the like is performed by a photolithography technique or laser (YAG, CO 2 , excimer, etc.) irradiation. Further, the electrodes 14 and 16 of each of the capacitors 12 are connected to the wiring layer 2 which also serves as a conversion layer that is continuous in the left-right direction immediately above.
6, 27 are connected to each other. Therefore, the eight capacitors 12 are connected in parallel to form a combined capacitor having a large capacitance.

【0018】同様にして、配線層26,27上には、絶
縁層28,29と配線層32,33およびフィルドビア
導体30,31が形成される。更に、絶縁層28および
配線層32の上に形成したソルダーレジスト層(絶縁層)
34には、配線層32上に位置し且つ上端が第1主面3
4aよりも高く突出するハンダ製のフリップチップバン
プ36が、複数個貫通する。各バンプ36には、第1主
面34a上に搭載されるICチップ(半導体素子)38の
底面における接続端子39が個別に接続され、且つこれ
らの周囲にエポキシ樹脂を主成分するアンダーフィル材
39aが厚さ約60μmにして充填される。一方、絶縁
層29および配線層33の下にはソルダーレジスト(絶
縁層)層35が形成され、第2主面35aに向けて開口
した複数の開口部35b内には、上記配線層33内の配
線37が露出し、その表面に薄いNiおよびAuメッキ
を被覆され、図示しないマザーボードなどと接続するた
めの接続端子を形成している。かかる接続端子となる配
線37には、ピン(コバール、Fe−42wt%Ni合
金、銅など)がハンダ付けされていても良い。
Similarly, on the wiring layers 26 and 27, insulating layers 28 and 29, wiring layers 32 and 33, and filled via conductors 30 and 31 are formed. Furthermore, a solder resist layer (insulating layer) formed on the insulating layer 28 and the wiring layer 32
Reference numeral 34 denotes a first main surface 3 located on the wiring layer 32 and having an upper end.
A plurality of flip chip bumps 36 made of solder projecting higher than 4a penetrate. Connection terminals 39 on the bottom surface of an IC chip (semiconductor element) 38 mounted on the first main surface 34a are individually connected to each bump 36, and an underfill material 39a mainly composed of epoxy resin is Is filled to a thickness of about 60 μm. On the other hand, a solder resist (insulating layer) layer 35 is formed below the insulating layer 29 and the wiring layer 33, and a plurality of openings 35 b opened toward the second main surface 35 a are provided in the wiring layer 33. The wiring 37 is exposed, its surface is coated with thin Ni and Au plating, and a connection terminal for connecting to a motherboard (not shown) is formed. A pin (Kovar, Fe-42 wt% Ni alloy, copper, etc.) may be soldered to the wiring 37 serving as such a connection terminal.

【0019】ここで、上記配線基板1の製造方法の主要
な工程を図3により説明する。図3(A)は、平面視が正
方形で一辺が31mm、厚さ0.8mmのガラスクロス
入りのコア基板2の所定位置(中央)に穿孔した一辺が1
2mmの正方形を呈する貫通孔6内に、一辺が9mmの
正方形で厚さが0.75mmの電子部品ユニット10を
挿入する状態を示す。貫通孔6における裏面4側の開口
部は、図3(A)に示すように、粘着面5aを上向きにし
たテープ5により、予め閉塞されている。貫通孔6内に
挿入された電子部品ユニット10は、その裏面側に突出
する各チップコンデンサ12の複数の電極16がテープ
5の粘着面5aに接着することにより、位置決めされ
る。
Here, main steps of the method of manufacturing the wiring board 1 will be described with reference to FIG. FIG. 3 (A) is a plan view of a core substrate 2 containing a glass cloth having a square shape, a side of 31 mm and a thickness of 0.8 mm in a plan view.
A state in which the electronic component unit 10 having a square of 9 mm on a side and a thickness of 0.75 mm is inserted into the through-hole 6 having a square of 2 mm is shown. As shown in FIG. 3A, the opening of the through hole 6 on the back surface 4 side is previously closed by the tape 5 with the adhesive surface 5a facing upward. The electronic component unit 10 inserted into the through hole 6 is positioned by bonding a plurality of electrodes 16 of each chip capacitor 12 projecting to the back surface side to the adhesive surface 5 a of the tape 5.

【0020】上記ユニット10が位置決めされた状態
で、貫通孔6内に表面3側からエポキシ樹脂を主成分と
する溶けた樹脂11を注入した後、キュア処理を施して
固化する。この結果、図3(B)に示すように、電子部品
ユニット10は貫通孔6内で固化した樹脂11に固着し
且つ内蔵される。上記電子部品ユニット10のモールド
樹脂18は、キュア処理後に樹脂11と一体化して、電
子部品12,12を固着し且つ内臓する樹脂11となる
(即ち、モールド樹脂18と樹脂11とは、同一の熱膨
張率を有するため、実質的に同一物となる)。更に、テ
ープ5を剥離するとこれに倣った樹脂11の平坦な裏面
11bには、前記各電極16の下端面が露出する。次い
で、図3(B)に示す樹脂11の盛り上がった表面11a
を、例えばバフ研磨により平坦に整面する。この結果、
図3(C)に示すように、樹脂11の新たな表面11cに
は、前記複数の電極14の上端面が露出する。
In a state where the unit 10 is positioned, a melted resin 11 containing an epoxy resin as a main component is injected into the through hole 6 from the front surface 3 side, and then cured and solidified. As a result, as shown in FIG. 3B, the electronic component unit 10 is fixed to the resin 11 solidified in the through hole 6 and is built therein. The mold resin 18 of the electronic component unit 10 is integrated with the resin 11 after the curing process, and becomes the resin 11 that fixes and incorporates the electronic components 12 and 12.
(That is, since the mold resin 18 and the resin 11 have the same coefficient of thermal expansion, they are substantially the same.) Further, when the tape 5 is peeled off, the lower end surfaces of the electrodes 16 are exposed on the flat back surface 11b of the resin 11 following the tape 5. Next, the raised surface 11a of the resin 11 shown in FIG.
Is flattened by, for example, buffing. As a result,
As shown in FIG. 3C, the upper end surfaces of the plurality of electrodes 14 are exposed on a new surface 11c of the resin 11.

【0021】これ以降は、前述した方法によって絶縁層
22,23などおよび配線層20,21,26,27な
どからなるビルドアップ層BU1,BU2、ビア導体2
4,25など、および前記バンプ36や接続端子用の配
線37が形成される。尚、樹脂11の裏面11bも上記
と同様に整面すると、一層望ましくなる。また、上記製
造方法では、複数の電子部品12を予め一体化した前記
ユニット10を用いたが、各電子部品12毎にチップマ
ウンタなどを用いて貫通孔6内に個別に内蔵した後、樹
脂11を充填してキュア処理を行うこともできる。とこ
ろで、コア基板2、樹脂11、および電子部品たるチップ
コンデンサ12の各熱膨張率α1,α2,α3は、数式7
の関係になるように予め設定されている。
Thereafter, the build-up layers BU1, BU2 composed of the insulating layers 22, 23, etc. and the wiring layers 20, 21, 26, 27, etc., and the via conductors 2 are formed by the above-described method.
4, 25, etc., and the bumps 36 and wirings 37 for connection terminals are formed. It is more desirable that the rear surface 11b of the resin 11 be leveled in the same manner as described above. In the above-described manufacturing method, the unit 10 in which a plurality of electronic components 12 are integrated in advance is used. However, after each electronic component 12 is individually embedded in the through hole 6 using a chip mounter or the like, the resin 11 And curing treatment can be performed. By the way, the thermal expansion coefficients α1, α2, α3 of the core substrate 2, the resin 11, and the chip capacitor 12, which is an electronic component, are given by the following equations.
Are set in advance so that

【0022】[0022]

【数7】α3<α1≦α2Equation 3 α3 <α1 ≦ α2

【0023】本実施形態では、α1:15ppm/℃、
α2:32ppm/℃、α3:10ppm/℃とした。
これにより、前記樹脂11のキュア処理時の加熱や第1
主面34a上にICチップ38を搭載する際の前記バン
プ36の加熱時において、各コンデンサ12が膨張して
もコア基板2や樹脂11は更に大きく膨張し、コア基板
2の貫通孔6および各コンデンサ12を包囲する樹脂1
1自体が大きくなる。従って、樹脂11やコア基板2が
割れたり破損する事態を防止できるので、各コンデンサ
12と内部の配線層20,21などとの間における導通
を安定した状態で確実に取ることが可能となる。尚、前
記電子部品ユニット10に用いるモールド樹脂18の熱
膨張率は、樹脂11の熱膨張率α2とほぼ同じ値であ
る。また、数式7に更にICチップ(半導体素子)38の
熱膨張率α4を加えると、数式8の関係になる。
In the present embodiment, α1: 15 ppm / ° C.,
α2: 32 ppm / ° C., α3: 10 ppm / ° C.
Thereby, the heating during the curing process of the resin 11 and the first
When the bumps 36 are heated when the IC chip 38 is mounted on the main surface 34a, even if each capacitor 12 expands, the core substrate 2 and the resin 11 further expand more, and the through-hole 6 of the core substrate 2 Resin 1 surrounding capacitor 12
1 itself becomes large. Accordingly, it is possible to prevent the resin 11 and the core substrate 2 from being broken or damaged, so that it is possible to reliably ensure the conduction between the capacitors 12 and the internal wiring layers 20 and 21 in a stable state. The coefficient of thermal expansion of the mold resin 18 used in the electronic component unit 10 is substantially the same as the coefficient of thermal expansion α2 of the resin 11. Further, when the coefficient of thermal expansion α4 of the IC chip (semiconductor element) 38 is further added to Expression 7, the relationship of Expression 8 is obtained.

【0024】[0024]

【数8】α4≦α3<α1≦α2[Equation 8] α4 ≦ α3 <α1 ≦ α2

【0025】本実施形態では、α4:4ppm/℃とし
た。このため、例えば第1主面34a上にICチップ3
8を搭載する際の前記バンプ36の加熱時にて、ICチ
ップ38が熱膨してもその熱膨張率α4は各コンデンサ
(電子部品)12と同じかそれ以下であるため、コア基板
2やコンデンサ12を埋設する樹脂11に影響しなくな
る。従って、搭載したICチップ38と各コンデンサ1
2とを、配線層20などを介して確実且つ安定して導通
させることができる。更に、数式7に対し、ビルドアッ
プ層BU1,BU2を形成する絶縁層22,23,2
8,29などの熱膨張率α5を加えると、数式9の関係
になる。
In the present embodiment, α4: 4 ppm / ° C. Therefore, for example, the IC chip 3 is placed on the first main surface 34a.
When the IC chip 38 is thermally expanded during the heating of the bumps 36 when mounting the IC chip 8, the coefficient of thermal expansion α4 of each
Since it is equal to or less than (electronic component) 12, it does not affect the core substrate 2 or the resin 11 in which the capacitor 12 is embedded. Therefore, the mounted IC chip 38 and each capacitor 1
2 can be reliably and stably conducted through the wiring layer 20 or the like. Further, with respect to Equation 7, the insulating layers 22, 23, 2 forming the buildup layers BU1, BU2
When the coefficient of thermal expansion α5 such as 8, 29 is added, the relationship of Expression 9 is obtained.

【0026】[0026]

【数9】α3<α1≦α2≦α5## EQU9 ## α3 <α1 ≦ α2 ≦ α5

【0027】本実施形態では、α5:60ppm/℃と
した。このため、前記数式7の関係に加え、絶縁層2
2,23などの熱膨張率α5は、樹脂の熱膨張率α2と
同じかそれ以上の関係となる。この結果、樹脂11を固
化させる際や別途の位置での加熱に際し、上記各コンデ
ンサ(電子部品)12、配線基板本体2、および樹脂11
が膨張しても、絶縁層22,23などはこれらよりも更
に大きく膨張するので、樹脂11などの膨張を吸収でき
る。従って、樹脂11や配線基板本体2が割れたり破損
する事態を防止できるため、各コンデンサ12と絶縁層
22,23,28,29間などの配線層26,27など
との間における導通を安定して確実に取ることが可能と
なる。
In this embodiment, α5 is set to 60 ppm / ° C. Therefore, in addition to the relationship of the above equation 7, the insulating layer 2
The coefficient of thermal expansion α5, such as 2, 23, has a relationship equal to or greater than the coefficient of thermal expansion α2 of the resin. As a result, when the resin 11 is solidified or heated at a separate position, each of the capacitors (electronic components) 12, the wiring board body 2, and the resin 11
When the insulating layer 22 and 23 expand, the expansion of the resin 11 and the like can be absorbed. Therefore, since the resin 11 and the wiring board main body 2 can be prevented from being broken or broken, conduction between each capacitor 12 and the wiring layers 26, 27 between the insulating layers 22, 23, 28, 29 and the like is stabilized. Can be taken reliably.

【0028】以上のような配線基板1によれば、コア基
板(配線基板本体)2の貫通孔6に、樹脂11を介して内
臓される電子部品ユニット10中の各チップコンデンサ
12における電極14,16と配線層20,21との接
続部分も断線しにくくなり、その導通が安定する。尚、
各コンデンサ12の電極14,16およびこれらに接続
する配線層20,21は、上記Cu同士のような同じ材
料で且つハンダよりも高融点の材料が望ましい。これに
よりICチップ38を搭載する際のハンダ製の前記バン
プ36の加熱時にも断線を防止できる。
According to the wiring board 1 as described above, the electrodes 14 and the electrodes 14 of the respective chip capacitors 12 in the electronic component unit 10 built in the through holes 6 of the core board (wiring board main body) 2 via the resin 11. The connection between the wiring layer 16 and the wiring layers 20 and 21 is hardly broken, and the conduction is stabilized. still,
The electrodes 14 and 16 of each capacitor 12 and the wiring layers 20 and 21 connected thereto are preferably made of the same material such as the above-mentioned Cu and having a higher melting point than solder. Thus, disconnection can be prevented even when the solder bumps 36 are heated when the IC chip 38 is mounted.

【0029】このため、各コンデンサ12と第1主面3
4a上に搭載したICチップ38との間も比較的短い配
線で安定した導通を得ることができる。また、各コンデ
ンサ12の電極16と第2主面35側の配線(接続端子)
37との間も比較的短い配線で安定した導通が得られ、
且つ配線基板1自体を搭載するマザーボードなどとの導
通も確実となる。従って、小型化し且つ配線が高密度す
る配線基板1において、そのコア基板2に内蔵する電子
部品たるコンデンサ12を安定して活用することがで
き、且つそれらの耐久性に優れたものとすることができ
る。尚、配線層20,21は、各コンデンサ12とは別
にスルーホール導体8を介して互いに導通される。ま
た、ビア導体24,25,30,31は、前記図1で示した
フィルドビアとし且つ厚さ方向に直線状に積み上がるス
タックドビアにすることが望ましい。これにより、各コ
ンデンサ12と第1主面34a上に搭載するICチップ
38との間を最短距離で接続できるため、電気的特性が
向上すると共に、各コンデンサ12とマザーボードとの
間も短い距離で接続することができる。
For this reason, each capacitor 12 and the first main surface 3
Stable continuity can also be obtained with relatively short wiring between the IC chip 38 mounted on 4a. Also, the wiring (connection terminal) on the electrode 16 of each capacitor 12 and the second main surface 35 side.
Stable conduction can be obtained with relatively short wiring between
In addition, continuity with the motherboard on which the wiring board 1 itself is mounted is also ensured. Accordingly, in the wiring board 1 having a small size and high wiring density, it is possible to stably utilize the capacitors 12 as the electronic components incorporated in the core board 2 and to make them excellent in durability. it can. The wiring layers 20 and 21 are electrically connected to each other via the through-hole conductor 8 separately from the capacitors 12. The via conductors 24, 25, 30, 31 are preferably the filled vias shown in FIG. 1 and stacked vias which are linearly stacked in the thickness direction. Thereby, each capacitor 12 and the IC chip 38 mounted on the first main surface 34a can be connected with the shortest distance, so that the electrical characteristics are improved and the distance between each capacitor 12 and the motherboard is also short. Can be connected.

【0030】[0030]

【実施例】ここで本発明の配線基板の具体的な実施例を
比較例と共に説明する。前記と同じサイズのコア基板2
を複数個用意し、それらの貫通孔6内に前記電子部品ユ
ニット10を、熱膨張率α2が互いに異なる樹脂11を
用い同じ条件にて、前記図3(C)に示すように固着して
内蔵した。これらのうち、樹脂11の熱膨張率α2が1
5ppm/℃、32ppm/℃のものを実施例1,2と
し、熱膨張率α2が45ppm/℃のものを比較例1と
した。実施例1,2および比較例1の一部を、前記図1
のような配線基板1に形成すると共に、その第1主面3
4a上に熱膨張率が30ppm/℃以下のアンダーフィ
ル材39aを介して、熱膨張率α4が4ppm/℃のI
Cチップ38を搭載した。このうち実施例1,2の前記
コア基板2などを用いたものを実施例3,4、比較例1
のコア基板2などを用いたものを比較例2とした。尚、
実施例1,2および比較例1は前記数式7を、実施例
3,4および比較例2は前記数式8をそれぞれ満たして
いる。各例について3個ずつ用意したものに対して、+
125℃と−55℃との間を1000回(サイクル)ずつ
加熱・冷却する信頼性(熱衝撃)テストを行った。かかる
テストにおいて、各例の樹脂11に割れが生じたか否か
を、1000回終了後においてそれぞれ観察した。それ
らの結果を表1に示す。
Now, specific examples of the wiring board of the present invention will be described together with comparative examples. Core substrate 2 of the same size as above
And a plurality of electronic component units 10 are fixed in the through holes 6 by using resins 11 having different thermal expansion coefficients α2 under the same conditions as shown in FIG. did. Among them, the coefficient of thermal expansion α2 of the resin 11 is 1
Those having 5 ppm / ° C and 32 ppm / ° C were referred to as Examples 1 and 2, and those having a thermal expansion coefficient α2 of 45 ppm / ° C were referred to as Comparative Example 1. Examples 1 and 2 and a part of Comparative Example 1 are shown in FIG.
And the first main surface 3
4a through an underfill material 39a having a coefficient of thermal expansion of 30 ppm / ° C. or less, the I having a coefficient of thermal expansion α4 of 4 ppm / ° C.
The C chip 38 was mounted. Of these, those using the core substrate 2 of Examples 1 and 2 were used in Examples 3 and 4 and Comparative Example 1
A substrate using the core substrate 2 of Comparative Example 2 was used as Comparative Example 2. still,
Examples 1 and 2 and Comparative Example 1 satisfy Expression 7, and Examples 3, 4 and Comparative Example 2 satisfy Expression 8. For each of the three prepared for each example, +
A reliability (thermal shock) test of heating and cooling between 125 ° C. and −55 ° C. 1000 times (cycles) was performed. In this test, whether or not cracks occurred in the resin 11 of each example was observed after completion of 1,000 times. Table 1 shows the results.

【0031】[0031]

【表1】 [Table 1]

【0032】表1の結果によれば、実施例1〜4では、
何れも樹脂11に割れが生じていなかったのに対し、比
較例1,2では、3個全てが樹脂11に割れが生じてい
た。かかる結果から、コア基板2、樹脂11、チップコ
ンデンサ12、およびICチップ38の熱膨張率α1,
α2,α3,α4が前記数式7,8を満たすと共に、樹
脂11の熱膨張率α2を40ppm/℃以下、好ましく
は35ppm/℃以下にすることが肝要であることが理
解される。これにより、本発明の配線基板の効果が裏付
けられたことも容易に理解されよう。
According to the results shown in Table 1, in Examples 1 to 4,
In all cases, cracks did not occur in the resin 11, whereas in Comparative Examples 1 and 2, all three cracks occurred in the resin 11. From these results, the coefficient of thermal expansion α1, of the core substrate 2, the resin 11, the chip capacitor 12, and the IC chip 38
It is understood that it is important that α2, α3, and α4 satisfy the above Expressions 7 and 8, and that the thermal expansion coefficient α2 of the resin 11 be 40 ppm / ° C. or less, preferably 35 ppm / ° C. or less. Thus, it can be easily understood that the effect of the wiring board of the present invention is supported.

【0033】図4は異なる形態の配線基板における製造
方法の主要な工程に関する。尚、以下において、前記形
態と同じ部分や要素には前記と共通する符号を用いる。
図4(A)は、ガラスクロス入りのコア基板(配線基板本
体)40の表面41側に開口する凹部44内に前記と同
じ電子部品ユニット10を挿入する状態を示す。尚、上
記凹部44を有するコア基板40は、貫通孔を有する図
示しない厚肉の絶縁板と薄肉で平板の絶縁板とを、予め
接着シートを介して積層し加熱および圧着することによ
り形成されるが、凹部44を単一の絶縁板からルータな
どを用いて座ぐり加工により形成したものを用いても良
い。図4(A)に示すように、凹部44の底面45とコア
基板40の裏面42との間には、複数のスルーホール4
6が貫通し、各ホール46内には円筒形のスルーホール
導体48および充填樹脂47が貫通して形成されてい
る。
FIG. 4 relates to main steps of a manufacturing method for a wiring board of a different form. In the following, the same reference numerals are used for the same parts and elements as in the above embodiment.
FIG. 4A shows a state in which the same electronic component unit 10 is inserted into a concave portion 44 opened on the surface 41 side of a core substrate (wiring substrate main body) 40 containing glass cloth. The core substrate 40 having the concave portion 44 is formed by previously laminating a thick insulating plate (not shown) having a through hole and a thin flat insulating plate via an adhesive sheet, and heating and crimping. However, the concave portion 44 may be formed from a single insulating plate by spot facing using a router or the like. As shown in FIG. 4A, a plurality of through holes 4 are provided between the bottom surface 45 of the concave portion 44 and the back surface 42 of the core substrate 40.
6 penetrates, and in each hole 46, a cylindrical through-hole conductor 48 and a filling resin 47 are formed to penetrate.

【0034】図4(B)に示すように、各スルーホール導
体48の上端部と、挿入された電子部品ユニット10の
各コンデンサ12の底面における電極16とを、Sn−
Ag系合金からなるロウ材(低融点合金)49を介して個
別に予め接続しておく。かかる状態で、凹部44内に溶
けた樹脂11を注入した後、キュア処理を施す。その結
果、図4(B)に示すように、凹部44内において電子部
品ユニット10は、固化した樹脂11に固着および埋設
され且つ凹部44に内臓される。更に、樹脂11の盛り
上がった表面11aを研磨して平坦に整面することによ
り、図4(C)に示すように、新たに形成される樹脂11
の表面11cには、上記ユニット10中における各コン
デンサ12の電極14の上端面が露出する。
As shown in FIG. 4B, the upper end of each through-hole conductor 48 and the electrode 16 on the bottom surface of each capacitor 12 of the inserted electronic component unit 10 are connected to Sn-
They are individually connected in advance via a brazing material (low melting point alloy) 49 made of an Ag-based alloy. In this state, after the melted resin 11 is injected into the concave portion 44, a curing process is performed. As a result, as shown in FIG. 4B, the electronic component unit 10 is fixed and embedded in the solidified resin 11 in the concave portion 44 and is embedded in the concave portion 44. Further, the raised surface 11a of the resin 11 is polished and flattened to form a newly formed resin 11 as shown in FIG.
The upper end surface of the electrode 14 of each capacitor 12 in the unit 10 is exposed on the surface 11c.

【0035】以降は、前記図1に示したように、コア基
板40の表・裏面41,42上に前記図1で示した絶縁
層22,23など、配線層20,21などからなるビル
ドアップ層BU1,BU2、およびフィルドビア導体2
4,25などが形成される。この際、各電極14は前記
配線層20と接続され、上記スルーホール導体48の下
端は前記配線層21/27と接続される。また、図1と
同様にコア基板40の表・裏面41,42間を貫通する
スルーホール導体8(図示せず)が形成されると共に、第
1・第2主面34a,35a側に前記バンプ36や配線
(接続端子)37が形成される。これにより、凹部44に
複数のチップコンデンサ12を有する電子部品ユニット
10を内蔵したコア基板40を備える配線基板が得られ
る。
Thereafter, as shown in FIG. 1, the build-up of the wiring layers 20, 21 and the like on the front and back surfaces 41, 42 of the core substrate 40, such as the insulating layers 22, 23 shown in FIG. Layers BU1, BU2 and filled via conductor 2
4, 25, etc. are formed. At this time, each electrode 14 is connected to the wiring layer 20, and the lower end of the through-hole conductor 48 is connected to the wiring layer 21/27. 1, a through-hole conductor 8 (not shown) penetrating between the front and rear surfaces 41, 42 of the core substrate 40 is formed, and the bumps are formed on the first and second main surfaces 34a, 35a. 36 and wiring
(Connection terminals) 37 are formed. As a result, a wiring board including the core board 40 in which the electronic component unit 10 having the plurality of chip capacitors 12 in the recess 44 is obtained.

【0036】尚、上記コア基板(配線基板本体)40、樹
脂11、チップコンデンサ(電子部品)12の熱膨張率α
1,α2,α3は、前記数式7の関係下に設定されてい
る。また、ICチップ(半導体素子)38および絶縁層2
2などの熱膨張率α4,α5は、前記数式8または数式
9の関係下に設定されている。本実施形態では、配線基
板本体(コア基板)40の熱膨張率α1:16ppm/
℃、樹脂11の熱膨張率α2:23ppm/℃、チップ
コンデンサ(電子部品)12の熱膨張率α3:8ppm/
℃、ICチップ(半導体素子)38の熱膨張率α4:4p
pm/℃、絶縁層22などの熱膨張率α5:60ppm
/℃、とした。
The thermal expansion coefficient α of the core substrate (wiring substrate body) 40, resin 11, and chip capacitor (electronic component) 12
1, α2 and α3 are set under the relationship of the above equation (7). Further, the IC chip (semiconductor element) 38 and the insulating layer 2
The coefficients of thermal expansion α4 and α5, such as 2, are set in accordance with the relationship of the above formula 8 or formula 9. In the present embodiment, the thermal expansion coefficient α of the wiring substrate body (core substrate) 40 is 1:16 ppm /
° C, thermal expansion coefficient α2 of resin 11: 23 ppm / ° C, thermal expansion coefficient α3 of chip capacitor (electronic component) 12: 8 ppm /
° C, thermal expansion coefficient α4: 4p of IC chip (semiconductor element) 38
pm / ° C., coefficient of thermal expansion α5 of the insulating layer 22: 60 ppm
/ ° C.

【0037】本発明は、以上において説明した各形態や
実施例に限定されるものではない。例えば、前記電子部
品には、インダクタ、抵抗、フィルタなどの受動部品
や、ローノイズアンプ(LNA)、メモリ、半導体素子、
FET、またはトランジスタなどの能動部品、あるい
は、SAWフィルタ、LCフィルタ、アンテナスイッチ
モジュール、ダイプレクサなどや、これらをチップ状に
したもの、更には、これらのうち異種のもの同士を同じ
貫通孔や凹部内に内蔵しても良い。また、電子部品は、
一つのみを配線基板本体(コア基板)の貫通孔や凹部内に
内蔵しても良い。この場合、電子部品の電極をハンダ付
けにより、配線層やこれに接続するランドに接続するこ
とも可能である。
The present invention is not limited to the embodiments and examples described above. For example, the electronic components include passive components such as inductors, resistors, and filters, low-noise amplifiers (LNA), memories, semiconductor devices,
Active components such as FETs or transistors, or SAW filters, LC filters, antenna switch modules, diplexers, etc., or chips of these, and different types of these in the same through-hole or recess It may be built in. Also, electronic components
Only one may be built in the through-hole or recess of the wiring board body (core board). In this case, the electrodes of the electronic component can be connected to the wiring layer and the lands connected to the wiring layer by soldering.

【0038】更に、配線基板本体(コア基板)には、複数
の貫通孔または凹部を形成しても良く、あるいは、かか
る貫通孔と凹部とを隣接して併設することも可能であ
る。また、配線基板本体(コア基板)2,40の材質は、
前記ガラス−エポキシ樹脂複合材料の他、同様の耐熱
性、機械強度、可撓性、加工容易性などを有するガラス
織布や、ガラス織布などのガラス繊維とエポキシ樹脂、
ポリイミド樹脂、BT樹脂などの樹脂との複合材料であ
るガラス繊維−樹脂材料を用いても良い。あるいは、ポ
リイミド繊維などの有機繊維と樹脂との複合材料、連続
気孔を有するPTFEなどの3次元網目構造のフッ素系
樹脂にエポキシ樹脂などの樹脂を含浸させた樹脂−樹脂
複合材料などを用いることも可能である。
Further, a plurality of through holes or concave portions may be formed in the wiring substrate body (core substrate), or the through holes and the concave portions may be provided adjacent to each other. The material of the wiring board body (core board) 2 and 40 is
In addition to the glass-epoxy resin composite material, similar heat resistance, mechanical strength, flexibility, glass woven fabric having the ease of processing and the like, glass fiber and epoxy resin such as glass woven fabric,
A glass fiber-resin material which is a composite material with a resin such as a polyimide resin or a BT resin may be used. Alternatively, a composite material of an organic fiber and a resin such as a polyimide fiber, or a resin-resin composite material in which a resin such as an epoxy resin is impregnated into a fluororesin having a three-dimensional network structure such as PTFE having continuous pores may be used. It is possible.

【0039】更に、絶縁層22,23などの材質は、前
記エポキシ樹脂を主成分とするものの他、同様の耐熱
性、パターン成形性等を有するポリイミド樹脂、BT樹
脂、PPE樹脂、あるいは、連続気孔を有するPTFE
など3次元網目構造のフッ素系樹脂にエポキシ樹脂など
の樹脂を含浸させた樹脂−樹脂系の複合材料などを用い
ることもできる。また、配線層20,21などの材質
は、前記銅メッキの他、Niや、Ni−Auなどにして
も良く、あるいは、金属メッキを用いず、導電性樹脂を
塗布するなどの方法によって形成することも可能であ
る。更に、ICチップ38との接続端子には、前記フリ
ップチップバンプ36の他、フリップチップパッド、ワ
イヤボンディングパッド、あるいはTAB接続用パッド
を形成したものなどを用いても良い。
Further, the material of the insulating layers 22 and 23 may be a polyimide resin, a BT resin, a PPE resin, or a continuous pore having the same heat resistance, pattern moldability, and the like, in addition to the epoxy resin as a main component. PTFE having
For example, a resin-resin composite material in which a resin such as an epoxy resin is impregnated into a fluorine resin having a three-dimensional network structure can be used. Further, the material of the wiring layers 20, 21 and the like may be Ni, Ni-Au, or the like in addition to the copper plating, or may be formed by applying a conductive resin without using metal plating. It is also possible. Further, as the connection terminals to the IC chip 38, in addition to the flip chip bumps 36, those formed with flip chip pads, wire bonding pads, or TAB connection pads may be used.

【0040】また、前記電子部品12のコンデンサで
は、BaTiOを主成分とする高誘電体セラミックを
用いたが、PbTiO,PbZrO,TiO,S
rTiO,CaTiO,MgTiO,KNb
,NaTiO,KTaO,PbTaO,(N
1/2Bi1/2)TiO,Pb(Mg1/2
1/2)O ,(K1/2Bi1/2)TiOなどを主
成分とするものを用いても良い。更に、前記電子部品1
2の電極14,16の材質は、Cuを主成分としたが、
電子部品12との適合性を有するPt,Ag,Ag−P
t,Ag−Pd,Cu,Au,Niなどを用いることが
できる。加えて、前記電子部品のコンデンサ12は、高
誘電体セラミックを主成分とする誘電体層やAg−Pd
などからなる電極層と、樹脂やCuメッキ、Niメッキ
などからなるビア導体や配線層とを複合させたコンデン
サとしたものとしても良い。尚、本発明の配線基板に
は、前記コア基板2,40の表面3,41と裏面4,4
2上に配線層20,21と絶縁層22,23のみを有す
る形態も含まれる。
Further, in the capacitor of the electronic component 12,
Is BaTiO3High dielectric ceramics
Used, but PbTiO3, PbZrO3, TiO2, S
rTiO3, CaTiO3, MgTiO3, KNb
O3, NaTiO3, KTaO3, PbTaO3, (N
a1/2Bi1/2) TiO3, Pb (Mg1/2W
1/2) O 3, (K1/2Bi1/2) TiO3Mainly
What is used as a component may be used. Further, the electronic component 1
The material of the second electrodes 14 and 16 was mainly composed of Cu,
Pt, Ag, Ag-P compatible with the electronic component 12
t, Ag-Pd, Cu, Au, Ni, etc.
it can. In addition, the capacitor 12 of the electronic component has a high
Dielectric layer mainly composed of dielectric ceramic or Ag-Pd
Electrode layer made of resin, Cu plating, Ni plating
Condensed with via conductors and wiring layers
It is good also as what was made. The wiring board of the present invention
Are the front surfaces 3, 41 and the back surfaces 4, 4 of the core substrates 2, 40.
2 has only wiring layers 20 and 21 and insulating layers 22 and 23
Is included.

【0041】[0041]

【発明の効果】以上において説明した本発明の配線基板
(請求項1)によれば、配線基板本体(コア基板)の熱膨張
率は、内臓される電子部品のそれよりも大きく、且つ係
る電子部品が埋設される樹脂のそれと等しいか、または
それよりも小さい関係にある。このため、溶けた上記樹
脂を固化させるためや別途の位置での加熱に際し、上記
電子部品が膨張しても配線基板本体や樹脂は更に大きく
膨張するので、かかる配線基板本体の貫通孔または凹
部、あるいは上記電子部品を包囲し内臓する樹脂自体が
大きくなる。従って、樹脂や配線基板本体が割れたり破
損する事態を防止できるので、内臓される電子部品と内
部の配線層との間における導通を安定して確実に取るこ
とが可能となる。
The wiring board of the present invention described above.
According to the first aspect, the coefficient of thermal expansion of the wiring board body (core board) is larger than that of the built-in electronic component, and is equal to or smaller than that of the resin in which the electronic component is embedded. Also have a small relationship. For this reason, in order to solidify the melted resin, or when heating at a separate position, even if the electronic component expands, the wiring board body and the resin expand further, so that the through-holes or recesses of the wiring board body, Alternatively, the size of the resin that surrounds and houses the electronic component increases. Therefore, it is possible to prevent the resin or the wiring board main body from being broken or damaged, so that the conduction between the built-in electronic component and the internal wiring layer can be stably and reliably obtained.

【0042】また、請求項2の配線基板によれば、上記
に加えて、半導体素子の熱膨張率が内臓される電子部品
の熱膨張率と同じかそれ以下の関係になるため、例えば
第1主面上などに半導体素子を搭載する際のハンダ付け
時において、半導体素子が熱膨してもその熱膨張率は電
子部品と同じかそれ以下となる。このため、配線基板本
体や電子部品を埋設する樹脂に影響しなくなる。従っ
て、搭載した半導体素子と電子部品とを直に、または内
部の配線層を介して確実且つ安定して導通できると共
に、かかる配線基板を効率良く製造することも可能とな
る。
According to the second aspect of the present invention, in addition to the above, since the coefficient of thermal expansion of the semiconductor element is equal to or less than the coefficient of thermal expansion of the built-in electronic component, for example, At the time of soldering when mounting a semiconductor element on a main surface or the like, even if the semiconductor element expands thermally, its coefficient of thermal expansion is equal to or less than that of the electronic component. For this reason, it does not affect the resin in which the wiring board body and the electronic components are embedded. Therefore, the mounted semiconductor element and the electronic component can be reliably and stably conducted directly or via an internal wiring layer, and the wiring substrate can be efficiently manufactured.

【0043】更に、請求項3の配線基板によれば、前記
の各関係に加えて、絶縁層は、前記樹脂と同じかそれ以
上に熱膨張するため、樹脂を固化させる際や別途の位置
での加熱に際し、電子部品、配線基板本体、および樹脂
が膨張しても、絶縁層はこれらよりも更に大きく膨張す
る。このため、樹脂などの膨張を吸収できるので、樹脂
や配線基板本体が割れたり破損する事態を防止できる。
従って、電子部品と絶縁層間の配線層との間における導
通を安定して確実に取ることが可能となる。加えて、請
求項4の配線基板によれば、前記樹脂や配線基板本体が
割れたり破損する事態を防止したり、半導体素子の膨張
による配線基板本体などへの影響を一層確実に阻止する
ことが可能となる。
Further, according to the wiring board of the third aspect, in addition to the above relationships, the insulating layer thermally expands to the same degree or more than the resin, so that the insulating layer may be solidified when the resin is solidified or at a separate position. When the electronic component, the wiring board main body, and the resin expand during heating, the insulating layer expands further more than these. For this reason, since the expansion of the resin or the like can be absorbed, it is possible to prevent the resin or the wiring board body from being broken or damaged.
Therefore, it is possible to stably and reliably establish conduction between the electronic component and the wiring layer between the insulating layers. In addition, according to the wiring board of the fourth aspect, it is possible to prevent the resin or the wiring board body from being cracked or damaged, and to more reliably prevent the expansion of the semiconductor element from affecting the wiring board body. It becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による1形態の配線基板における主要部
を示す断面図。
FIG. 1 is a sectional view showing a main part of a wiring board according to one embodiment of the present invention.

【図2】図1の配線基板に内蔵する電子部品ユニットの
斜視図。
FIG. 2 is a perspective view of an electronic component unit built in the wiring board of FIG. 1;

【図3】(A)乃至(C)は図1の配線基板の製造方法にお
ける主要な工程を示す概略図。
FIGS. 3A to 3C are schematic diagrams showing main steps in a method of manufacturing the wiring board of FIG. 1;

【図4】(A)乃至(C)は、異なる形態の配線基板の製造
方法における主要な工程を示す概略図。
FIGS. 4A to 4C are schematic views showing main steps in a method of manufacturing a wiring board of a different form.

【図5】(A)および(B)は、従来の配線基板を示す概略
図。
FIGS. 5A and 5B are schematic diagrams showing a conventional wiring board.

【符号の説明】[Explanation of symbols]

1………………………………………配線基板 2,40………………………………配線基板本体(コア
基板) 3,41………………………………表面 4,42………………………………裏面 6………………………………………貫通孔 12……………………………………チップコンデンサ
(電子部品) 11……………………………………樹脂 22,23,28,29,34,35…絶縁層 34a…………………………………第1主面(配線基板
本体の表面上方) 38……………………………………ICチップ(半導体
素子) 44……………………………………凹部
1 ………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… 3,41 ……… Front 4,42 ………………… Back side 6 ………………………………………………………………… Through-hole 12 …………… Chip capacitors
(Electronic components) 11 Resin 22, 23, 28, 29, 34, 35 Insulating layer 34a ............... First Main surface (above the surface of the main body of the wiring board) 38 IC chip (semiconductor element) 44 …………………… Recess

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】表・裏面を有する絶縁性の配線基板本体
と、この配線基板本体に設けた貫通孔または凹部と、か
かる貫通孔または凹部内に内蔵され且つ樹脂を介して固
着される電子部品と、を含むと共に、 上記配線基板本体、樹脂、および電子部品の熱膨張率α
1,α2,α3が数式1の関係にある、ことを特徴とす
る配線基板。 【数1】α3<α1≦α2
1. An insulative wiring board main body having front and back surfaces, a through hole or a recess provided in the wiring board main body, and an electronic component incorporated in the through hole or the recess and fixed via a resin. And the thermal expansion coefficient α of the wiring board body, the resin, and the electronic component.
1, wherein α1, α2 and α3 have a relationship represented by Expression 1. Equation 1 α3 <α1 ≦ α2
【請求項2】表・裏面を有する絶縁性の配線基板本体
と、この配線基板本体に設けた貫通孔または凹部と、か
かる貫通孔または凹部内に内蔵され且つ樹脂を介して固
着される電子部品と、上記配線基板本体の表面上方に搭
載され且つ上記電子部品と導通される半導体素子と、を
含むと共に、 上記配線基板本体、樹脂、電子部品、および、半導体素
子の熱膨張率α1,α2,α3,α4が数式2の関係に
ある、ことを特徴とする配線基板。 【数2】α4≦α3<α1≦α2
2. An insulative wiring board body having front and back surfaces, a through hole or a recess provided in the wiring board body, and an electronic component incorporated in the through hole or the recess and fixed via a resin. And a semiconductor element mounted above the surface of the wiring board main body and electrically connected to the electronic component, and the thermal expansion coefficients α1, α2, of the wiring board main body, the resin, the electronic component, and the semiconductor element. α3, α4 have a relationship represented by the following equation (2). ## EQU2 ## α4 ≦ α3 <α1 ≦ α2
【請求項3】表・裏面を有する絶縁性の配線基板本体
と、この配線基板本体に設けた貫通孔または凹部と、か
かる貫通孔または凹部内に内蔵され且つ樹脂を介して固
着される電子部品と、上記配線基板本体の表面および裏
面の少なくとも一方の上に形成される絶縁層と、を含む
と共に、 上記配線基板本体、樹脂、電子部品、および、絶縁層の
熱膨張率α1,α2,α3,α5が数式3の関係にあ
る、ことを特徴とする配線基板。 【数3】α3<α1≦α2≦α5
3. An insulative wiring board body having front and back surfaces, a through hole or a recess provided in the wiring board body, and an electronic component incorporated in the through hole or the recess and fixed via a resin. And an insulating layer formed on at least one of the front surface and the back surface of the wiring board body, and the thermal expansion coefficients α1, α2, α3 of the wiring board body, the resin, the electronic component, and the insulating layer. , Α5 have the relationship of Equation 3. Equation 3 α3 <α1 ≦ α2 ≦ α5
【請求項4】前記樹脂の熱膨張率α2が、40ppm/
℃よりも小さい、ことを特徴とする請求項1乃至3の何
れかに記載の配線基板。
4. A resin having a coefficient of thermal expansion α2 of 40 ppm /
The wiring board according to claim 1, wherein the temperature is lower than ℃.
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JP2004006828A (en) * 2002-04-26 2004-01-08 Ngk Spark Plug Co Ltd Wiring board
JP2007096258A (en) * 2005-09-01 2007-04-12 Ngk Spark Plug Co Ltd Wiring substrate and ceramic capacitor
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JP2012156533A (en) * 2012-03-26 2012-08-16 Dainippon Printing Co Ltd Component built-in wiring board, and method of manufacturing component built-in wiring board
US8299366B2 (en) 2009-05-29 2012-10-30 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
JP2013042164A (en) * 2010-03-30 2013-02-28 Murata Mfg Co Ltd Component assembly
JP2014027282A (en) * 2012-07-30 2014-02-06 Samsung Electro-Mechanics Co Ltd Manufacturing method of electronic element built-in substrate
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US8917520B2 (en) 2011-12-22 2014-12-23 Taiyo Yuden Co., Ltd. Circuit substrate
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JP2004006828A (en) * 2002-04-26 2004-01-08 Ngk Spark Plug Co Ltd Wiring board
JP2007096258A (en) * 2005-09-01 2007-04-12 Ngk Spark Plug Co Ltd Wiring substrate and ceramic capacitor
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US8917520B2 (en) 2011-12-22 2014-12-23 Taiyo Yuden Co., Ltd. Circuit substrate
US9093981B2 (en) 2011-12-22 2015-07-28 Taiyo Yuden Co., Ltd. Circuit substrate
JP2012156533A (en) * 2012-03-26 2012-08-16 Dainippon Printing Co Ltd Component built-in wiring board, and method of manufacturing component built-in wiring board
JP2014027282A (en) * 2012-07-30 2014-02-06 Samsung Electro-Mechanics Co Ltd Manufacturing method of electronic element built-in substrate
WO2019186780A1 (en) * 2018-03-28 2019-10-03 株式会社Fuji Circuit formation method and circuit formation device
JPWO2019186780A1 (en) * 2018-03-28 2020-12-03 株式会社Fuji Circuit formation method and circuit formation device

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