JP4685251B2 - Wiring board manufacturing method - Google Patents

Description

【００７６】
尚、表１において、○は良好、×は不良を示す。
また本実施例では、シート材２３の粘着剤２４としてシリコン系のものを使用したが、これは、次のような実験に基づいている。表２は、シート材（基材）と粘着剤との種々の組み合わせについて、硬化した充填樹脂４からの剥がし易さ、およびシート材の耐熱性（２００℃の環境における変形、変質の有無）について調べた結果を示している。この実験において、充填樹脂４としてはエポキシ樹脂を使用し、これにシリカフィラーを混入したものを用いた。
【００７７】
【表２】

【００７８】
尚、表２において、○は良好、×は不良、−は未確認であることを示す。
表２に示す様に、基材がポリエステルまたはポリイミドであると、シート材２３は耐熱性に優れたものとなり変形や変質がなく、また、粘着剤がシリコン系である場合には、充填樹脂の硬化後に剥がし易いことがわかる。
【００７９】
本実施例では、シート材２３の基材としてポリイミドを用い、かつシリコン系の粘着剤２４を用いているので、充填樹脂４を熱硬化させる際にシート材２３に変形がなく、そのためシート材２３上に配置した電子部品（コンデンサ素子１３）の位置ずれが少なく、高い位置精度で電子部品を配線基板本体３内に設けることができる。また硬化した充填樹脂４からシート材２３を剥がしやすいため、シート材２３の一部が残渣となって後のビルドアップ工程に支障をきたすことを防ぐことができる。
【００８０】
さて、以上の様に各主面３ａ，３ｂ側を研磨した後、次に図３（ｆ）に示す様に、スルーホール１１の形成、及び、各主面３ａ，３ｂ上への第１導体層５ａ，５ｂの形成を行う。
第１導体層５ａ，５ｂの形成は、次の様にして行われる。即ち、貫通孔２１内にコンデンサ素子１３を内蔵した配線基板本体３全体に、Ｃｕにて無電解メッキを施した後、更にＣｕにて電解メッキを施すことにより、配線基板本体３全体にパネルめっきを行う。そして、エッチングによって導体層の不要部分を除去することにより、第１導体層５ａ，５ｂを形成する。
【００８１】
なお、パネルめっきの際には、コンデンサ素子１３の外部接続部１４の露出部分にもメッキが形成される。即ち、外部接続部１４は、メッキにより、配線基板１の配線（ここでは、第１導体層５ａ，５ｂ）と接続されることになる。しかも、その接続は、配線の形成と同時に実現される。
【００８２】
この様にコンデンサ素子１３の外部接続部１４と導体層との接続をメッキにより行うため、以下の効果がある。即ち、半田によりコンデンサ素子１３を実装するときには、半田実装のための受けランドを形成するために所定の面積（例えば４６０μｍ×９００μｍ）を必要とし、コンデンサ素子１３の実装密度を高くする上での制限となる。これに対して、コンデンサ素子１３の外部接続部１４と導体層との接続をメッキにより行うと、受けランドを形成する必要がなく、しかも外部接続部１４のうち導体層との接続に必要な面積は小さいので（例えば３００μｍ×１００μｍ）、コンデンサ素子１３を高密度に実装できる。
【００８３】
また、メッキにより配線形成と同時にコンデンサ素子１３の外部接続部１４と導体層との接続を図ることができ、半田印刷という工程を省略できるため、安価に実装可能である。また、半田リフローによるコンデンサ素子１３のダメージをなくすことができる。
【００８４】
また、上記のパネルめっきの際には、貫通孔９の内周面にもメッキ層を形成し、その後貫通孔９内部に樹脂を充填し硬化させることにより、スルーホール１１を形成する（図３（ｆ））。なお、配線基板本体３に貫通孔９を形成し、内周面にメッキ層を形成し、樹脂を充填した後、貫通孔を形成し、同様にコンデンサ素子１３を内蔵しても良い。
【００８５】
以上の様な第１導体層５ａ，５ｂの形成後、第１主面３ａ側及び第２主面３ｂ側において、充填樹脂４、第１導体層５ａ，５ｂ並びに上端部１４ａ及び下端部１４ｂの上に、エポキシ樹脂を主成分とするフィルム化された感光性樹脂を貼付する。そして、この感光性樹脂を露光・現像することにより、上端部１４ａ及び下端部１４ｂを露出すべき位置にビアホールを形成し、感光性樹脂を硬化させて、第１層間絶縁層１０３ａ，１０３ｂを形成する。なお、ビアホールは、第１層間絶縁層１０３ａ，１０３ｂを感光性のない樹脂で形成した後、レーザなどを用いて穿設しても良い。
【００８６】
さらに、Ｃｕにて無電解メッキおよび電解メッキを施し、第１層間絶縁層１０３ａ、１０３ｂに形成したビアホールに導電体を充填すると共に、パネルメッキを行ってメッキ層を形成する。このメッキ層の上にドライフィルムを貼り付け、露光現像してエッチングレジストを形成し、メッキ層の内の不要部分をエッチングにより除去する。これにより、第２導体層１０５ａ、１０５ｂから成る配線が形成される。なお、導体層の形成には、周知のサブトラクティブ法の他、フルアディティブ法やセミアディティブ法を用いてもよい。
【００８７】
以降は、同様にして第２層間絶縁層１０７ａ，１０７ｂ、フィルドビア１１７ａ，１１７ｂ、フリップチップパッド１１１（ＬＧＡパッド１１３）を順に形成し、その後ソルダレジスト層１０９ａ，１０９ｂを形成する。そして、ソルダレジスト層１０９ａから露出したフリップチップパッド１１１の上には、Ｎｉ−Ａｕメッキ層を形成し、更にハンダペーストを塗布しリフローすることで、フリップチップバンプ１１２を形成する。以上、第１導体層５ａ，５ｂ、第２導体層１０５ａ、１０５ｂなどを形成する工程が、請求項の「配線形成工程」に相当する。なお、フィルドビア１１７ａ，１１７ｂの一部は、フィルドビア１１５ａ，１１５ｂ等の直上に形成される。
【００８８】
以上の様にして、図１に示す構造の配線基板１が完成されるが、ＬＧＡパッド１１３の表面には、酸化防止のためにＮｉ−Ａｕメッキ層を形成すると良い。
なお、本実施例において、外部接続部１４の上端１４ａおよび下端１４ｂにおいて、素子本体１５から５０μｍ程度突出するように形成されるものとして説明したが、これは発明者らによる試験結果に基づいている。即ち、外部接続部１４の上端１４ａおよび下端１４ｂにおける、素子本体１５からの突出の高さ（以下「電極の高さ」という）を変え、上記の工程により配線基板の製造を行ったところ、表３に示す結果が得られた。
【００８９】
【表３】

【００９０】
表３は、「電極の高さ」が夫々１０μｍ，１５μｍ，３０μｍ，６０μｍ，１００μｍ，１２０μｍとされた試料（コンデンサ素子１３）を用いた場合において、研磨工程後における不具合の発生状況と、第１導体層５ａ，５ｂを形成するためのメッキ工程後における不具合の発生状況を示している。
【００９１】
研磨工程後における不具合とは、例えば、素子本体１５が充填樹脂４の外部に露出したり、誤って研磨されるといったものであるとか、また素子本体１５を覆っている充填樹脂４が割れるといったものである。また、メッキ工程後における不具合とは、例えば素子本体１５を覆っている充填樹脂４の浮き、脱落が発生したり、或いは電極間の短絡（同じコンデンサ素子１３の外部接続部１４の間における短絡、又は異なるコンデンサ素子１３の外部接続部１４の間における短絡）が発生したりするといったものである。
【００９２】
表３に示す様に、「電極の高さ」が１０μｍである場合、研磨工程により８８％の割合で不具合が生じた。また、「電極の高さ」が１５μｍである場合は、研磨工程により６２％の割合で不具合が生じ、そして、研磨工程後には問題がなかった物のうちの６％が、メッキ工程後に不具合を生じた。
【００９３】
また「電極の高さ」が１２０μｍである場合、メッキ工程後に電極間（特に同じコンデンサ素子１３の外部接続部１４の間）が短絡するという不具合が発生しやすくなった。
これらの結果に対して、「電極の高さ」が３０μｍ，６０μｍ，１００μｍである試料については、上記の様な不具合は、研磨工程後においても、メッキ工程後においても見られなかった。こうしたことから、「電極の高さ」を、本実施例では５０μｍとしたのである。
【００９４】
以上説明した本実施例の製造方法によれば、以下の効果（１）〜（９）を奏する。
（１）外部接続部１４の上端（即ち上端部１４ａ）は、第１主面３ａよりも上側にあることから、充填樹脂４内に外部接続部１４の上端が埋まり難い。仮に埋まってしまっても、充填樹脂４を研磨することにより、第１主面３ａ側に容易に外部接続部１４を露出させることができる。また、素子本体１５の上端は、第１主面３ａよりも下側にあるので、第１主面３ａ側において充填樹脂４を研磨する際に、素子本体１５が削られる畏れが少ない。
【００９５】
（２）外部接続部１４の直上に、フィルドビア１１５ａ，１１５ｂ（バイアホール導体）が形成されていることから、ＩＣチップなど配線基板表面に設けられる素子と、当該内蔵した電子部品との接続経路が短くなり、ノイズの侵入を抑制するなど、電気的特性が向上する。また、フィルドビア１１５ａ，１１５ｂの更に直上にフィルドビア１１７ａ，１１７ｂ（バイアホール導体）が形成されているから、電気的特性が更に向上する。
【００９６】
（３）外部接続部１４の下端（即ち下端部１４ｂ）は、第２主面３ｂよりも下側にあることから、充填樹脂４内に外部接続部１４の上端が埋まり難い。仮に埋まってしまっても、充填樹脂４を研磨することにより、第１主面３ａ側に容易に外部接続部１４を露出させることができる。そして、素子本体１５の上端は、第１主面３ａを基準として上側にあることから、充填樹脂４の第２主面３ｂ側を研磨する際に、素子本体１５が削られ損傷する畏れも少ない。
【００９７】
（４）＃４００の研磨布紙を用いて充填樹脂４を研磨したので、配線基板本体３の表面や導体層２０ａ、２０ｂにキズが付きにくい。そのため、例えばビルドアップ法などの、配線形成を支障なく行うことができる。
（５）＃４００の研磨布紙を用いて充填樹脂４を研磨したので、導体層２０ａ、２０ｂの剥離を生じさせる可能性が少ない。
【００９８】
（６）外部接続部１４を複数層（本実施例では２層）の導体層、即ち外部電極層３０および外部接続層３１で形成するので、容易に、コンデンサ素子本体１５からの外部接続部１４の高さを稼ぐことができる。
（７）外部接続層３１（最外層）をメッキにて形成することとしていることから、その厚さの調整が容易である。
【００９９】
（８）外部電極層３０および外部接続層３１を同一の材料（Ｃｕ）で形成し、しかも、その材料を第１配線層５ａ，５ｂ、フィルドビア１０５ａ、１０５ｂ…などの、配線基板１の内部配線と同一としていることから、熱応力の発生による断線を抑制できる。
【０１００】
（９）「電極の高さ」を充分に大きくとったため、素子本体１５が研磨されて損傷したり、充填樹脂４のうち素子本体１５を覆う部分に割れや剥がれが生じたりすることがない。また、電子部品１３をシート材２３の上に配置した際、素子本体１５とシート材２３との間には、充填樹脂４が流入するための隙間を充分大きく形成できることとなり、素子本体１５の表面に充填樹脂４にて覆われない部分が生じることを防止できる。この様に、素子本体１５の保護を確実に図ることができ、電子部品１３の電気的特性の信頼性を高めることができる。
【０１０１】
以上、本発明の一実施例について説明したが、本発明は上記実施例に限定される物ではなく、例えば、以下の様な種々の態様も本発明の技術的範囲に属する。
例えば、上記実施例では、各貫通孔２１にコンデンサ素子１３を複数内蔵するものとして図示して説明したが、これに限らず単数のコンデンサ素子１３を内蔵してもよい。
【０１０２】
また、上記実施例では、収容部として、貫通孔２１を例にとって説明したが、これに限られるものではなく、凹部に電子部品を収容する場合にも本発明を適用できる。
また、上記実施例では、コンデンサ素子１３において、その外部接続部１４を、外部電極層３０と外部接続層３１の２層により形成するものとして説明したが、これに限られるものではない。
【０１０３】
例えば、図４（ａ）に示す様な構成のものでも良く、これは次のようにして構成することができる。まず、素子本体２１５の側面に外部電極層２３０をＣｕペーストの印刷により形成する。但し、そのとき、素子本体２１５の側面においては厚く形成できるが、配線基板１の配線（例えば第１導体層５ａなど）と接続すべき部位（図４では上端）においては十分な厚さ（即ち、素子本体２１５からの高さ）が得られない場合がある。そうした場合には、図４（ｂ）の様に、当該部位に、例えばＣｕペースト２３２を更に付着させ、盛り上げるようにして、十分な厚みを得るようにする。その後、図２と共に上述した如く、Ｎｉメッキを施し、外部接続層２３１（例えば２μｍ程度）を形成する。これにより、外部接続部２１４の上端部２１４ａを、素子本体２１５から６０μｍ程度突出して形成する。
【０１０４】
Ｃｕペーストを付着させる部位は、上下両端である必要はなく、図４（ｃ）の様に、片側のみでもよい。即ち、上記実施例では、外部接続部１４は、その上端１４ａおよび下端１４ｂにおいて素子本体１５から充分高く突出するよう形成されたものとして説明したが、これに限られるものではない。
【０１０５】
こうしたコンデンサ素子２１３の場合、これを配線基板１に内蔵するには、図６に示す工程を採用すればよい。
使用する配線基板本体３は、図３（ａ）に示したものと同様のものである。そして、図３（ａ）と共に説明した様に、配線基板本体３に、スルーホール１１を構成するための貫通孔９を多数個形成（例えばドリルにより）すると共に、コンデンサ素子１３を配置するための貫通孔２１を形成（例えばパンチングにより）する。
【０１０６】
そして図６（ａ）に示すように、電子部品配設用の貫通孔２１の開口部の一方を、片面にシリコン系の粘着剤２４を有するポリイミドからなるシート材２３で覆う。なお、この図では、配線基板本体３を裏表反転させ、第１主面３ａ側の開口部をシート材２３で塞ぐ。また、その際、上記と同様に、粘着剤２４を有する面２３ａが配線基板本体３側に向けられ、シート材２３は配線基板本体３（詳しくは、導体層２０ａ）に張り付けられる。
【０１０７】
この様にシート材２３で貫通孔２１を塞いだ後、図６（ａ）に示す様に、コンデンサ素子２１３を、粘着剤２４を介してシート材２３に粘着するよう、貫通孔２１の内部に配置する。
この際、コンデンサ素子２１３の上下を逆にして、その外部接続部２１４の上端２１４ａにてシート材２３に粘着すると共に、その素子本体２１５とシート材２３との間には充填樹脂４が流入可能な隙間が形成されるよう配置する。しかも、外部接続部１４の上端（図６（ａ）中、Ａ１で示す）が第１主面３ａを基準面（Ｂ１で示す）として下側に位置し、素子本体１５の上端（Ｃ１で示す）は、第１主面３ａを基準面（Ｂ１）として上側に位置するように、コンデンサ素子２１３を配置する。
【０１０８】
以上の様にして貫通孔２１の内部にコンデンサ素子２１３を配置した状態とした上で、図６（ｂ）の様に、貫通孔２１の内部に充填樹脂４を注入し、充填樹脂４を硬化させる。これにより、配線基板本体３の内部に電子部品としてのコンデンサ素子１３が埋設されることとなる。また、コンデンサ素子２１３の素子本体２１５とシート材２３との間にも、充填樹脂４が充填される。そして充填樹脂４を貫通孔２１に注入した後、上記実施例と同様にして、充填樹脂４から真空脱泡により気泡を抜き、充填樹脂４を硬化させる。また、充填樹脂４には、上記実施例と同様のものを用いればよい。
【０１０９】
充填樹脂４を硬化させた後、次に、シート材２３を、コンデンサ素子２１３の外部接続部２１４、充填樹脂４および配線基板本体３（詳しくは、導体層２０ａ）から除去し、その後、充填樹脂４および配線基板本体３の各主面３ａ，３ｂを、ベルトサンダーにより研磨する（図６（ｃ））。
【０１１０】
シート材２３の除去によって、第１主面３ａ側からは、外部接続部２１４の上端部２１４ａが、充填樹脂４の外部に露出される。また、コンデンサ素子２１３の素子本体２１５は、充填樹脂４の中に埋没した状態となっている。
なお、このコンデンサ素子２１５の外部接続部２１４は、配線基板本体３の厚みよりも短いため、図６（ｃ）に示す様に、研磨工程後においても第２主面３ｂ側から外部接続部２１４ｂが露出しない。
【０１１１】
そこで、次に図６（ｄ）に示す様に、第２主面３ｂ側からレーザを照射することにより充填樹脂４に穴２０４（バイアを形成するための穴）を穿設して、外部接続部２１４の下端部２１４ｂを充填樹脂４の外部に露出させる。
そして、図６（ｅ）に示す様に、各主面３ａ，３ｂ上への第１導体層５ａ，５ｂの形成、およびスルーホール１１の形成を行う。これについては、上記実施例と同様であり、パネルめっきの際には、コンデンサ素子２１３の外部接続部１４の露出部分にもメッキが形成されるが、同時に、上記穴２０４にはメッキが充填される。
【０１１２】
第１導体層５ａ，５ｂの形成後の工程については、上記実施例と同様であるので説明を省略するが、以上の様にして、図５に示す構成の配線基板を得ることができる。
なお、図７に示す様に、例えば、ＩＣチップ１６の搭載面側に向く側の端部（図７では上端）においてのみ、素子本体２１５から突出するものとして外部接続部１４を構成しても良い。この構造の配線基板は、図６と共に説明した製造工程から「第２主面３ｂ側におけるレーザによる穴開け」を除いた工程により得ることができる。
【０１１３】
また、上記実施例では、電子部品として、コンデンサ素子１３を配線基板に内蔵するものとして説明したが、これに限らず、チップ状の抵抗体、インダクタ、フィルタ（ＳＡＷフィルタ、ＬＣフィルタ等）、カプラ、ダイプレクサ、アンテナスイッチモジュール等の受動部品や、トランジスタ、メモリ、ローノイズアンプ（ＬＮＡ）、ＦＥＴ等の能動部品など、各種の電子部品を内蔵させてもよい。また、これらのうちで異種の電子部品同士を同じ貫通孔内に内蔵してもよい。
【０１１４】
また、上記実施例の説明においては、図３（ｄ）に示す様に、第１主面３ａ側（即ち、シート材２３で貫通孔２１を塞がない開口部の側）から、貫通孔２１内に充填樹脂４を注入するものとして説明した。しかし、充填樹脂４の粘性と貫通孔２１内の隙間との関係によっては、貫通孔２１内において、充填樹脂４が第２主面３ｂ側にまで十分行き渡らない可能性がある。貫通孔２１内における隙間とは、コンデンサ素子１３同士の間、或いはコンデンサ素子１３と貫通孔２１の内壁との間、コンデンサ素子１３の素子本体１５と、シート材２３との間などである。そこで、シート材２３を剥がした後、開口部２１ａ側からも、充填樹脂４を貫通孔２１内に注入するとよい。そうすれば、隙間なく、確実に貫通孔２１に充填樹脂４を充填することができる。
【０１１５】
また、上記実施例では、配線基板本体３の材質として、ガラス−エポキシ樹脂複合材料を用いたが、これに限られることなく、耐熱性、機械強度、可撓性、加工の容易さ等を考慮して選択すればよい。従って、例えばガラス織布、ガラス不織布などのガラス繊維と、エポキシ樹脂、ポリイミド樹脂、ＢＴ樹脂等の樹脂との複合材料であるガラス繊維−樹脂複合材料を用いることができる。また、ポリイミド繊維などの有機繊維と樹脂との複合材料、連続気孔を有するＰＴＦＥなど３次元網目構造のフッ素系樹脂にエポキシ樹脂等の樹脂を含浸させた樹脂−樹脂複合材料などを用いることができる。
【０１１６】
また、配線基板本体としては、導体層（導体パターン）が内蔵されている多層基板を用いてもよい。例えば、図８に示す配線基板の配線基板本体３０３の内部には、導体層３０５ａ，３０５ｂが形成されている。この配線基板本体３０３は、例えば図９の様な手順により得ることができる。
【０１１７】
まず、図９（ａ）に示す様な銅張積層板を用意する。これは、例えば、ＢＴ樹脂、ＦＲ−４、ＦＲ−５などからなる絶縁基板３０６の両面に銅を積層して導体層３０５ａ、３０５ｂを形成したものである。この絶縁基板３０６の両面に形成された銅製の導体層３０５ａ、３０５ｂをエッチングすることにより、所要のパターンを形成する（図９（ｂ）参照）。
【０１１８】
次に銅張積層板の両面を粗化し、図９（ｃ）に示す様に、両面に絶縁材３０７ａ，３０７ｂをラミネートする。絶縁材３０７ａ、３０７ｂは、上記の絶縁基板３０６を構成する樹脂とは異なる材料であっても同じ材料であってもよく、例えばエポキシ樹脂など、種々の樹脂のものを使用できる。この様にして、内部に導体層３０５ａ，３０５ｂを有する配線基板本体３０３を得ることができる。
【０１１９】
次に、図９（ｄ）に示す様に、ビアを形成するための穴部３０８を絶縁材３０７ａ，３０７ｂにレーザで形成したり、スルーホールを形成するためのスルーホール貫通孔３０９をレーザやドリルにより形成する。
次に図９（ｅ）に示す様に、パネルめっきを施すことにより、絶縁材３０７ａ，３０７ｂの表面、穴部３０８の内面およびスルーホール貫通孔３０９の内周面に、Ｃｕからなるメッキ層３１２を形成し、そして、図９（ｆ）に示すように、スルーホール貫通孔３０９の内部には、シリカフィラーを含有するエポキシ樹脂などの穴埋樹脂３１４を充填し、硬化させる。この穴埋樹脂３１４は、絶縁材３０７ａ，３０７ｂの表面のメッキ層３１２と略同一面を形成するように研磨する。
【０１２０】
電子部品を内蔵するためには、図９（ｇ）に示す様に、電子部品配置用貫通孔３２１を形成し、この電子部品配置用貫通孔３２１の開口部をシート材２３で塞ぐ。そして図５と共に説明した手順によって、電子部品を配線基板本体３０３に内蔵でき、更にビルドアップ層を形成することができる。
【０１２１】
また、例えば図１０に示す様に、予め内部に導体層４０５ａ，４０５ｂを有する配線基板本体４０３を用いてもよい。これを用いて図８と略同様な配線基板を得るには、まず図１０（ａ）に示す配線基板本体４０３に、スルーホール貫通孔４０７やビア形成用の穴部（図示せず）などを形成する（図１０（ｂ））。次にパネルめっきにより配線基板本体４０３の両面およびスルーホール貫通孔４０７の内周面にメッキ層４０９を積層し（図１０（ｃ））、そしてスルーホール貫通孔４０７の内部に穴埋樹脂４１１を充填する（図１０（ｄ））。そして更に、電子部品配置用貫通孔４２１を形成する（図１０（ｅ））。この後、電子部品配置用貫通孔３２１の開口部をシート材で塞ぎ、図５と共に説明した手順によって、電子部品を配線基板本体４０３に内蔵でき、更にビルドアップ層を形成することができる。
【０１２２】
以上の様に、配線基板本体として、導体層が内蔵されているものを用いると、配線基板本体の上に積層すべき導体層の数を減らすことができる。例えば、図１では、配線基板本体の両主面の上に導体層を３層ずつ積層したものを示したが、これに対し、配線基板本体として導体層を内蔵したものを用いた場合には、図８に示す様に、両主面の上に積層すべき導体層の数が２層ずつに減少している。
【０１２３】
そのため、電子部品とＩＣチップとの間の導通経路を短くすることができ、ループインダクタンス、スイッチングノイズ、クロストークノイズなどの低減、即ち、配線基板の電気的特性の向上を図ることが可能となる。
また、スルーホール貫通孔が配線基板本体を貫通し、配線基板本体の両主面の上に積層すべき導体層の数が２層ずつになっていることから、スタックトビア（積み上げビア）を形成する必要がなくなる。そして、スタックトビアが不要となるため、フィルドビア（導体で完全に充填されたビア）を形成する必要がなくなり、コンフォーマルビア（導体で完全には充填されないビア）で足りることになるので、ビアの形成にかかるコストを抑制することができる。
【０１２４】
なお、図８では、配線基板本体３０３の両主面上に２層の導体層を積層するものとして示したが、その層数はこれに限定されない。また、配線基板本体３０３の内部には２層の導体層３０５ａ，３０５ｂを有するものとして説明したが、その層数はこれに限定されるものではない。
【０１２５】
さて、上記実施例では、研磨布紙で充填樹脂４を研磨するものとして説明したが、研磨布紙以外の手段を用いても良いことは明らかである。
また、上記実施例では、第１層間絶縁層１０３ａ，１０３ｂ、第２層間絶縁層１０７ａ，１０７ｂとしてエポキシ樹脂を主成分とするものを用いたが、耐熱性、パターン成形性等を考慮して適宜選択すればよい。例えば、ポリイミド樹脂、ＢＴ樹脂、ＰＰＥ樹脂、連続気孔を有するＰＴＦＥなど３次元網目構造のフッ素系樹脂にエポキシ樹脂等の樹脂を含浸させた樹脂−樹脂複合材料などを用いることができる。
【０１２６】
また、上記実施例では、第１導体層５ａ，５ｂ、第２導体層１０５ａ，１０５ｂ等を無電解Ｃｕメッキ及び電解メッキによって形成したが、他の材質、例えばＮｉ，Ｎｉ−Ａｕ等によって形成しても良く、さらには、メッキによらず、導電性樹脂を塗布するなどの手法によって形成しても良い。
【０１２７】
また、上記実施例では、ＩＣチップ１６との接続のために、配線基板上面にフリップチップパッド１１１やフリップチップバンプ１１２を多数設けた。しかし、ＩＣ接続端子としては、接続するＩＣチップに形成された端子に応じて、適切な形態のものを使用すれば良く、フリップチップバンプを形成したものの他、フリップチップパッドのみのもの、或いはワイヤボンディングパッドやＴＡＢ接続用のパッドを形成したものなどが挙げられる。また、フリップチップバンプの半田には、Ｓｎ−Ａｇ、Ｓｎ−Ａｇ−Ｃｕ、Ｓｎ−Ｐｂ、Ｓｎ−Ｓｂ、Ｓｎ−Ｚｎ系等の半田を使用できる。
【０１２８】
また、上記実施例では、コンデンサ素子１３の素子本体１５にＢａＴｉＯ₃を主成分とする高誘電体セラミックを用いたが、この材質に限定されず、例えば、ＰｂＴｉＯ₃、ＰｂＺｒＯ₃、ＴｉＯ₂、ＳｒＴｉＯ₃、ＣａＴｉＯ₃、ＭｇＴｉＯ₃、ＫＮｂＯ₃、ＮａＴｉＯ₃、ＫＴａＯ₃、ＲｂＴａＯ₃、（Ｎａ_1/2Ｂｉ_1/2）ＴｉＯ₃、Ｐｂ（Ｍｇ_1/2Ｗ_1/2）Ｏ₃、（Ｋ_1/2Ｂｉ_1/2）ＴｉＯ₃などが挙げられ、要求されるコンデンサの静電容量その他に応じて適宜選択すればよい。
【０１２９】
また、外部接続部１４には、Ｃｕを使用したが、素子本体１５の材質等との適合性を考慮して選択すれば良く、例えば、Ｐｄ、Ｐｔ、Ａｇ、Ａｇ−Ｐｔ、Ａｇ−Ｐｄ、Ａｕ、Ｎｉ等が挙げられる。
さらに、高誘電体セラミックを主成分とする誘電体層や Ａｇ−Ｐｄ等から成る電極層と、樹脂やＣｕメッキ、Ｎｉメッキ等から成るビア導体や配線層とを複合させてコンデンサとして構成したものを用いることもできる。
【図面の簡単な説明】
【図１】 本発明の一実施例の配線基板の構成を示す説明図である。
【図２】 コンデンサ素子の構成を示す説明図である。
【図３】 配線基板の製造方法を示す説明図である。
【図４】 コンデンサ素子の他の構成例を示す説明図である。
【図５】 本発明の他の実施例の配線基板の構成を示す図である。
【図６】 図５の構成を有する配線基板の製造方法を示す説明図である。
【図７】 本発明の他の実施例の配線基板の構成を示す図である。
【図８】 配線基板本体の変形例を説明する図である。
【図９】 変形例の配線基板本体の製造方法を示す図である。
【図１０】 配線基板本体の別の変形例を示す図である。
【符号の説明】
１…配線基板
３，３０３，４０３…配線基板本体
３ａ…第１主面 ３ｂ…第２主面 ４…充填樹脂
５ａ，５ｂ…第１導体層（配線）
１３，２１３…コンデンサ素子（電子部品）
１４，２１４…外部接続部
１５，２１５…素子本体（電子部品本体）
２１，３２１，４２１…貫通孔
２１ａ…開口部
２３…シート材 ２４…粘着剤
３０，２３０…外部電極層
３１，２３１…外部接続層
１０５ａ，１０５ｂ…第２導体層（配線）
１１１…フリップチップパッド（配線）
１１５，１１７…フィルドビア（配線）[0001]
BACKGROUND OF THE INVENTION
  The present invention provides a wiring board incorporating electronic components.PlankManufacturing methodTo the lawRelated.
[0002]
[Prior art]
Conventionally, a capacitor element is provided on a wiring board on which an integrated circuit element (hereinafter referred to as an “IC chip”) is mounted in order to reduce switching noise of the IC chip and stabilize the operation power supply voltage. Has been done. However, when the capacitor element is provided on the wiring board, the longer the wiring length between the IC chip and the capacitor element is, the more the inductance component of the wiring increases. It is desirable to provide as close to the IC chip as possible.
[0003]
[Problems to be solved by the invention]
In view of this, the inventors have considered that a capacitor element is built in a wiring board main body that is a skeleton of the wiring board. Specifically, a capacitor element housing portion (through hole or recess) is provided in the wiring board body, and the capacitor element is placed therein and filled with a filling resin. At this time, it is conceivable that the external connection part of the capacitor element (the conductor part for electrically connecting the capacitor element to the wiring) is also buried in the filling resin. To be exposed.
[0004]
In order to expose the external connection portion to the outside of the filling resin, a method of making a hole in the filling resin after curing with a laser or a drill can be considered. However, since the electronic components that can be incorporated in the wiring board main body are small, it is not easy to find the position of the external connection portion (that is, the position where the hole should be opened by the laser).
[0005]
The above problem is not limited to the capacitor element, but also applies when various electronic components are built in the wiring board.
The present invention has been made in view of these problems, and allows external connection portions of electronic components housed in a state of being fixed with a filling resin in a wiring board body to be easily exposed to the outside of the filling resin. The purpose is to.
[0017]
[Means for Solving the Problems and Effects of the Invention]
  Made to solve the above problemsClaim1The manufacturing method of the described wiring board is as follows:
  A plate shape having a first main surface and a second main surface;Provided with an electronic component body and an external connection for conducting the electronic component body and the outsideHas an accommodating part that can accommodate electronic componentsAnd having a surface conductor layer on at least one of the main surfaces.Wiring board bodyAgainst thatIn the containment sectionSaidAn arrangement process of arranging electronic components;
  A fixing step of fixing the electronic component in the housing portion by filling and curing a filling resin in the housing portion in which the electronic component is housed; and
  A polishing step of exposing the external connection portion of the electronic component on the first main surface side by polishing the filled resin cured in the fixing step;
  Forming a wiring to be connected to the external connection portion exposed on the first main surface side above the first main surface; and
  A method of manufacturing a wiring board having
  The external connection part of the electronic component is constituted by an external electrode layer formed by printing and baking on the surface of the electronic component main body, and an external connection layer formed so as to cover the external electrode layer by plating,
  In the arranging step, the electronic component is placed so that the upper end of the external connection portion is located above the first main surface and the upper end of the electronic component body is located below the first main surface. Arranged in the accommodating partAnd
In the polishing step, the height of the surface of the surface conductor layer and the surface of the filling resin is aligned by the polishing,
In the wiring formation step, an interlayer insulating layer and a conductor layer are alternately formed, and the conductor layer formed on the interlayer insulating layer is electrically connected to the external connection portion through a via.It is characterized by doing.
[0018]
  Such claims1According to the described method for manufacturing a wiring board, the electronic component is disposed so that the upper end of the external connection portion is on the upper side of the first main surface. Therefore, the upper end of the external connection portion is buried in the filling resin. However, it is possible to easily expose the external connection portion to the first main surface side by polishing the filling resin. In addition, since the upper end of the electronic component main body is located below the first main surface, the electronic component main body is less likely to be damaged by being scraped when the filling resin is polished on the first main surface side.
  Here, “upper side” indicates the outer side direction of the main surface of the wiring board, and “lower side” indicates the inner side direction of the wiring board opposite to the outer side direction.
[0019]
  Here, if there is little difference in height between the upper end of the external connection part and the upper end of the electronic component body, ElectricThere is also a possibility that the protection of the child component body is incomplete.
  Therefore, as an electronic component to be arranged in the housing portion, the claim2As described above, it is preferable to use an electronic component in which the external connection portion is formed to be 30 μm to 100 μm high from the electronic component main body. Then, as will be understood from the experiment described later, it is possible to prevent the electronic component main body from being accidentally shaved or the filling resin covering the electronic component main body from being peeled off or cracked. Further, in the arranging step, the electronic component may be arranged so that the upper end of the external connection portion is located above the first main surface and the upper end of the electronic component main body is located below the first main surface. It becomes easy.
[0020]
  Next claim3The wiring board manufacturing method described above is characterized in that, in the polishing step, the filling resin is polished with # 320 or more polishing cloth (specified in JIS R6004).
  That is, if the filling resin is polished with a polishing cloth having a count of # 320 or more (fineness of the eye. The higher the count, the finer the eye (as defined in JIS R6001)), The surface of the wiring board body (in advance on the first main surfacesurfaceWhen a conductor layer is formedOn the surfaceThe surface of the conductor layer is not easily scratched. Therefore, wiring formation (for example, wiring formation by a build-up method) can be performed without hindrance.
[0021]
  Next claim4In the wiring board manufacturing method described above, in the polishing step, the filling resin is polished with a polishing cloth of # 320 or more and # 600 or less.
  That is, if the filled resin is polished using a polishing cloth of # 320 or more and # 600 or less,1In addition to the effect of the present invention, as described later, the surface (first main surface) of the wiring board main body is previouslysurfaceWhen a conductor layer is formedOn the surfaceLess likely to cause stripping of the conductor layer.
[0022]
The filler resin is preferably mixed with a filler (for example, SiO2) having a smaller thermal expansion coefficient than that of the filler resin (becomes a composite material containing the resin). By doing so, it is possible to accurately control the thermal expansion coefficient as a composite of the filling resin and the filler. As a result, for example, it becomes easy to match the thermal expansion coefficient between a wiring board (conductor layer) formed of Cu or the like, or an IC chip formed of Si or the like and the wiring board, and is configured on the wiring board. It is possible to prevent the wiring pattern from being peeled off, and to improve the reliability with respect to heat.
[0023]
In particular, the filler resin may contain an inorganic filler as a component that is difficult to dissolve in the oxidizing agent. In some cases, the surface of the filling resin is roughened with an oxidizing agent in order to improve the adhesion to the wiring pattern or the electronic component. Therefore, when an inorganic filler is included as a component that is difficult to dissolve in the oxidizing agent, the coefficient of thermal expansion can be adjusted, and the inorganic filler functions as an aggregate after curing of the filling resin, so that after the roughening treatment It is possible to prevent the shape of the filled resin from collapsing more than necessary.
[0024]
The inorganic filler that does not substantially dissolve in the oxidizing agent is not particularly limited, but crystalline silica, fused silica, alumina, silicon nitride, and the like are preferable, and the thermal expansion coefficient of the filled resin can be effectively reduced. These inorganic fillers are added as a filler so as to have a high filling rate, and the thermal expansion coefficient of the filled resin is 40 ppm / ° C. or less (preferably 30 ppm / ° C. or less, more preferably 25 ppm / ° C. or less, more preferably 20 ppm / The lower limit value is 10 ppm / ° C. or more), thereby reducing the stress concentration caused by the difference in thermal expansion coefficient between the embedded electronic component and the mounted semiconductor element. Can do.
[0025]
The shape of the inorganic filler is preferably substantially spherical in order to increase the fluidity and filling rate of the filled resin. In particular, silica-based inorganic fillers are preferable because spherical particles can be easily obtained. To further improve the low viscosity and high filling rate of the filled resin, it is preferable to add two or more kinds of inorganic fillers having different particle shapes.
[0026]
Regarding the filler diameter of the inorganic filler, it is necessary to use a filler having a coarse diameter of 50 μm or less because the filled resin needs to easily flow into the gaps between the electrodes of the electronic component. The preferable range of the particle diameter is preferably 30 μm or less, more preferably 20 μm or less, and further 10 μm or less. When it exceeds 50 μm, the filler is easily clogged in the gap between the electrodes of the electronic component, and a portion where the thermal expansion coefficient is extremely different locally occurs due to poor filling of the filling resin. Further, when polishing to flatten the surface, the filler is grain-separated and large concave portions are generated, which prevents the formation of fine wiring by subsequent plating. The lower limit of the filler diameter is preferably 0.1 μm or more. If it is finer than this, it becomes difficult to ensure the fluidity of the filled resin. Preferably it is 0.3 μm or more, more preferably 0.5 μm or more. In order to achieve low viscosity and high filling of the filled resin, it is preferable to widen the particle size distribution.
[0027]
The surface of the inorganic filler may be surface treated with a coupling agent as necessary. This is because the wettability of the inorganic filler with the resin component is improved, and the fluidity of the filled resin can be improved. As the type of coupling agent, silane, titanium, aluminum and the like are used.
[0028]
As the component that does not substantially dissolve in the oxidizer, other modifiers such as a curing accelerator, silicone oil, reactive silicone gel, reactive diluent, antifoaming agent, and the like can be used.
When the thermosetting resin is included in the filling resin, it is necessary to add a curing agent. There are no particular restrictions on the type of curing agent, but imidazole, amine, acid anhydride, novolak resin, and the like may be used. In particular, when an epoxy resin is used as the thermosetting resin, the use of a liquid curing agent such as imidazole, amine or acid anhydride makes it easy to lower the viscosity of the filling resin. May be effective when adding.
[0029]
The filling resin is preferably roughened at least at the contact interface with the wiring. This is because the unevenness on the roughened surface has an anchor effect that improves the adhesion with the wiring formed by electroless plating. The roughened surface is preferably adjusted so that the surface roughness Rz is 0.1 to 15 μm. Preferably it is 0.5-10 micrometers, More preferably, it is 1-8 micrometers, More preferably, it is 3-7 micrometers, Especially 5-7 micrometers. It is preferable that the wiring substantially bites into the fine irregularities on the roughened surface. This is because if there are fine gaps or inadequate contact portions where the wiring does not substantially bite into the unevenness, wiring blisters are likely to occur in the reliability test.
[0030]
Inclusion of the inorganic filler in the filling resin is significant in adjusting the surface shape (unevenness) after the roughening of the filling resin. That is, the filling resin contains at least one kind of inorganic filler, and the content of the inorganic filler is in the range of 35 to 65% by volume (preferably 40 to 60% by volume, more preferably 40 to 50% by volume). %). By adjusting the ten-point average roughness Rz of the unevenness formed by the interface between the filling resin and the wiring layer to be within a predetermined range, and by regulating the content of the inorganic filler to be within the predetermined range, the adhesion of the wiring layer The anchor effect necessary to obtain the properties can be obtained more effectively, and the shape of the filled resin after the roughening treatment is maintained, so that potential defects such as excessively large vacancies are formed under the wiring layer. There is an advantage that generation can be suppressed.
[0031]
And in particular, a filling resin containing a thermosetting resin, its curing agent and at least one inorganic filler, wherein the thermosetting resin is at least one selected from bisphenol epoxy resin, naphthalene type epoxy resin and phenol novolac resin It is good to use filling resin whose content of the inorganic filler is 35-65 volume% and whose hardening agent is an acid anhydride hardening agent. This is because the adhesion of the wiring layer to the filled resin can be improved and high reliability can be obtained in reliability tests such as a thermal shock test and a water resistance test.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
Fig.1 (a) is a figure explaining the internal structure of the wiring board 1 manufactured by the method of an Example. In addition, the wiring board 1 of a present Example is a multi-piece wiring board (about 330 mm x 330 mm length and width) which becomes a plurality of circuit boards (about 40 mm x 40 mm) by dividing.
[0039]
  As shown in FIG. 1A, in this wiring board 1, both front and back surfaces (first main surface) of a wiring board body 3 which is an insulating board made of a glass-epoxy resin composite material having a thickness of about 0.8 mm. The first conductor layer having a thickness of about 25 μm is formed on the surface 3a and the second main surface 3b).(Surface conductor layer)5a and 5b are formed.
[0040]
The wiring board main body 3 is formed with a through hole 11 having a diameter of about 250 μm and plated on the inner wall of the through hole 9 penetrating from one of the main surfaces 3a, 3b to the other. By the through hole 11, the first conductor layer 5a on the first main surface 3a and the first conductor layer 5b on the second main surface 3b are connected to each other. The through hole 11 is filled with resin.
[0041]
Further, a through hole 21 (approximately 12 mm × 12 mm) is formed in the wiring board body 3 as an “accommodating portion” for placing electronic components, and a plurality of capacitor elements 13 (approximately 3 as electronic components) are formed therein. .2 mm × 1.6 mm × 0.7 mm). The capacitor element 13 is made of BaTiO_ThreeThe main body is composed of an element main body (electronic component main body) 15 made of a high-dielectric ceramic whose main component is Cu, an external connection portion 14 made of Cu, and an internal electrode layer (not shown in FIG. 1) made of Ni.
[0042]
Inside the through hole 21, the capacitor element 13 is fixed by the cured filling resin 4. The capacitor element 13 is for suppressing switching noise generated in the IC chip 16 to be provided on the wiring board 1 and stabilizing the operation power supply voltage to be supplied to the IC chip 16. .
[0043]
On the first conductor layers 5a and 5b, first interlayer insulating layers 103a and 103b (thickness of about 30 μm) are stacked, and on the first interlayer insulating layers 103a and 103b, the second conductors are stacked. Layers 105a and 105b (thickness of about 15 μm, width of about 25 μm) are formed. That is, the first conductor layer 5a (5b) and the second conductor layer 105a (105b) are stacked with the first interlayer insulating layer 103a (103b) interposed therebetween. The first conductor layer 5a (5b) and the second conductor layer 105a (105b) are filled vias 104a (104b) and 115a (115b) formed in the first interlayer insulating layer 103a (103b) and having an opening diameter of about 50 μm. Connected by. The filled vias 104a (104b) and 115a (115b) correspond to “via-hole conductors” in the claims.
[0044]
Second interlayer insulating layers 107a and 107b are further stacked on the second conductor layers 105a and 105b. Among these, a large number of flip chip pads 111 are formed on the second interlayer insulating layer 107a on the first main surface 3a side in order to connect the IC chip 16 indicated by the broken line and the wiring of the wiring board 1, and each flip chip is formed. A substantially hemispherical flip chip bump 112 made of high-temperature solder is formed on the pad 111. A solder for preventing the solder from flowing around the flip chip pad 111 when the flip chip bump 112 is formed on the second interlayer insulating layer 107a on the first main surface 3a side. A resist layer 109a (having a thickness of about 20 μm) is formed.
[0045]
On the other hand, on the second interlayer insulating layer 107b on the second main surface side, a large number of LGA pads 113 for connecting to the wiring of another wiring board such as a mother board and the wiring of the wiring board 1 are formed. . A solder resist layer 109b is also formed around the LGA pad 113 on the second interlayer insulating layer 107b on the second main surface 3b side.
[0046]
On the first main surface 3a side, the second conductor layer 105a and the flip chip pad 111 are connected to each other by a filled via 117a formed in the second interlayer insulating layer 107a. On the second main surface 3b side, the second conductor layer 105b and the LGA pad 113 are connected to each other via a filled via 117b formed in the second interlayer insulating layer 107b. Thus, by using filled vias for interlayer connection, the external connection portion 14 of the capacitor element and the flip chip pad 111 can be connected in a straight line (that is, a stacked via can be formed). Therefore, the IC chip 16 and the capacitor element 13 can be connected with a short distance, and the electrical characteristics can be improved.
[0047]
The wiring substrate 1 is divided by tiling processing or the like after passing through the following steps, and becomes a plurality of circuit substrates.
In this embodiment, the external connection portion 14 includes an external electrode layer 30 formed of Cu on a part of the surface of the element body 15 and an external electrode formed of Cu so as to cover the external electrode layer 30. It is composed of two conductor layers with the connection layer 31. That is, the external connection layer 31 constitutes the outermost layer of the conductor layers constituting the external connection portion 14. The external connection layer 31 constitutes the upper end portion 14 a and the lower end portion 14 b of the external connection portion 14.
[0048]
The first conductor layer 5a is also formed of Cu. In this way, the external connection portion 14 (external electrode layer 30 and external connection layer 31) of the electronic component (capacitor element 13) and the wiring of the wiring board 1 are formed of the same material (that is, Cu), so that the IC chip Thermal stresses that are likely to occur during solder reflow can be relaxed, and the possibility of disconnection can be reduced.
[0049]
The external connection portion 14 is formed such that its upper end (indicated by A1 in FIG. 1B) protrudes about 50 μm higher than the upper end (indicated by C1) of the element body 15. The upper end (A1) of the external connection portion 14 is located on the upper side with the first main surface 3a of the wiring board body 3 as a reference plane (indicated by B1), and the upper end (indicated by C1) of the element body 15. Is located on the lower side with the first main surface 3a as the reference surface (B1).
[0050]
Further, the external connection portion 14 is formed so that the lower end (indicated by A2 in FIG. 1B) also protrudes higher by about 45 μm from the lower end (indicated by C2) of the element body 15. The lower end (A2) of the external connection portion 14 is positioned on the lower side with the second main surface 3b as a reference surface (indicated by B2), and the lower end (indicated by C2) of the element body 15 is the second main surface 3b. The surface 3b is positioned above the reference surface (B2).
[0051]
The external connection portion 14 is formed as shown in FIG.
FIG. 2A is a diagram showing a known capacitor element, and an internal electrode 33 mainly composed of Ni is provided inside the element body 15. Specifically, of the two external electrode layers 30, a group of internal electrodes 33 connected to one external electrode layer 30 and a group of internal electrodes 33 connected to another external electrode layer 30 are BaTiO3._ThreeAre stacked alternately with a high dielectric ceramic therebetween.
[0052]
Such a capacitor element is configured by stacking a large number of Ni printed on a high dielectric ceramic green sheet, press-bonding them, firing them, and printing and baking the external electrode layer 30.
Thus, the external electrode layer 30 connected to the internal electrode 33 can be directly connected to an external wiring, but its thickness is thin (about 10 μm in this embodiment). Therefore, when the external connection portion 14 is constituted only by the external electrode layer 30, the upper end (A1) is made higher than the upper end surface (B1) of the first main surface 3a, and the upper end (C1) of the element body 15 is made the first main surface It is difficult to make it lower than the upper end surface (B1) of the surface 3a.
[0053]
Therefore, in this embodiment, as shown in FIG. 2B, an external connection layer 31 as a conductor layer is further formed on the external electrode layer 30.
The external connection layer 31 is formed on the surface of the external electrode layer 30 by barrel plating. Specifically, after the surface of the capacitor element (including the external electrode layer 30) shown in FIG. 2A is acid-activated at room temperature (about 20 ° C.) for about 60 seconds and washed twice with water. This is acid soaked at room temperature (about 20 ° C.) for about 15 seconds, and further washed twice with water. Thereafter, predetermined conditions (25 ° C., 2 A / dm²4 hours), a Cu layer having a thickness of about 70 μm (that is, the external connection layer 31) was formed on the surface of the external electrode layer 30 by electrolytic plating (copper sulfate plating), and was washed twice with water. Then, it is dried at 80 ° C. for about 1 hour.
[0054]
In this way, the external connection layer 31 made of Cu is formed. As a result, the external connection portion 14 protrudes from the element body 15 by about 50 μm at the upper end 14a and the lower end 14b.
In electrolytic plating, Fe spheres are used as media, but various methods such as using resin balls with Cu plating on the surface can be used.
[0055]
Now, how to manufacture the wiring board 1 incorporating the capacitor element 13 having the above configuration will be described with reference to FIG. FIG. 3 shows an enlarged view of the vicinity of one through hole 21.
As shown to Fig.3 (a), it is preferable to use what was previously comprised as a part of copper clad laminated board as the wiring board main body 3. FIG. The copper-clad laminate is obtained by placing copper foil on both surfaces of a resin-made insulating substrate, and laminating conductor layers 20a and 20b made of copper on the insulating substrate by heating and pressing. Note that an insulating substrate on which such conductor layers 20a and 20b are not stacked may be used as the wiring board body 3.
[0056]
A large number of through holes 9 for forming the through holes 11 are formed in the wiring board body 3 (for example, by drilling), and through holes 21 for arranging the capacitor elements 13 are formed (for example by punching). To do. The through-hole 9 and the through-hole 21 can be reduced in diameter if they are drilled with a laser (CO2, YAG, excimer, etc.). In addition to that shown in FIG. 1A, a large number of through holes 21 are formed in the wiring board 1.
[0057]
Next, as shown in FIG. 3B, one of the openings (opening 21a on the second main surface 3b side) of the through hole 21 for arranging the electronic component is provided, and a silicon-based adhesive 24 is provided on one side. Cover with a sheet material 23 made of polyimide. At that time, the surface 23 a having the adhesive 24 is directed toward the wiring board body 3, and the sheet material 23 is attached to the wiring board body 3.
[0058]
At this time, the adhesive 24 is exposed inside the through hole 21. In addition, a large number of through holes 21 are formed in the wiring board 1, and these openings 21 a are covered with one sheet material 23.
After closing the through hole 21 with the sheet material 23, as shown in FIG. 3C, the capacitor element 13 is disposed inside the through hole 21 so as to adhere to the sheet material 23 through the adhesive 24. This corresponds to the “arrangement step” in the claims.
[0059]
At this time, the capacitor element 13 adheres to the sheet material 23 at the external connection portion 14, and a gap through which the filling resin 4 can flow is formed between the element body 15 and the sheet material 23. Arranged so that. The external connection portion 14 includes end portions 14a and 14b facing in opposite directions, and the end portions 14a and 14b are directed to the first main surface 3a side and the second main surface 3b side, respectively. Here, the end directed toward the first main surface 3a is the upper end portion 14a, and the end directed toward the second main surface 3b is the lower end portion 14b.
[0060]
Further, when the capacitor element 13 is disposed in the through hole 21, the position of the capacitor element 13 is adjusted as follows.
That is, the upper end (indicated by A1 in FIG. 3C) of the external connection portion 14 is positioned on the upper side with the first main surface 3a as the reference plane (indicated by B1), and the upper end of the element body 15 (indicated by C1). Is located on the lower side with the first main surface 3a as the reference surface (B1), and the lower end (indicated by A2) of the external connection portion 14 is on the lower side with the second main surface 3b as the reference surface (indicated by B2) Furthermore, the lower end (indicated by C2) of the element body 15 is located on the upper side with the second main surface 3b as the reference surface (B2). The capacitor element 13 is disposed so that such a positional relationship is formed.
[0061]
After the capacitor element 13 is placed inside the through hole 21 as described above, the filling resin 4 is injected into the through hole 21 as shown in FIG. 3D, and the filling resin 4 is cured. Let This corresponds to the “fixing step” in the claims.
As a result, the capacitor element 13 as an electronic component is embedded in the wiring board body 3. The filling resin 4 is also filled between the element body 15 of the capacitor element 13 and the sheet material 23. After injecting the filling resin 4 into the through hole 21 and before curing, bubbles are extracted from the filling resin 4 by vacuum defoaming.
[0062]
In order to cure the filling resin 4, various methods are conceivable depending on the type of the filling resin 4. In this embodiment, a thermosetting epoxy resin is used as the filling resin 4 and is cured (so-called curing) by heating and drying. Specifically, curing is performed by maintaining the filling resin 4 filled in the through-hole 21 at a temperature of 100 ° C. to 120 ° C. for about 1 hour to 3 hours.
[0063]
The filler resin 4 is preferably mixed with a filler having a smaller thermal expansion coefficient than that of the filler resin 4 (for example, SiO 2). By doing so, it is possible to accurately control the thermal expansion coefficient as a composite of the filling resin 4 and the filler. As a result, for example, it becomes easy to match the thermal expansion coefficient between the wiring board 1 made of, for example, wiring (conductor layer) made of Cu or the like, and the IC chip 16 made of Si or the like, and the wiring board 1. The reliability with respect to heat of the wiring comprised above can be improved.
[0064]
Further, even if the capacitor element 13 is placed at an accurate position on the surface of the sheet material 23, there is a possibility that the position is shifted or inclined by being pushed by the filling resin 4 to be injected thereafter. Then, it may be difficult to connect the external connection portion 14 of the capacitor element 13 and the wiring pattern.
[0065]
Therefore, in order to increase the accuracy of the position of the capacitor element 13, it is preferable to increase the adhesive strength of the sheet material 23. When a sheet material 23 having an adhesive strength of 8.83 N / 25 mm was used, peeling from the sheet material was confirmed in 7.1% pieces (eight capacitor elements 13 per piece). From this, it is considered desirable to use the sheet material 23 having an adhesive strength of 8.0 N / 25 mm or more. This adhesive strength is measured by a 180 ° peeling method (JIS Z0237). The unit [N / 25 mm] means a force measured using a sheet material having a width of 25 mm as a sample (the same applies hereinafter).
[0066]
Thus, if the adhesive force of the sheet | seat material 23 is high, when inject | pouring the filling resin 4 into the through-hole 21 in which the capacitor | condenser element 13 is arrange | positioned, the capacitor | condenser element 13 will become difficult to move and the precision of the position can be improved. .
The sheet material 23 is preferably one having high mechanical strength. This is because if the strength of the sheet material 23 is too low, there is a problem that the sheet material 23 is deformed when the capacitor element 13 is placed on the surface thereof and the capacitor element 13 is displaced. Specifically, as the sheet material 23, one having a tensile strength (JIS Z0237) of 100 N / 25 mm or more (more preferably 150 N / 25 mm or more) may be used.
[0067]
In order to form a gap through which the filling resin 4 can flow between the element body 15 (that is, the electronic component body) and the sheet material 23, the adhesive 24 on the surface of the sheet material 23 is used as the sheet material 23. It is better to use a material whose thickness is smaller than the height of the electrode (described later). For example, when the capacitor element 13 (that is, the electronic component) having an “electrode height” of 30 μm to 70 μm is built in, the thickness of the adhesive 24 needs to be less than 70 μm. When the thickness of the pressure-sensitive adhesive 24 is 70 μm or more, it becomes difficult to secure a gap between the element body 15 and the sheet material 23 through which the filling resin 4 can flow when the external connection portion 14 is buried in the pressure-sensitive adhesive 24. Because.
[0068]
Moreover, when the thickness of the adhesive 24 on the surface of the sheet material 23 is small, it is difficult to obtain a predetermined adhesive force. Therefore, in order to ensure a predetermined adhesive strength, the thickness of the adhesive 24 is desirably 15 μm or more. That is, as the sheet material 23, a material having a thickness of the adhesive 24 of 15 μm or more and less than 70 μm may be used.
[0069]
After the filling resin 4 is cured, the sheet material 23 is then removed from the external connection portion 14 of the capacitor element 13, the filling resin 4 and the wiring board body 3 (specifically, the conductor layer 20a), and then filled. The main surfaces 3a and 3b of the resin 4 and the wiring board main body 3 are polished by a belt sander (FIG. 3E). This corresponds to the “polishing step” in the claims.
[0070]
By polishing the filling resin 4 on the first main surface 3a side, the upper end portion 14a of the external connection portion 14 is exposed to the outside of the filling resin 4 from the first main surface 3a side. From the second main surface 3 b side, the lower end portion 14 b of the external connection portion 14 is exposed to the outside of the filling resin 4 by removing the sheet material 23. The element body 15 of the capacitor element 13 is in a state of being buried in the filling resin 4.
[0071]
Further, when the main surfaces 3a and 3b are polished, the filling resin 4 formed around the capacitor element 13 is flattened, and the heights of the surfaces of the conductor layers 20a and 20b and the filling resin 4 are increased. Are aligned. That is, the conductor layer 20a and the filling resin 4 are in the same plane on the first main surface 3a side, and the conductor layer 20b and the filling resin 4 are also in the same plane on the second main surface 3b side. As a result, it is possible to form a flat conductor layer and an interlayer insulating layer on both the main surfaces 3a and 3b by a known build-up method.
[0072]
When an insulating substrate on which the conductor layers 20a and 20b are not stacked is used as the wiring board body 3, the surfaces of the first main surface 3a and the second main surface 3b and the surface of the filling resin 4 are obtained as a result of polishing. The height is aligned. That is, the first main surface 3a and the filling resin 4 are on the same plane, and the second main surface 3b and the filling resin 4 are on the same plane.
[0073]
In addition, the polishing cloth used for polishing the filling resin 4 has a fineness of # 400, but it is preferable to use a polishing cloth with finer mesh than # 320 or # 320. In particular, it is more preferable to use abrasive cloth of # 320 or more and # 600 or less. The reason is as follows.
[0074]
That is, as shown in Table 1, when the filled resin 4 was ground with the # 120 and # 240 abrasive cloths, the conductor layers 20a and 20b were peeled off, and scratches were seen on the surfaces of the conductor layers 20a and 20b. It was. Further, when # 800 abrasive cloth was used, no scratches were seen on the conductor layers 20a and 20b, but some of the layers were peeled off. This is because, when the abrasive cloth paper becomes finer, the resin becomes difficult to scrape, but the metal part (Cu in this embodiment) is relatively scraped, and the conductor layer is peeled off. It is thought that it will end.
[0075]
[Table 1]

[0076]
In Table 1, ◯ indicates good and × indicates poor.
In this embodiment, a silicon-based adhesive is used as the adhesive 24 of the sheet material 23. This is based on the following experiment. Table 2 shows the ease of peeling from the cured filling resin 4 and the heat resistance of the sheet material (the presence or absence of deformation or alteration in an environment of 200 ° C.) for various combinations of the sheet material (base material) and the pressure-sensitive adhesive. The result of the investigation is shown. In this experiment, an epoxy resin was used as the filling resin 4 and a silica filler mixed therein was used.
[0077]
[Table 2]

[0078]
In Table 2, ◯ indicates good, x indicates poor, and-indicates unconfirmed.
As shown in Table 2, when the base material is polyester or polyimide, the sheet material 23 has excellent heat resistance and is not deformed or deteriorated. In addition, when the adhesive is silicon-based, It turns out that it is easy to peel off after hardening.
[0079]
In this embodiment, since polyimide is used as the base material of the sheet material 23 and the silicon-based adhesive 24 is used, the sheet material 23 is not deformed when the filling resin 4 is thermally cured. The position of the electronic component (capacitor element 13) arranged above is small, and the electronic component can be provided in the wiring board body 3 with high positional accuracy. Moreover, since it is easy to peel off the sheet | seat material 23 from the hardening filling resin 4, it can prevent that a part of sheet | seat material 23 becomes a residue and interferes with a subsequent buildup process.
[0080]
Now, after polishing each main surface 3a, 3b side as described above, as shown in FIG. 3 (f), formation of the through hole 11 and the first conductor on each main surface 3a, 3b. The layers 5a and 5b are formed.
The first conductor layers 5a and 5b are formed as follows. That is, the entire wiring board body 3 having the capacitor element 13 built in the through hole 21 is subjected to electroless plating with Cu, and further subjected to electrolytic plating with Cu, whereby the entire wiring board body 3 is subjected to panel plating. I do. Then, the first conductor layers 5a and 5b are formed by removing unnecessary portions of the conductor layer by etching.
[0081]
During panel plating, plating is also formed on the exposed portion of the external connection portion 14 of the capacitor element 13. That is, the external connection portion 14 is connected to the wiring (here, the first conductor layers 5a and 5b) of the wiring board 1 by plating. Moreover, the connection is realized simultaneously with the formation of the wiring.
[0082]
Thus, since the connection between the external connection portion 14 of the capacitor element 13 and the conductor layer is performed by plating, the following effects are obtained. That is, when the capacitor element 13 is mounted by solder, a predetermined area (for example, 460 μm × 900 μm) is required to form a receiving land for solder mounting, and there is a limitation in increasing the mounting density of the capacitor element 13. It becomes. On the other hand, when the connection between the external connection portion 14 of the capacitor element 13 and the conductor layer is performed by plating, it is not necessary to form a receiving land, and the area necessary for connection to the conductor layer in the external connection portion 14 Is small (for example, 300 μm × 100 μm), the capacitor element 13 can be mounted with high density.
[0083]
In addition, the external connection portion 14 of the capacitor element 13 and the conductor layer can be connected simultaneously with the formation of the wiring by plating, and the step of solder printing can be omitted, so that it can be mounted at a low cost. Further, damage to the capacitor element 13 due to solder reflow can be eliminated.
[0084]
Further, during the above-described panel plating, a plated layer is also formed on the inner peripheral surface of the through-hole 9, and then the through-hole 11 is formed by filling and hardening the resin inside the through-hole 9 (FIG. 3). (F)). Alternatively, the through-hole 9 may be formed in the wiring board body 3, the plating layer may be formed on the inner peripheral surface, the resin may be filled, the through-hole may be formed, and the capacitor element 13 may be similarly incorporated.
[0085]
After the formation of the first conductor layers 5a and 5b as described above, the filling resin 4, the first conductor layers 5a and 5b, the upper end portion 14a and the lower end portion 14b are formed on the first main surface 3a side and the second main surface 3b side. A photosensitive resin in the form of a film mainly composed of an epoxy resin is attached to the top. Then, by exposing and developing the photosensitive resin, via holes are formed at positions where the upper end portion 14a and the lower end portion 14b should be exposed, and the photosensitive resin is cured to form the first interlayer insulating layers 103a and 103b. To do. Note that the via hole may be formed using a laser or the like after the first interlayer insulating layers 103a and 103b are formed of non-photosensitive resin.
[0086]
Further, electroless plating and electrolytic plating are performed with Cu to fill the via holes formed in the first interlayer insulating layers 103a and 103b with a conductor, and panel plating is performed to form a plating layer. A dry film is pasted on the plated layer, exposed and developed to form an etching resist, and unnecessary portions of the plated layer are removed by etching. As a result, a wiring composed of the second conductor layers 105a and 105b is formed. For forming the conductor layer, a full additive method or a semi-additive method may be used in addition to the well-known subtractive method.
[0087]
Thereafter, similarly, second interlayer insulating layers 107a and 107b, filled vias 117a and 117b, and flip chip pad 111 (LGA pad 113) are formed in this order, and then solder resist layers 109a and 109b are formed. Then, a Ni—Au plating layer is formed on the flip chip pad 111 exposed from the solder resist layer 109a, and further, a solder paste is applied and reflowed to form a flip chip bump 112. The process of forming the first conductor layers 5a and 5b, the second conductor layers 105a and 105b, and the like corresponds to the “wiring forming process” in the claims. Part of the filled vias 117a and 117b is formed immediately above the filled vias 115a and 115b.
[0088]
As described above, the wiring substrate 1 having the structure shown in FIG. 1 is completed. On the surface of the LGA pad 113, a Ni—Au plating layer may be formed to prevent oxidation.
In the present embodiment, the upper end 14a and the lower end 14b of the external connection portion 14 have been described as being formed so as to protrude from the element body 15 by about 50 μm, but this is based on the test results by the inventors. . That is, when the height of the protrusion from the element body 15 (hereinafter referred to as “electrode height”) at the upper end 14a and the lower end 14b of the external connection portion 14 is changed and the wiring board is manufactured by the above-described process, The result shown in 3 was obtained.
[0089]
[Table 3]

[0090]
Table 3 shows the state of occurrence of defects after the polishing process when the samples (capacitor elements 13) having “electrode heights” of 10 μm, 15 μm, 30 μm, 60 μm, 100 μm, and 120 μm, respectively, The situation of occurrence of defects after the plating process for forming the conductor layers 5a and 5b is shown.
[0091]
The trouble after the polishing process is, for example, that the element body 15 is exposed to the outside of the filling resin 4 or is mistakenly polished, or the filling resin 4 covering the element body 15 is cracked. It is. In addition, the defect after the plating step is, for example, that the filling resin 4 covering the element body 15 is floated or dropped, or a short circuit between the electrodes (a short circuit between the external connection portions 14 of the same capacitor element 13, Or, a short circuit between the external connection portions 14 of different capacitor elements 13 may occur.
[0092]
As shown in Table 3, when the “electrode height” was 10 μm, defects occurred at a rate of 88% by the polishing process. In addition, when the “electrode height” is 15 μm, defects occur at a rate of 62% by the polishing process, and 6% of those that have no problems after the polishing process are defective after the plating process. occured.
[0093]
Further, when the “electrode height” is 120 μm, a problem that a short circuit between the electrodes (particularly, between the external connection portions 14 of the same capacitor element 13) is likely to occur after the plating step.
In contrast to these results, for the samples having “electrode heights” of 30 μm, 60 μm, and 100 μm, the above-described problems were not observed after the polishing process or after the plating process. Therefore, the “electrode height” is set to 50 μm in this embodiment.
[0094]
According to the manufacturing method of the present embodiment described above, the following effects (1) to (9) are obtained.
(1) Since the upper end (namely, upper end part 14a) of the external connection part 14 exists above the 1st main surface 3a, the upper end of the external connection part 14 is hard to be embedded in the filling resin 4. Even if buried, the external connection portion 14 can be easily exposed to the first main surface 3a side by polishing the filling resin 4. Further, since the upper end of the element main body 15 is below the first main surface 3a, the element main body 15 is less likely to be scraped when the filling resin 4 is polished on the first main surface 3a side.
[0095]
(2) Since filled vias 115a and 115b (via-hole conductors) are formed immediately above the external connection portion 14, there is a connection path between an element provided on the surface of the wiring substrate such as an IC chip and the built-in electronic component. The electrical characteristics are improved by shortening and suppressing noise intrusion. Further, since filled vias 117a and 117b (via hole conductors) are formed immediately above filled vias 115a and 115b, the electrical characteristics are further improved.
[0096]
(3) Since the lower end (that is, the lower end portion 14b) of the external connection portion 14 is below the second main surface 3b, the upper end of the external connection portion 14 is not easily embedded in the filling resin 4. Even if buried, the external connection portion 14 can be easily exposed to the first main surface 3a side by polishing the filling resin 4. And since the upper end of the element main body 15 is on the upper side with respect to the first main surface 3a, when the second main surface 3b side of the filling resin 4 is polished, the element main body 15 is less likely to be scraped and damaged. .
[0097]
(4) Since the filling resin 4 is polished using the # 400 polishing cloth, the surface of the wiring board body 3 and the conductor layers 20a and 20b are hardly scratched. Therefore, for example, the wiring formation such as a build-up method can be performed without any trouble.
(5) Since the filling resin 4 is polished using the # 400 polishing cloth, there is little possibility of causing the conductor layers 20a and 20b to peel off.
[0098]
(6) Since the external connection portion 14 is formed of a plurality of layers (two layers in the present embodiment), that is, the external electrode layer 30 and the external connection layer 31, the external connection portion 14 from the capacitor element body 15 can be easily formed. You can earn height.
(7) Since the external connection layer 31 (outermost layer) is formed by plating, the thickness can be easily adjusted.
[0099]
(8) The external electrode layer 30 and the external connection layer 31 are formed of the same material (Cu), and the internal wiring of the wiring board 1 such as the first wiring layers 5a, 5b, filled vias 105a, 105b,. Therefore, disconnection due to generation of thermal stress can be suppressed.
[0100]
(9) Since the “electrode height” is sufficiently large, the element body 15 is not polished and damaged, and the portion of the filling resin 4 covering the element body 15 is not cracked or peeled off. Further, when the electronic component 13 is disposed on the sheet material 23, a sufficiently large gap for the filling resin 4 to flow between the element body 15 and the sheet material 23 can be formed. It is possible to prevent a portion that is not covered with the filling resin 4 from occurring. In this way, the element body 15 can be reliably protected, and the reliability of the electrical characteristics of the electronic component 13 can be improved.
[0101]
As mentioned above, although one Example of this invention was described, this invention is not a thing limited to the said Example, For example, the following various aspects also belong to the technical scope of this invention.
For example, in the above embodiment, the plurality of capacitor elements 13 are illustrated and described as being incorporated in each through hole 21, but the present invention is not limited thereto, and a single capacitor element 13 may be incorporated.
[0102]
Moreover, in the said Example, although the through-hole 21 was demonstrated as an example as an accommodating part, it is not restricted to this, This invention is applicable also when accommodating an electronic component in a recessed part.
In the above embodiment, the external connection portion 14 of the capacitor element 13 is described as being formed by the two layers of the external electrode layer 30 and the external connection layer 31, but the present invention is not limited to this.
[0103]
For example, a configuration as shown in FIG. 4A may be used, and this can be configured as follows. First, the external electrode layer 230 is formed on the side surface of the element body 215 by printing Cu paste. However, at that time, it can be formed thick on the side surface of the element body 215, but a sufficient thickness (that is, the upper end in FIG. 4) (ie, the upper end in FIG. 4) to be connected to the wiring (for example, the first conductor layer 5 a) of the wiring substrate 1 , The height from the element body 215) may not be obtained. In such a case, as shown in FIG. 4 (b), for example, a Cu paste 232 is further adhered to the portion, and the thickness is raised to obtain a sufficient thickness. Thereafter, as described above with reference to FIG. 2, Ni plating is performed to form the external connection layer 231 (for example, about 2 μm). Thus, the upper end portion 214a of the external connection portion 214 is formed so as to protrude from the element body 215 by about 60 μm.
[0104]
The part to which the Cu paste is attached need not be at both the upper and lower ends, and may be only on one side as shown in FIG. That is, in the above-described embodiment, the external connection portion 14 is described as being formed so as to protrude sufficiently high from the element body 15 at the upper end 14a and the lower end 14b, but is not limited thereto.
[0105]
In the case of such a capacitor element 213, the process shown in FIG.
The wiring board body 3 to be used is the same as that shown in FIG. Then, as described with FIG. 3A, a large number of through holes 9 for forming the through holes 11 are formed in the wiring board main body 3 (for example, by drilling), and the capacitor elements 13 are arranged. The through hole 21 is formed (for example, by punching).
[0106]
And as shown to Fig.6 (a), one side of the opening part of the through-hole 21 for electronic component arrangement | positioning is covered with the sheet | seat material 23 which consists of a polyimide which has the silicon-type adhesive 24 on one side. In this figure, the wiring board body 3 is turned upside down and the opening on the first main surface 3a side is closed with the sheet material 23. At that time, similarly to the above, the surface 23a having the adhesive 24 is directed to the wiring board body 3 side, and the sheet material 23 is attached to the wiring board body 3 (specifically, the conductor layer 20a).
[0107]
After closing the through hole 21 with the sheet material 23 in this way, as shown in FIG. 6A, the capacitor element 213 is placed inside the through hole 21 so as to adhere to the sheet material 23 via the adhesive 24. Deploy.
At this time, the capacitor element 213 is turned upside down so as to adhere to the sheet material 23 at the upper end 214 a of the external connection portion 214, and the filling resin 4 can flow between the element body 215 and the sheet material 23. It arrange | positions so that a clearance gap may be formed. In addition, the upper end (indicated by A1 in FIG. 6A) of the external connection portion 14 is positioned below the first main surface 3a as the reference plane (indicated by B1), and the upper end of the element body 15 (indicated by C1). ) Arranges the capacitor element 213 so that the first main surface 3a is located on the upper side with the reference surface (B1).
[0108]
After the capacitor element 213 is disposed inside the through hole 21 as described above, the filling resin 4 is injected into the through hole 21 as shown in FIG. 6B, and the filling resin 4 is cured. Let As a result, the capacitor element 13 as an electronic component is embedded in the wiring board body 3. The filling resin 4 is also filled between the element body 215 of the capacitor element 213 and the sheet material 23. And after filling resin 4 to penetration hole 21, like the above-mentioned example, bubbles are extracted from filling resin 4 by vacuum defoaming, and filling resin 4 is hardened. The filling resin 4 may be the same as that in the above embodiment.
[0109]
After the filling resin 4 is cured, the sheet material 23 is then removed from the external connection portion 214, the filling resin 4 and the wiring board body 3 (specifically, the conductor layer 20a) of the capacitor element 213, and then the filling resin. 4 and the main surfaces 3a and 3b of the wiring board body 3 are polished by a belt sander (FIG. 6C).
[0110]
By removing the sheet material 23, the upper end portion 214 a of the external connection portion 214 is exposed to the outside of the filling resin 4 from the first main surface 3 a side. Further, the element body 215 of the capacitor element 213 is in a state of being buried in the filling resin 4.
Since the external connection portion 214 of the capacitor element 215 is shorter than the thickness of the wiring board body 3, as shown in FIG. 6C, the external connection portion 214b from the second main surface 3b side even after the polishing step. Is not exposed.
[0111]
Then, as shown in FIG. 6 (d), a hole 204 (a hole for forming a via) is formed in the filling resin 4 by irradiating a laser from the second main surface 3b side, and external connection is performed. The lower end portion 214 b of the portion 214 is exposed to the outside of the filling resin 4.
Then, as shown in FIG. 6E, the first conductor layers 5a and 5b are formed on the main surfaces 3a and 3b, and the through holes 11 are formed. This is the same as in the above embodiment, and during panel plating, the exposed portion of the external connection portion 14 of the capacitor element 213 is also plated, but at the same time, the hole 204 is filled with plating. The
[0112]
Since the steps after the formation of the first conductor layers 5a and 5b are the same as those in the above embodiment, the description thereof is omitted, but the wiring board having the configuration shown in FIG. 5 can be obtained as described above.
As shown in FIG. 7, for example, the external connection portion 14 may be configured so as to protrude from the element body 215 only at the end portion (upper end in FIG. 7) facing the mounting surface side of the IC chip 16. good. The wiring board having this structure can be obtained by a process excluding “drilling by laser on the second main surface 3b side” from the manufacturing process described with reference to FIG.
[0113]
In the above embodiment, the capacitor element 13 is built in the wiring board as the electronic component. However, the present invention is not limited to this, and the chip-like resistor, inductor, filter (SAW filter, LC filter, etc.), coupler Various electronic components such as passive components such as a diplexer and an antenna switch module and active components such as a transistor, a memory, a low noise amplifier (LNA), and an FET may be incorporated. Moreover, you may incorporate different types of electronic components in the same through-hole among these.
[0114]
In the description of the above embodiment, as shown in FIG. 3D, the through hole 21 is formed from the first main surface 3 a side (that is, the opening side where the sheet material 23 does not block the through hole 21). In the above description, the filling resin 4 is injected. However, depending on the relationship between the viscosity of the filling resin 4 and the gap in the through hole 21, the filling resin 4 may not sufficiently reach the second main surface 3 b side in the through hole 21. The gap in the through hole 21 is between the capacitor elements 13, between the capacitor element 13 and the inner wall of the through hole 21, between the element body 15 of the capacitor element 13, and the sheet material 23. Therefore, after the sheet material 23 is peeled off, the filling resin 4 may be injected into the through hole 21 also from the opening 21a side. If it does so, the filling resin 4 can be reliably filled into the through-hole 21 without a gap.
[0115]
Moreover, in the said Example, although the glass-epoxy resin composite material was used as a material of the wiring board main body 3, it considers heat resistance, mechanical strength, flexibility, ease of processing, etc. without being restricted to this. And select. Therefore, for example, a glass fiber-resin composite material that is a composite material of glass fibers such as glass woven fabric and glass nonwoven fabric and a resin such as epoxy resin, polyimide resin, and BT resin can be used. Further, a composite material of organic fiber and resin such as polyimide fiber, a resin-resin composite material in which a resin such as epoxy resin is impregnated with a fluororesin having a three-dimensional network structure such as PTFE having continuous pores can be used. .
[0116]
Further, as the wiring board main body, a multilayer board in which a conductor layer (conductor pattern) is incorporated may be used. For example, conductor layers 305a and 305b are formed inside the wiring board main body 303 of the wiring board shown in FIG. The wiring board main body 303 can be obtained, for example, by a procedure as shown in FIG.
[0117]
First, a copper clad laminate as shown in FIG. 9A is prepared. In this example, conductor layers 305a and 305b are formed by laminating copper on both surfaces of an insulating substrate 306 made of BT resin, FR-4, FR-5, or the like. The copper conductor layers 305a and 305b formed on both surfaces of the insulating substrate 306 are etched to form a required pattern (see FIG. 9B).
[0118]
Next, both surfaces of the copper clad laminate are roughened, and insulating materials 307a and 307b are laminated on both surfaces as shown in FIG. The insulating materials 307a and 307b may be a material different from or the same as the resin constituting the insulating substrate 306, and for example, various resins such as an epoxy resin can be used. In this way, the wiring board main body 303 having the conductor layers 305a and 305b inside can be obtained.
[0119]
Next, as shown in FIG. 9D, a hole 308 for forming a via is formed in the insulating materials 307a and 307b with a laser, or a through-hole through hole 309 for forming a through hole is formed with a laser. Form with a drill.
Next, as shown in FIG. 9 (e), a plating layer 312 made of Cu is formed on the surfaces of the insulating materials 307 a and 307 b, the inner surface of the hole 308, and the inner peripheral surface of the through-hole through-hole 309 by performing panel plating. Then, as shown in FIG. 9F, the inside of the through-hole through hole 309 is filled with a hole-filling resin 314 such as an epoxy resin containing a silica filler, and is cured. The hole filling resin 314 is polished so as to form substantially the same surface as the plating layer 312 on the surfaces of the insulating materials 307a and 307b.
[0120]
In order to incorporate the electronic component, as shown in FIG. 9G, an electronic component placement through hole 321 is formed, and the opening of the electronic component placement through hole 321 is closed with the sheet material 23. The electronic component can be built in the wiring board main body 303 and a build-up layer can be formed by the procedure described with reference to FIG.
[0121]
For example, as shown in FIG. 10, a wiring board body 403 having conductor layers 405a and 405b inside may be used in advance. In order to obtain a wiring board substantially similar to that shown in FIG. 8 using this, first, a through-hole through-hole 407 and a via-forming hole (not shown) are formed in the wiring board main body 403 shown in FIG. It forms (FIG.10 (b)). Next, a plating layer 409 is laminated on both surfaces of the wiring board main body 403 and the inner peripheral surface of the through-hole through hole 407 by panel plating (FIG. 10C), and a filling resin 411 is placed inside the through-hole through hole 407. Fill (FIG. 10 (d)). Further, an electronic component placement through hole 421 is formed (FIG. 10E). Thereafter, the opening of the electronic component placement through-hole 321 is closed with a sheet material, and the electronic component can be built in the wiring board main body 403 and a build-up layer can be formed by the procedure described with reference to FIG.
[0122]
As described above, when a wiring board body having a built-in conductor layer is used, the number of conductor layers to be laminated on the wiring board body can be reduced. For example, FIG. 1 shows a structure in which three conductor layers are laminated on both main surfaces of the wiring board body. On the other hand, when a wiring board body having a built-in conductor layer is used, As shown in FIG. 8, the number of conductor layers to be laminated on both main surfaces is reduced by two layers.
[0123]
Therefore, the conduction path between the electronic component and the IC chip can be shortened, and it is possible to reduce loop inductance, switching noise, crosstalk noise, etc., that is, improve the electrical characteristics of the wiring board. .
In addition, the through-hole through-hole penetrates the wiring board body, and the number of conductor layers to be laminated on both main surfaces of the wiring board body is two, so a stacked via is formed. There is no need to do it. Since the stacked via is not required, it is not necessary to form a filled via (via that is completely filled with a conductor), and a conformal via (via that is not completely filled with a conductor) is sufficient. The cost for forming can be suppressed.
[0124]
In FIG. 8, two conductor layers are stacked on both main surfaces of the wiring board main body 303, but the number of layers is not limited to this. Further, the wiring board main body 303 has been described as having two conductor layers 305a and 305b, but the number of layers is not limited thereto.
[0125]
In the above embodiment, the filler resin 4 is polished with the abrasive cloth paper. However, it is obvious that means other than the abrasive cloth paper may be used.
In the above embodiment, the first interlayer insulating layers 103a and 103b and the second interlayer insulating layers 107a and 107b are mainly composed of an epoxy resin. However, in consideration of heat resistance, pattern formability, etc. Just choose. For example, a resin-resin composite material in which a fluororesin having a three-dimensional network structure such as polyimide resin, BT resin, PPE resin, or PTFE having continuous pores is impregnated with a resin such as an epoxy resin can be used.
[0126]
In the above embodiment, the first conductor layers 5a and 5b and the second conductor layers 105a and 105b are formed by electroless Cu plating and electrolytic plating. However, the first conductor layers 5a and 5b are formed by other materials such as Ni and Ni-Au. Further, it may be formed by a technique such as applying a conductive resin without plating.
[0127]
In the above embodiment, a large number of flip chip pads 111 and flip chip bumps 112 are provided on the upper surface of the wiring substrate for connection to the IC chip 16. However, as an IC connection terminal, an appropriate form may be used in accordance with a terminal formed on an IC chip to be connected. In addition to a flip chip bump formed, only a flip chip pad or a wire is used. Examples include a bonding pad and a TAB connection pad. Further, Sn-Ag, Sn-Ag-Cu, Sn-Pb, Sn-Sb, Sn-Zn solder, etc. can be used for the solder of the flip chip bump.
[0128]
In the above embodiment, the element body 15 of the capacitor element 13 has a BaTiO._ThreeIs used, but is not limited to this material. For example, PbTiO_Three, PbZrO_ThreeTiO₂, SrTiO_Three, CaTiO_Three, MgTiO_Three, KNbO_ThreeNaTiO_Three, KTaO_Three, RbTaO_Three, (Na_1/2Bi_1/2) TiO_Three, Pb (Mg_1/2W_1/2) O_Three, (K_1/2Bi_1/2) TiO_ThreeAnd may be appropriately selected depending on the required capacitance of the capacitor and the like.
[0129]
Further, although Cu is used for the external connection portion 14, it may be selected in consideration of compatibility with the material of the element body 15, for example, Pd, Pt, Ag, Ag—Pt, Ag—Pd, Au, Ni, etc. are mentioned.
In addition, a capacitor composed of a dielectric layer composed mainly of high-dielectric ceramic, an electrode layer made of Ag-Pd, etc., and a via conductor or wiring layer made of resin, Cu plating, Ni plating, etc. Can also be used.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a configuration of a wiring board according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram showing a configuration of a capacitor element.
FIG. 3 is an explanatory view showing a method for manufacturing a wiring board.
FIG. 4 is an explanatory diagram showing another configuration example of the capacitor element.
FIG. 5 is a diagram showing a configuration of a wiring board according to another embodiment of the present invention.
6 is an explanatory view showing a method for manufacturing a wiring board having the configuration of FIG. 5;
FIG. 7 is a diagram showing a configuration of a wiring board according to another embodiment of the present invention.
FIG. 8 is a diagram for explaining a modification of the wiring board main body.
FIG. 9 is a diagram illustrating a method for manufacturing a wiring board main body according to a modification.
FIG. 10 is a view showing another modified example of the wiring board main body.
[Explanation of symbols]
1 ... Wiring board
3,303,403 ... Wiring board body
3a ... 1st main surface 3b ... 2nd main surface 4 ... Filling resin
5a, 5b ... 1st conductor layer (wiring)
13,213 ... Capacitor element (electronic component)
14, 214 ... external connection
15, 215 ... Element body (electronic component body)
21, 321, 421 ... through hole
21a ... opening
23 ... Sheet material 24 ... Adhesive
30, 230 ... External electrode layer
31,231 ... External connection layer
105a, 105b ... second conductor layer (wiring)
111 ... Flip chip pad (wiring)
115,117 ... Filled via (wiring)

Claims (4)

A plate shape having a first major surface and a second major surface, and having an accommodating portion capable of accommodating an electronic component having an external connection unit which performs conduction between the electronic component body and electronic component body and the outside, the to the wiring substrate main body having on at least one surface conductor layer on both main surface sides, a placement step of placing the electronic component on the housing part,
A fixing step of fixing the electronic component in the housing portion by filling and curing a filling resin in the housing portion in which the electronic component is housed; and
A polishing step of exposing the external connection portion of the electronic component on the first main surface side by polishing the filled resin cured in the fixing step;
Forming a wiring to be connected to the external connection portion exposed on the first main surface side above the first main surface; and
A method of manufacturing a wiring board having
The external connection part of the electronic component is constituted by an external electrode layer formed by printing and baking on the surface of the electronic component main body, and an external connection layer formed so as to cover the external electrode layer by plating,
In the arranging step, the electronic component is placed so that the upper end of the external connection portion is located above the first main surface and the upper end of the electronic component body is located below the first main surface. Arranged in the housing part ,
In the polishing step, the height of the surface of the surface conductor layer and the surface of the filling resin is aligned by the polishing,
In the wiring formation step, an interlayer insulating layer and a conductor layer are alternately formed, and the conductor layer formed on the interlayer insulating layer and the external connection portion are electrically connected through a via. A method for manufacturing a wiring board. Wherein in the disposing step, the electronic component on which the external connection portion is formed higher the electronic component 30μm or more from the body 100μm or less, the manufacturing method of the wiring substrate according to claim 1, characterized in that disposed in the receptacle. 3. The method of manufacturing a wiring board according to claim 1, wherein in the polishing step, the filling resin is polished with a polishing cloth of # 320 or more. 3. The method of manufacturing a wiring board according to claim 1, wherein in the polishing step, the filling resin is polished with a polishing cloth of # 320 or more and # 600 or less.

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