JP2002118197A - Circuit board and semiconductor device using the same as well as its manufacturing method - Google Patents

Circuit board and semiconductor device using the same as well as its manufacturing method

Info

Publication number
JP2002118197A
JP2002118197A JP2000311721A JP2000311721A JP2002118197A JP 2002118197 A JP2002118197 A JP 2002118197A JP 2000311721 A JP2000311721 A JP 2000311721A JP 2000311721 A JP2000311721 A JP 2000311721A JP 2002118197 A JP2002118197 A JP 2002118197A
Authority
JP
Japan
Prior art keywords
wiring
elastic body
wiring board
semiconductor chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000311721A
Other languages
Japanese (ja)
Other versions
JP4035949B2 (en
Inventor
Tatsuya Otaka
達也 大高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP2000311721A priority Critical patent/JP4035949B2/en
Publication of JP2002118197A publication Critical patent/JP2002118197A/en
Application granted granted Critical
Publication of JP4035949B2 publication Critical patent/JP4035949B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

PROBLEM TO BE SOLVED: To simplify manufacturing steps in a semiconductor device obtained by flip-chip connecting a semiconductor chip onto a circuit board via an elastic material. SOLUTION: The circuit board comprises an insulating board, wirings provided on the surface of the base and its external connecting terminal. The board further comprises protruding conductors provided at prescribed positions of the base, and elastic materials (elastomers) provided on the wirings of the base and the terminal so as to expose the surfaces of the protrusions.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、配線テープ及びそ
れを用いた半導体装置、ならびにその製造方法に関し、
特に、半導体チップを、配線テープ上に弾性体(エラス
トマ)を介在させてフリップチップ接合する半導体装置
に適用して有効な技術に関するものである。
The present invention relates to a wiring tape, a semiconductor device using the same, and a method of manufacturing the same.
In particular, the present invention relates to a technique that is effective when applied to a semiconductor device in which a semiconductor chip is flip-chip bonded with an elastic body (elastomer) interposed on a wiring tape.

【0002】[0002]

【従来の技術】従来、配線及びその外部接続端子が設け
られた配線基板上に半導体チップを搭載し、前記半導体
チップの外部電極と配線基板の配線を接続する方法の一
つとしてフリップチップ接合があげられる。
2. Description of the Related Art Conventionally, flip chip bonding has been used as one of the methods for mounting a semiconductor chip on a wiring board provided with wiring and external connection terminals thereof and connecting external electrodes of the semiconductor chip to wiring on the wiring board. can give.

【0003】前記フリップチップ接合を用いて製造され
る半導体装置は、例えば、図10(a)及び図10
(b)に示すように、絶縁性基板101に配線102A
及びその外部接続端子102Bが設けられた配線基板1
上に、例えば二つの弾性体(エラストマ)2A,2Bが
設けられ、前記弾性体2A,2B上に半導体チップ3が
設けられている。前記半導体チップ3は、図10(b)
に示すように、その外部電極形成面が前記弾性体2A,
2Bと向かい合うように設けられ、前記外部電極301
と前記配線基板1の配線102Aが突起導体(バンプ)
5により接合されている。このとき、前記弾性体2A,
2Bは、前記半導体チップ3の外部電極301が形成さ
れた領域をはさんだ両側に設けられており、前記突起導
体(バンプ)5の周辺にできる隙間には、レジンなどの
封止樹脂(アンダーフィル)13を流し込んで前記突起
導体(バンプ)5の周辺を封止している。前記弾性体2
A,2Bは、前記配線基板1と半導体チップ3とを接着
する接着剤であるとともに、前記配線基板1と半導体チ
ップ3の熱膨張係数の違いにより生じる熱応力を緩和す
るための緩和材としても機能するものを用いており、例
えば、熱硬化性のエポキシ系樹脂などが用いられる。ま
た、前記配線基板1の外部接続端子102Bは、前記テ
ープ状基材101に設けられたビア孔に充填されたはん
だビアを介して、はんだボールなどのボール端子4と接
続されている。
A semiconductor device manufactured by using the flip chip bonding is, for example, shown in FIGS.
As shown in (b), the wiring 102A is formed on the insulating substrate 101.
And wiring board 1 provided with external connection terminals 102B
For example, two elastic bodies (elastomers) 2A and 2B are provided thereon, and the semiconductor chip 3 is provided on the elastic bodies 2A and 2B. The semiconductor chip 3 is shown in FIG.
As shown in FIG.
2B, the external electrode 301
And the wiring 102A of the wiring substrate 1 is a projecting conductor (bump).
5 are joined. At this time, the elastic body 2A,
2B are provided on both sides of the region of the semiconductor chip 3 where the external electrodes 301 are formed, and a gap formed around the projecting conductor (bump) 5 is provided with a sealing resin such as resin (underfill). 13) is poured to seal the periphery of the projecting conductor (bump) 5. The elastic body 2
A and 2B are adhesives for adhering the wiring board 1 and the semiconductor chip 3, and are also used as a relaxation material for relieving thermal stress caused by a difference in thermal expansion coefficient between the wiring board 1 and the semiconductor chip 3. A functional material is used, for example, a thermosetting epoxy resin or the like is used. The external connection terminals 102B of the wiring board 1 are connected to ball terminals 4 such as solder balls via solder vias filled in via holes provided in the tape-shaped base material 101.

【0004】前記フリップチップ接合された半導体装置
の製造方法は、まず、テープ状基材101に配線102
A及びその外部接続端子102B、前記外部接続端子1
02B部分のビア孔を形成した配線基板1を形成したの
ち、前記配線基板1の所定位置に弾性体(エラストマ)
2A,2Bを配置し、前記弾性体2A,2B上に半導体
チップ3を、その外部電極301が前記弾性体2A,2
Bと向かい合うように配置する。このとき、例えば、前
記外部電極301上に突起電極5が設けておき、前記突
起電極5と前記配線102Aが接するようにしておく。
そして、前記弾性体2A,2B及び突起電極5を加熱し
て、前記半導体チップ3と配線基板1を前記弾性体2
A,2Bにより接着するとともに、前記半導体チップ3
の外部電極301と配線基板1の配線102を前記突起
導体(バンプ)5により接続する。その後、前記突起導
体(バンプ)5を封止するために、図11に示すよう
に、樹脂注入用ノズル14を用いて、前記半導体チップ
3の側面方向から前記二つの弾性体2A,2B間にレジ
ン等の封止樹脂13を流し込む。前記封止樹脂13によ
りバンプ5を封止した後、前記配線基板1のビア孔上に
はんだボール等のボール端子4を載せて加熱し、部分的
に融解させて前記はんだボールと外部接続端子102B
を接続する。
In the method of manufacturing a semiconductor device bonded by flip-chip bonding, first, wiring 102
A and its external connection terminal 102B, the external connection terminal 1
After forming the wiring board 1 in which the via hole of the portion 02B is formed, an elastic body (elastomer) is provided at a predetermined position of the wiring board 1.
2A and 2B, the semiconductor chip 3 is placed on the elastic members 2A and 2B, and the external electrodes 301 are connected to the elastic members 2A and 2B.
It is arranged so as to face B. At this time, for example, the protruding electrode 5 is provided on the external electrode 301 so that the protruding electrode 5 and the wiring 102A are in contact with each other.
Then, the elastic members 2A and 2B and the protruding electrode 5 are heated to separate the semiconductor chip 3 and the wiring board 1 from each other.
A, 2B and the semiconductor chip 3
The external electrodes 301 and the wiring 102 of the wiring board 1 are connected by the projecting conductors (bumps) 5. Thereafter, in order to seal the projecting conductors (bumps) 5, as shown in FIG. 11, a resin injection nozzle 14 is used between the two elastic bodies 2 </ b> A and 2 </ b> B from the side of the semiconductor chip 3. A sealing resin 13 such as a resin is poured. After sealing the bump 5 with the sealing resin 13, the ball terminal 4 such as a solder ball is placed on the via hole of the wiring board 1, heated and partially melted, and the solder ball and the external connection terminal 102 </ b> B are melted.
Connect.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、前記従
来の技術では、前記弾性体2A,2Bを介して半導体チ
ップ3と配線基板1をフリップチップ接合する工程と、
前記突起導体(バンプ)2を封止する工程が別の工程で
あるため、製造工程が増え、製造コストが上昇するとい
う問題があった。
However, according to the conventional technique, a step of flip-chip bonding the semiconductor chip 3 and the wiring board 1 via the elastic bodies 2A and 2B,
Since the step of sealing the projecting conductor (bump) 2 is another step, there is a problem that the number of manufacturing steps increases and the manufacturing cost increases.

【0006】また、前記弾性体(エラストマ)2A,2
Bを介して半導体チップ3と配線基板1をフリップチッ
プ接合する工程の後に、前記弾性体2A,2B間に封止
樹脂13を流し込んで突起導体(バンプ)3を封止する
工程が行われているが、前記封止樹脂13を流し込むと
きに、図11に示すように、前記バンプ5間に封止樹脂
13が流れ込まずにボイド15ができてしまうことが多
い。前記ボイド15が生じると、その後の製造工程での
加熱処理、例えば、前記ボール端子4を接続するための
リフロー工程等で、前記ボイド15内の空気が加熱され
て膨張し、前記バンプ5が配線102Aあるいは外部電
極301から剥がれて接続不良になるという問題があっ
た。また、前記ボイド15の膨張により、前記封止樹脂
13と半導体チップ3あるいは配線基板1の接着面が剥
がれ、パッケージクラックの原因になるという問題があ
った。
Further, the elastic bodies (elastomers) 2A, 2
After the step of flip-chip bonding the semiconductor chip 3 and the wiring board 1 via B, a step of pouring a sealing resin 13 between the elastic bodies 2A and 2B to seal the projecting conductor (bump) 3 is performed. However, when the sealing resin 13 is poured, voids 15 are often formed without the sealing resin 13 flowing between the bumps 5 as shown in FIG. When the voids 15 are formed, the air in the voids 15 is heated and expanded in a heat treatment in a subsequent manufacturing process, for example, a reflow process for connecting the ball terminals 4, and the bumps 5 There is a problem that the connection is poor due to peeling off from the external electrode 102A or the external electrode 301. In addition, due to the expansion of the void 15, the adhesive surface between the sealing resin 13 and the semiconductor chip 3 or the wiring board 1 is peeled off, which causes a problem of causing a package crack.

【0007】本発明の目的は、配線基板上に、弾性体を
介して半導体チップをフリップチップ接合した半導体装
置において、製造工程を簡略化することが可能な技術を
提供することにある。
An object of the present invention is to provide a technique capable of simplifying a manufacturing process in a semiconductor device in which a semiconductor chip is flip-chip bonded on a wiring board via an elastic body.

【0008】本発明の他の目的は、配線基板上に、弾性
体を介して半導体チップをフリップチップ接合した半導
体装置において、半導体チップの外部電極と配線の接続
不良を低減することが可能な技術を提供することにあ
る。
Another object of the present invention is to provide a semiconductor device in which a semiconductor chip is flip-chip bonded on a wiring board via an elastic body, whereby a connection failure between external electrodes of the semiconductor chip and wiring can be reduced. Is to provide.

【0009】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面によって明ら
かになるであろう。
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【0010】[0010]

【課題を解決するための手段】本発明において開示され
る発明の概要を説明すれば、以下のとおりである。
The summary of the invention disclosed in the present invention is as follows.

【0011】(1)絶縁性基材と、前記基材の表面に設
けられた配線及びその外部接続端子とを備える配線基板
において、前記配線の所定位置に突起導体が設けられ、
前記絶縁性基材の配線及びその外部接続端子上に、前記
突起導体の表面が露出するように弾性体(エラストマ)
が設けられている配線基板である。
(1) In a wiring board including an insulating base material, wiring provided on the surface of the base material, and external connection terminals thereof, a projecting conductor is provided at a predetermined position of the wiring,
An elastic body (elastomer) such that the surface of the projecting conductor is exposed on the wiring of the insulating base material and the external connection terminals thereof.
Is provided on the wiring board.

【0012】前記(1)によれば、前記配線基板の配線
上に突起電極を設け、前記突起電極が露出するように弾
性体(エラストマ)を設けておくことで、前記配線基板
上に半導体チップを接着して、前記半導体チップの外部
電極と配線を接続する際の製造工程を簡略化させること
ができる。
According to the above (1), by providing a projecting electrode on the wiring of the wiring board and providing an elastic body (elastomer) so that the projecting electrode is exposed, the semiconductor chip is provided on the wiring board. To simplify the manufacturing process when connecting the external electrodes of the semiconductor chip and the wiring.

【0013】(2)絶縁性基材の表面に配線及びその外
部接続端子が設けられ、前記配線の所定位置に突起導体
が設けられ、前記絶縁性基材の配線及びその外部接続端
子上に、前記突起導体の表面が露出するように弾性体
(エラストマ)が設けられた配線基板を設け、前記配線
基板の弾性体上に、半導体チップをその回路形成面が前
記弾性体と向かい合うように設け、前記半導体チップの
回路形成面に設けられた外部電極と前記配線基板の配線
が、前記弾性体(エラストマ)で密封されて接続されて
いる半導体装置である。
(2) Wiring and its external connection terminals are provided on the surface of the insulating base material, projecting conductors are provided at predetermined positions of the wiring, and the wiring of the insulating base material and its external connection terminals are provided on the wiring. Providing a wiring board provided with an elastic body (elastomer) so that the surface of the projecting conductor is exposed, and providing a semiconductor chip on the elastic body of the wiring board so that a circuit forming surface thereof faces the elastic body; The semiconductor device is a semiconductor device in which external electrodes provided on a circuit forming surface of the semiconductor chip and wiring of the wiring board are connected by being sealed with the elastic body (elastomer).

【0014】前記(2)によれば、前記半導体チップの
外部電極と配線基板の配線を接続する導体(突起導体)
が、前記弾性体(エラストマ)により密封されているた
め、前記導体の周辺にボイドができて、接合部の剥がれ
や、パッケージクラックが発生することを低減できるの
で、半導体装置の信頼性が向上する。
According to the above (2), the conductor (projecting conductor) for connecting the external electrode of the semiconductor chip to the wiring of the wiring board.
However, since it is sealed by the elastic body (elastomer), voids are formed around the conductor, and peeling of a bonding portion and occurrence of a package crack can be reduced, so that the reliability of the semiconductor device is improved. .

【0015】(3)テープ状の絶縁性基材の配線基板形
成領域に、配線及びその外部接続端子を形成し、前記配
線の所定位置に突起導体を形成し、前記配線基板形成領
域の配線及び外部接続端子上に、前記突起導体と平面的
に重なる位置に開口部を有する弾性体(エラストマ)を
貼り付ける配線基板の製造方法である。
(3) Wirings and their external connection terminals are formed in the wiring substrate forming area of the tape-shaped insulating base material, and projecting conductors are formed at predetermined positions of the wirings. This is a method for manufacturing a wiring board in which an elastic body (elastomer) having an opening at a position overlapping the projecting conductor in a plane is attached to the external connection terminal.

【0016】前記(3)によれば、前記配線基板の配線
上に突起電極を設け、前記突起電極が露出するように弾
性体(エラストマ)を設けておくことで、前記配線基板
上に半導体チップを接着して、前記半導体チップの外部
電極と配線を接続する際の製造工程を簡略化させること
ができる。
According to the above (3), by providing a projecting electrode on the wiring of the wiring board and providing an elastic body (elastomer) so that the projecting electrode is exposed, the semiconductor chip is provided on the wiring board. To simplify the manufacturing process when connecting the external electrodes of the semiconductor chip and the wiring.

【0017】(4)テープ状の絶縁性基材の配線基板形
成領域に、配線及びその外部接続端子を形成し、前記配
線の所定位置に突起導体を形成し、前記配線基板形成領
域の配線及び外部接続端子上に、前記突起導体と平面的
に重なる位置に開口部を有する弾性体(エラストマ)を
貼り付け、前記弾性体上に、半導体チップを、その外部
電極形成面が前記弾性体と向かい合うように配置し、前
記半導体チップを、前記弾性体を介して前記配線基板に
接着するとともに、前記半導体チップの外部電極と前記
配線基板の配線を、前記弾性体で密封される突起導体に
より接続する半導体装置の製造方法である。
(4) Wirings and their external connection terminals are formed in the wiring substrate forming area of the tape-shaped insulating base material, and projecting conductors are formed at predetermined positions of the wirings. An elastic body (elastomer) having an opening at a position overlapping the projecting conductor in a plane is attached to the external connection terminal, and the semiconductor chip is placed on the elastic body, and an external electrode forming surface of the semiconductor chip faces the elastic body. And the semiconductor chip is adhered to the wiring board via the elastic body, and the external electrodes of the semiconductor chip and the wiring of the wiring board are connected by a projecting conductor sealed by the elastic body. 6 shows a method for manufacturing a semiconductor device.

【0018】前記(4)によれば、前記配線基板の配線
上に突起電極を設け、前記突起電極が露出するように弾
性体(エラストマ)を設けておくことで、前記配線基板
上に半導体チップを接着して、前記半導体チップの外部
電極と配線を接続する際の製造工程を簡略化させること
ができる。そのため、前記半導体装置の製造コストを低
減させることができる。また、前記半導体チップの外部
電極と配線基板の配線をフリップチップ接合する際に、
前記導体 (突起導体)がその周辺のエラストマにより
密封されるため、前記導体の周辺にボイドができて、接
合部分の剥がれやパッケージクラックが発生することを
低減でき、半導体装置の信頼性を向上させることができ
る。
According to the above (4), by providing a projecting electrode on the wiring of the wiring board and providing an elastic body (elastomer) so that the projecting electrode is exposed, the semiconductor chip is provided on the wiring board. To simplify the manufacturing process when connecting the external electrodes of the semiconductor chip and the wiring. Therefore, the manufacturing cost of the semiconductor device can be reduced. Also, when the external electrodes of the semiconductor chip and the wiring of the wiring board are flip-chip bonded,
Since the conductor (protruding conductor) is sealed by an elastomer around the conductor, voids are formed around the conductor, and peeling of a bonding portion and occurrence of a package crack can be reduced, thereby improving the reliability of the semiconductor device. be able to.

【0019】以下、本発明について、図面を参照して実
施の形態(実施例)とともに詳細に説明する。
Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.

【0020】なお、実施例を説明するための全図におい
て、同一機能を有するものは、同一符号をつけ、その繰
り返しの説明は省略する。
In all the drawings for explaining the embodiments, parts having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

【0021】[0021]

【発明の実施の形態】(実施例)図1及び図2は、本発
明による一実施例の半導体装置の概略構成を示す模式図
であり、図1(a)は半導体装置の平面図、図1(b)
は図1(a)の裏面図、図1(c)は図1(a)の左側
面図、図2(a)は図1(a)の半導体チップを省略し
て示した平面図、図2(b)は図2(a)のA−A’線
での断面図である。
(Embodiment) FIGS. 1 and 2 are schematic views showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view of the semiconductor device. 1 (b)
1A is a back view of FIG. 1A, FIG. 1C is a left side view of FIG. 1A, FIG. 2A is a plan view of the semiconductor chip of FIG. FIG. 2B is a sectional view taken along line AA ′ in FIG.

【0022】図1(a)、図1(b)、及び図1(c)
において、1は配線基板、2は弾性体(エラストマ)、
3は半導体チップ、4はボール端子である。また、図2
(a)及び図2(b)において、101は絶縁性基板、
102Aは配線、102Bは外部接続端子、301は半
導体チップの外部電極、5は導体(突起導体)である。
FIGS. 1 (a), 1 (b) and 1 (c)
Wherein 1 is a wiring board, 2 is an elastic body (elastomer),
3 is a semiconductor chip and 4 is a ball terminal. FIG.
2A and 2B, reference numeral 101 denotes an insulating substrate;
102A is a wiring, 102B is an external connection terminal, 301 is an external electrode of a semiconductor chip, and 5 is a conductor (projecting conductor).

【0023】本実施例の半導体装置は、例えば、図1
(a)、図1(b)、及び図1(c)に示すように、配
線基板1の一主面(表面)上に、弾性体(エラストマ)
2を介在させて半導体チップ3が接着されており、前記
配線基板1の前記表面と対向する面(裏面)には、例え
ば、Pb−Sn系はんだ等のボール端子4が接続された
BGA(Ball Grid Array )型の半導体装置である。ま
た、図1では示していないが、本実施例の半導体装置で
用いている半導体チップ3は、外部電極が、回路形成面
の中心線付近に線状に設けられたセンターパッド型の半
導体チップであるとする。
The semiconductor device of the present embodiment is, for example, shown in FIG.
As shown in (a), FIG. 1 (b), and FIG. 1 (c), an elastic body (elastomer) is formed on one main surface (surface) of the wiring board 1.
The semiconductor chip 3 is adhered to the wiring board 1 with a ball terminal 4 made of, for example, Pb-Sn-based solder connected to a surface (back surface) of the wiring substrate 1 facing the front surface (back surface). Grid Array) type semiconductor device. Although not shown in FIG. 1, the semiconductor chip 3 used in the semiconductor device of this embodiment is a center pad type semiconductor chip in which external electrodes are linearly provided near a center line of a circuit forming surface. Suppose there is.

【0024】また、本実施例の半導体装置では、図2
(a)及び図2(b)に示すように、前記配線基板1
は、絶縁性基板101とその表面に設けられた配線10
2A及びその外部接続端子102Bにより構成される。
また、前記配線102A及びその外部接続端子102B
上には、前記弾性体2を介して前記半導体チップ3が、
その外部電極301が形成された面を向かい合わせるよ
うに接着されており、前記半導体チップ3の外部電極3
01と前記配線基板の配線102Aは、前記弾性体(エ
ラストマ)2で密封された導体(突起導体)5により電
気的に接続されている。また、前記外部接続端子102
Bは、前記絶縁性基板101に設けられたビア孔を介し
て前記ボール端子4と接続されている。
Further, in the semiconductor device of this embodiment, FIG.
As shown in FIG. 2A and FIG.
Are the insulating substrate 101 and the wiring 10 provided on the surface thereof.
2A and its external connection terminal 102B.
The wiring 102A and its external connection terminal 102B
On the upper side, the semiconductor chip 3 is provided via the elastic body 2,
The external electrodes 301 of the semiconductor chip 3 are bonded so that the surfaces on which the external electrodes 301 are formed face each other.
01 and the wiring 102A of the wiring board are electrically connected by a conductor (projection conductor) 5 sealed with the elastic body (elastomer) 2. Also, the external connection terminal 102
B is connected to the ball terminal 4 via a via hole provided in the insulating substrate 101.

【0025】図3乃至図8は、本実施例の半導体装置の
製造方法を説明するための模式図であり、図3(a)、
図4(a)、図5(a)、及び図6(a)は配線基板の
製造方法を説明するための模式平面図、図3(b)、図
4(b)、図6(b)はそれぞれ、図3(a)、図4
(a)、図6(a)のB−B’線での断面図、図5
(b)は図5(a)のC−C’線での断面図、図7
(a)及び図8(a)は前記配線基板を用いた半導体装
置の製造方法を説明するための模式平面図、図7(b)
及び図8(b)はそれぞれ、図7(a)及び図8(a)
のB−B’線での断面図である。以下、図3乃至図8に
沿って、本実施例の半導体装置の製造方法について説明
する。なお、前記半導体装置で用いる半導体チップ3
は、外部電極が、回路形成面の中心線付近に線状に設け
られた、センターパッド型の半導体チップであるとす
る。
FIGS. 3 to 8 are schematic views for explaining a method of manufacturing the semiconductor device of this embodiment.
4 (a), 5 (a) and 6 (a) are schematic plan views for explaining a method of manufacturing a wiring board, and FIGS. 3 (b), 4 (b) and 6 (b). 3A and FIG.
FIG. 5A is a sectional view taken along line BB ′ of FIG.
FIG. 7B is a cross-sectional view taken along line CC ′ of FIG.
8A and FIG. 8A are schematic plan views for explaining a method of manufacturing a semiconductor device using the wiring substrate, and FIG.
8A and FIG. 8B respectively show FIG. 7A and FIG.
13 is a sectional view taken along line BB ′ of FIG. Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. The semiconductor chip 3 used in the semiconductor device
Is a center pad type semiconductor chip in which external electrodes are linearly provided near the center line of the circuit formation surface.

【0026】まず、図3(a)及び図3(b)に示すよ
うに、例えば、ポリイミドなどの絶縁性のテープ状基材
6の配線基板形成領域1’に、所定の配線パターンの配
線102A及び外部接続端子102Bを形成し、前記テ
ープ状基材6の前記外部接続端子102B部分にビア孔
103を開口する。前記配線102A及び外部接続端子
102Bは、前記テープ状基材6の表面に設けられた、
例えば、銅箔のような導電性薄膜上に、所定の配線パタ
ーンに対応したレジストを形成し、前記レジストをマス
クとして前記導電性薄膜上にめっき層を形成し、その
後、前記レジストを除去して、今度は前記めっき層をマ
スクとして前記導電性薄膜をエッチング処理することに
より形成される。また、前記ビア孔103は、例えば、
レジスト膜をマスクとしたエッチング処理や、レーザに
よる開口などで形成する。また、前記テープ状基材6上
には、図3(a)に示したような配線基板形成領域1’
が複数個あり、各配線基板形成領域1’に同様の配線パ
ターンが形成される。
First, as shown in FIGS. 3 (a) and 3 (b), a wiring 102A having a predetermined wiring pattern is formed in a wiring board forming region 1 'of an insulating tape-shaped base material 6 made of, for example, polyimide. And an external connection terminal 102B, and a via hole 103 is opened in the external connection terminal 102B portion of the tape-shaped base material 6. The wiring 102A and the external connection terminal 102B are provided on the surface of the tape-shaped base material 6,
For example, on a conductive thin film such as a copper foil, a resist corresponding to a predetermined wiring pattern is formed, a plating layer is formed on the conductive thin film using the resist as a mask, and then the resist is removed. This time, the conductive thin film is formed by etching using the plating layer as a mask. The via hole 103 is formed, for example, by
It is formed by an etching process using a resist film as a mask, an opening by a laser, or the like. Further, on the tape-shaped base material 6, a wiring board forming area 1 'as shown in FIG.
And a similar wiring pattern is formed in each wiring board formation region 1 '.

【0027】次に、図4(a)及び図4(b)に示すよ
うに、前記配線102Aの所定位置に突起導体(バン
プ)5を形成する。前記突起導体5は、例えば、Pb−
Sn系はんだ等のはんだボールを前記配線102A上に
載せて、部分的に融解させて形成する方法や、金(A
u)ワイヤを用いてスタッドバンプを形成する方法など
がある。
Next, as shown in FIGS. 4A and 4B, projecting conductors (bumps) 5 are formed at predetermined positions of the wiring 102A. The projecting conductor 5 is, for example, Pb-
A method in which a solder ball such as Sn-based solder is placed on the wiring 102A and partially melted,
u) There is a method of forming a stud bump using a wire.

【0028】次に、図5(a)及び図5(b)に示した
ような、前記配線102Aに形成された突起導体5と対
応する位置に開口部201を有する弾性体(エラスト
マ)2を準備する。前記弾性体2は、例えば、熱硬化性
のエポキシ系樹脂にフィラーなどの添加剤を所定の割合
で配合して所定の弾性率が得られるようにしておく。ま
たこのとき、前記弾性体2の一主面には、図5(b)に
示したようにカバーフィルム7を設けておく。また、前
記開口部201は、前記突起電極5と同じ大きさ、もし
くは突起電極5よりも少し小さく形成する。
Next, as shown in FIGS. 5A and 5B, an elastic body (elastomer) 2 having an opening 201 at a position corresponding to the projecting conductor 5 formed on the wiring 102A is prepared. prepare. The elastic body 2 is prepared, for example, by adding an additive such as a filler to a thermosetting epoxy resin at a predetermined ratio so as to obtain a predetermined elastic modulus. At this time, a cover film 7 is provided on one main surface of the elastic body 2 as shown in FIG. The opening 201 is formed to have the same size as the projecting electrode 5 or a little smaller than the projecting electrode 5.

【0029】次に、図6(a)及び図6(b)に示すよ
うに、前記テープ状基板6の配線基板形成領域1’に形
成された配線102A及びその外部接続端子102B上
に、図5(a)及び図5(b)に示したカバーフィルム
7が設けられた弾性体2を配置する。このとき、前記弾
性体2は、前記開口部201が前記配線102A上の突
起導体5と平面的に重なるように位置あわせをして、前
記開口部201内に突起導体5が挿入されるように配置
される。またこのとき、前記弾性体2の開口部201を
前記突起導体5よりも小さくしておくことにより、前記
突起導体5が前記開口部201に押し込まれるように、
隙間なく挿入することができる。
Next, as shown in FIGS. 6A and 6B, the wiring 102A formed in the wiring board forming region 1 'of the tape-like substrate 6 and the external connection terminals 102B are placed on the wiring 102A. The elastic body 2 provided with the cover film 7 shown in FIG. 5A and FIG. 5B is arranged. At this time, the elastic body 2 is positioned so that the opening 201 overlaps the projecting conductor 5 on the wiring 102A in a plane, so that the projecting conductor 5 is inserted into the opening 201. Be placed. At this time, by making the opening 201 of the elastic body 2 smaller than the projecting conductor 5, the projecting conductor 5 is pushed into the opening 201 so that the projecting conductor 5 is pushed into the opening 201.
It can be inserted without gaps.

【0030】以上の手順に沿って、本実施例の半導体装
置に用いる配線基板1が各配線基板形成領域1’に形成
されたテープ状基材6が形成される。
According to the above procedure, the tape-shaped base material 6 in which the wiring board 1 used in the semiconductor device of the present embodiment is formed in each wiring board forming area 1 'is formed.

【0031】次に、図6(a)及び図6(b)に示した
ようなテープ状基材6の配線基板形成領域1’上に設け
られた弾性体(エラストマ)2の表面のカバーフィルム
7を剥がして、図7(a)及び図7(b)に示すよう
に、前記弾性体2上に、センターパッド型の半導体チッ
プ3を、その外部電極形成面が前記弾性体2と向かい合
うようにして、前記外部電極301と前記突起電極5の
位置あわせを行い、配置する。
Next, a cover film on the surface of the elastic body (elastomer) 2 provided on the wiring board forming region 1 'of the tape-like base material 6 as shown in FIGS. 6 (a) and 6 (b) 7, the center pad type semiconductor chip 3 is placed on the elastic body 2 so that the external electrode forming surface faces the elastic body 2 as shown in FIGS. 7 (a) and 7 (b). Then, the external electrode 301 and the protruding electrode 5 are aligned and arranged.

【0032】次に、例えば、前記弾性体2を加熱すると
ともに、前記半導体チップ3を押圧して、前記半導体チ
ップ3と前記弾性体2を接着するとともに、前記半導体
チップ3の外部電極301と前記突起導体5を接続す
る。このとき、前記突起導体5は、図2(a)及び図2
(b)に示したように、その周囲が前記弾性体(エラス
トマ)2で囲まれているため、前記半導体チップ3の外
部電極301と前記配線基板1の配線102Aを突起導
体5によりフリップチップ接合されると同時に、前記接
合部分が前記弾性体2により封止(密封)される。すな
わち、本実施例の半導体装置の製造方法では、前記半導
体チップの外部電極と配線基板の配線をフリップチップ
接合する工程と、前記接合部を封止する工程を一工程で
行うことができる。
Next, for example, the elastic body 2 is heated and the semiconductor chip 3 is pressed to bond the semiconductor chip 3 to the elastic body 2 and to connect the external electrode 301 of the semiconductor chip 3 to the semiconductor chip 3. The projecting conductor 5 is connected. At this time, the protruding conductors 5 are shown in FIGS.
As shown in (b), the periphery is surrounded by the elastic body (elastomer) 2, so that the external electrodes 301 of the semiconductor chip 3 and the wiring 102 A of the wiring board 1 are flip-chip bonded by the projecting conductor 5. At the same time, the joint portion is sealed (sealed) by the elastic body 2. That is, in the method of manufacturing a semiconductor device according to the present embodiment, the step of flip-chip bonding the external electrodes of the semiconductor chip and the wiring of the wiring board and the step of sealing the bonding portion can be performed in one step.

【0033】その後、前記テープ状基材6に設けられた
ビア孔103上に、例えば、Pb−Sn系はんだ等のボ
ール端子4を配置して、前記ボール端子4を部分的に融
解させて前記ビア孔103内に流し込み、図8(a)及
び図8(b)に示すように、前記ボール端子4と前記外
部接続端子102Bと電気的に接続する。その後、前記
テープ状基材6を前記配線基板形成領域1’の外周部分
で切断すると、図2(a)及び図2(b)に示したよう
な半導体装置が得られる。
Thereafter, a ball terminal 4 made of, for example, a Pb-Sn-based solder is placed on the via hole 103 provided in the tape-shaped base material 6, and the ball terminal 4 is partially melted. It flows into the via hole 103, and as shown in FIGS. 8A and 8B, the ball terminal 4 and the external connection terminal 102B are electrically connected. Thereafter, when the tape-shaped base material 6 is cut at the outer peripheral portion of the wiring substrate forming region 1 ', a semiconductor device as shown in FIGS. 2A and 2B is obtained.

【0034】以上説明したように、本実施例によれば、
絶縁性基材101の表面に形成された配線102Aの所
定位置に突起導体(バンプ)5を設け、前記配線102
A及びその外部接続端子102B上に、前記突起導体5
の表面が露出するように弾性体(エラストマ)2を設け
た配線基板1を用いることにより、半導体チップ3を、
その外部電極301形成面が前記弾性体2と向かい合う
ようにして前記外部電極301と配線102Aをフリッ
プチップ接合すると同時に、前記接合部の封止をするこ
とができる。そのため、従来2つの工程だった、フリッ
プチップ接合をする工程と、接合部を封止する工程を一
工程で行い、製造工程を少なくすることができる、半導
体装置の製造コストを低減させることができる。
As described above, according to this embodiment,
A protruding conductor (bump) 5 is provided at a predetermined position on a wiring 102A formed on the surface of the insulating base material 101, and the wiring 102A is formed.
A and the projecting conductor 5 on the external connection terminal 102B.
By using the wiring board 1 provided with the elastic body (elastomer) 2 so that the surface of the
The external electrode 301 and the wiring 102A are flip-chip bonded so that the surface on which the external electrode 301 is formed faces the elastic body 2, and at the same time, the bonding portion can be sealed. For this reason, the flip chip bonding step and the bonding section sealing step, which were two steps in the related art, are performed in one step, so that the number of manufacturing steps can be reduced, and the manufacturing cost of the semiconductor device can be reduced. .

【0035】また、前記配線基板1を用いてフリップチ
ップ接合を行うと、前記外部電極301と配線102A
を電気的に接続する導体(バンプ)5は、前記弾性体
(エラストマ)により封止(密封)されるので、導体5
の周辺にボイドができて、接合部分の剥離や、パッケー
ジクラックなどが発生することを低減でき、半導体装置
の信頼性が向上する。
When flip-chip bonding is performed using the wiring substrate 1, the external electrode 301 and the wiring 102A are connected.
(Bump) 5 for electrically connecting the conductor 5 is sealed (sealed) by the elastic body (elastomer).
, The occurrence of voids in the periphery of the semiconductor device and the occurrence of peeling of the bonding portion and cracking of the package can be reduced, and the reliability of the semiconductor device can be improved.

【0036】図9(a)及び図9(b)は前記実施例の
半導体装置の応用例を示す模式断面図である。
FIGS. 9A and 9B are schematic sectional views showing application examples of the semiconductor device of the above embodiment.

【0037】前記実施例では、一つのセンターパッド型
の半導体チップ3を配線基板1上にフリップチップ接合
した半導体装置を例に挙げて説明したが、これに限ら
ず、例えば、図9(a)に示したように、前記実施例で
説明した配線基板1上にフリップチップ接合されたセン
ターパッド型の半導体装置3上に、接着剤8を介して、
例えば、回路形成面の2方向の辺に沿って外部電極90
1が設けられた半導体チップ9を積層した半導体装置で
あっても良い。この場合、前記半導体チップ9の外部電
極901はボンディングワイヤ10により前記配線基板
上の配線102Aと接続され、積層されたセンターパッ
ド型の半導体チップ3及び半導体チップ9、ボンディン
グワイヤ10、及びその接続部はモールド樹脂11によ
り封止される。
In the above embodiment, a semiconductor device in which one center pad type semiconductor chip 3 is flip-chip bonded on the wiring board 1 has been described as an example. However, the present invention is not limited to this. For example, FIG. As shown in the above, on the center pad type semiconductor device 3 which is flip-chip bonded to the wiring board 1 described in the above embodiment,
For example, the external electrodes 90 may extend along two sides of the circuit forming surface.
1 may be a semiconductor device in which the semiconductor chips 9 provided with 1 are stacked. In this case, the external electrode 901 of the semiconductor chip 9 is connected to the wiring 102A on the wiring board by the bonding wire 10, and the center pad type semiconductor chip 3 and the semiconductor chip 9, the bonding wire 10, and the connection portion thereof are stacked. Is sealed with a mold resin 11.

【0038】また、前記実施例で説明した配線基板1上
にフリップチップ接続される半導体チップ前記実施例で
挙げたセンターパッド型の半導体装置3に限らず、図9
(b)に示したような、回路形成面の2方向の辺に沿っ
て外部電極が形成された半導体チップであっても良い。
この場合も、前記実施例で説明したように、絶縁性基板
101上に形成された配線102Aの所定位置に突起電
極5を設け、前記突起電極5に対応する位置に開口部が
形成された弾性体(エラストマ)を設けた配線基板を製
造することにより、フリップチップ接合する工程と接合
部を封止する工程を一工程で行うことができ、製造工程
が少なくなり製造コストが低減する。
Further, the semiconductor chip to be flip-chip connected on the wiring board 1 described in the above embodiment is not limited to the center pad type semiconductor device 3 described in the above embodiment.
A semiconductor chip in which external electrodes are formed along two sides of a circuit forming surface as shown in FIG.
Also in this case, as described in the above embodiment, the protruding electrode 5 is provided at a predetermined position of the wiring 102A formed on the insulating substrate 101, and an elastic portion having an opening at a position corresponding to the protruding electrode 5 is formed. By manufacturing the wiring board provided with the body (elastomer), the step of flip-chip bonding and the step of sealing the bonding portion can be performed in one step, and the number of manufacturing steps is reduced, and the manufacturing cost is reduced.

【0039】以上、本発明を、前記実施例に基づき具体
的に説明したが、本発明は、前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲において種々変
更可能であることはもちろんである。
As described above, the present invention has been specifically described based on the above-described embodiment. However, the present invention is not limited to the above-described embodiment, and may be variously modified without departing from the gist thereof. Of course.

【0040】[0040]

【発明の効果】本発明において開示される発明のうち、
代表的なものによって得られる効果を簡単に説明すれ
ば、以下のとおりである。
According to the invention disclosed in the present invention,
The effect obtained by the representative one will be briefly described as follows.

【0041】(1)配線基板上に、弾性体を介して半導
体チップをフリップチップ接合した半導体装置におい
て、製造工程を簡略化することができる。
(1) In a semiconductor device in which a semiconductor chip is flip-chip bonded on a wiring board via an elastic body, the manufacturing process can be simplified.

【0042】(2)配線基板上に、弾性体を介して半導
体チップをフリップチップ接合した半導体装置におい
て、半導体チップの外部電極と配線の接続不良を低減す
ることができる。
(2) In a semiconductor device in which a semiconductor chip is flip-chip bonded on a wiring board via an elastic body, it is possible to reduce the connection failure between the external electrodes of the semiconductor chip and the wiring.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による一実施例の半導体装置の概略構成
を示す模式図である。
FIG. 1 is a schematic diagram showing a schematic configuration of a semiconductor device according to one embodiment of the present invention.

【図2】本発明による一実施例の半導体装置の概略構成
を示す模式図である。
FIG. 2 is a schematic diagram showing a schematic configuration of a semiconductor device according to one embodiment of the present invention.

【図3】本実施例の半導体装置の製造方法を説明するた
めの模式図である。
FIG. 3 is a schematic view for explaining the method for manufacturing the semiconductor device according to the embodiment.

【図4】本実施例の半導体装置の製造方法を説明するた
めの模式図である。
FIG. 4 is a schematic view for explaining the method for manufacturing the semiconductor device according to the present embodiment.

【図5】本実施例の半導体装置の製造方法を説明するた
めの模式図である。
FIG. 5 is a schematic view for explaining the method for manufacturing the semiconductor device according to the embodiment.

【図6】本実施例の半導体装置の製造方法を説明するた
めの模式図である。
FIG. 6 is a schematic diagram for explaining the method for manufacturing the semiconductor device according to the present embodiment.

【図7】本実施例の半導体装置の製造方法を説明するた
めの模式図である。
FIG. 7 is a schematic view for explaining the method for manufacturing the semiconductor device according to the present embodiment.

【図8】本実施例の半導体装置の製造方法を説明するた
めの模式図である。
FIG. 8 is a schematic view for explaining the method for manufacturing the semiconductor device according to the present embodiment.

【図9】前記実施例の半導体装置の応用例を示す模式断
面図である。
FIG. 9 is a schematic sectional view showing an application example of the semiconductor device of the embodiment.

【図10】従来のフリップチップ接合した半導体装置の
概略構成を示す模式図である。
FIG. 10 is a schematic diagram showing a schematic configuration of a conventional flip-chip bonded semiconductor device.

【図11】従来のフリップチップ接合した半導体装置の
封止方法を説明するための模式図である。
FIG. 11 is a schematic diagram for explaining a conventional method of sealing a flip-chip bonded semiconductor device.

【符号の説明】[Explanation of symbols]

1 配線基板 101 絶縁性基材 102A 配線 102B 外部接続端子 103 ビア孔 2 弾性体(エラストマ) 201 エラストマの開口部 3 センターパッド型の半導体チップ 301 外部電極 4 ボール端子 5 突起導体(バンプ) 6 テープ状基材 7 カバーフィルム 8 接着剤 9 半導体チップ 901 外部電極 10 ボンディングワイヤ 11 封止樹脂 12 半導体チップ 1201 外部電極 13 封止樹脂(アンダーフィル) 14 ノズル 15 ボイド DESCRIPTION OF SYMBOLS 1 Wiring board 101 Insulating base material 102A Wiring 102B External connection terminal 103 Via hole 2 Elastic body (Elastomer) 201 Elastomer opening 3 Center pad type semiconductor chip 301 External electrode 4 Ball terminal 5 Projection conductor (bump) 6 Tape shape Base material 7 Cover film 8 Adhesive 9 Semiconductor chip 901 External electrode 10 Bonding wire 11 Sealing resin 12 Semiconductor chip 1201 External electrode 13 Sealing resin (underfill) 14 Nozzle 15 Void

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】絶縁性基材と、前記基材の表面に設けられ
た配線及びその外部接続端子とを備える配線基板におい
て、 前記配線の所定位置に突起導体が設けられ、 前記絶縁性基材の配線及びその外部接続端子上に、前記
突起導体の表面が露出するように弾性体(エラストマ)
が設けられていることを特徴とする配線基板。
1. A wiring board comprising an insulating base material, wiring provided on a surface of the base material, and external connection terminals thereof, wherein a projecting conductor is provided at a predetermined position of the wiring, Elastic body (elastomer) such that the surface of the projecting conductor is exposed on the wiring and the external connection terminals thereof.
A wiring board, comprising:
【請求項2】絶縁性基材の表面に配線及びその外部接続
端子が設けられ、 前記配線の所定位置に突起導体が設けられ、前記絶縁性
基材の配線及びその外部接続端子上に、前記突起導体の
表面が露出するように弾性体(エラストマ)が設けられ
た配線基板を設け、前記配線基板の弾性体上に、半導体
チップをその回路形成面が前記弾性体と向かい合うよう
に設け、前記半導体チップの回路形成面に設けられた外
部電極と前記配線基板の配線が、前記弾性体(エラスト
マ)で密封されて接続されていることを特徴とする半導
体装置。
2. A wiring and an external connection terminal thereof are provided on the surface of the insulating base material, a projecting conductor is provided at a predetermined position of the wiring, and the wiring and the external connection terminal of the insulating base material are provided on the wiring. A wiring board provided with an elastic body (elastomer) such that the surface of the projecting conductor is exposed; and a semiconductor chip provided on the elastic body of the wiring board such that a circuit forming surface thereof faces the elastic body. A semiconductor device, wherein an external electrode provided on a circuit formation surface of a semiconductor chip and a wiring of the wiring substrate are connected by being sealed with the elastic body (elastomer).
【請求項3】テープ状の絶縁性基材の配線基板形成領域
に、配線及びその外部接続端子を形成し、 前記配線の所定位置に突起導体を形成し、 前記配線基板形成領域の配線及び外部接続端子上に、前
記突起導体と平面的に重なる位置に開口部を有する弾性
体(エラストマ)を貼り付けることを特徴とする配線基
板の製造方法。
3. A wiring and an external connection terminal are formed in a wiring board forming area of a tape-shaped insulating base material, a projecting conductor is formed at a predetermined position of the wiring, and a wiring and an external of the wiring board forming area are formed. A method of manufacturing a wiring board, comprising: attaching an elastic body (elastomer) having an opening at a position overlapping with the projecting conductor in a plane on the connection terminal.
【請求項4】テープ状の絶縁性基材の配線基板形成領域
に、配線及びその外部接続端子を形成し、 前記配線の所定位置に突起導体を形成し、 前記配線基板形成領域の配線及び外部接続端子上に、前
記突起導体と平面的に重なる位置に開口部を有する弾性
体(エラストマ)を貼り付け、 前記弾性体上に、半導体チップを、その外部電極形成面
が前記弾性体と向かい合うように配置し、 前記半導体チップを、前記弾性体を介して前記配線基板
に接着するとともに、前記半導体チップの外部電極と前
記配線基板の配線を、前記弾性体で密封される突起導体
により接続することを特徴とする半導体装置の製造方
法。
4. A wiring and an external connection terminal are formed in a wiring board forming area of a tape-shaped insulating base material, a projecting conductor is formed at a predetermined position of the wiring, and a wiring and an external wiring in the wiring board forming area are formed. An elastic body (elastomer) having an opening at a position overlapping the projecting conductor in a plane is attached to the connection terminal, and the semiconductor chip is placed on the elastic body so that an external electrode forming surface faces the elastic body. And bonding the semiconductor chip to the wiring board via the elastic body, and connecting the external electrodes of the semiconductor chip and the wiring of the wiring board by a projecting conductor sealed by the elastic body. A method for manufacturing a semiconductor device, comprising:
JP2000311721A 2000-10-05 2000-10-05 Wiring board, semiconductor device using the same, and manufacturing method thereof Expired - Fee Related JP4035949B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000311721A JP4035949B2 (en) 2000-10-05 2000-10-05 Wiring board, semiconductor device using the same, and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000311721A JP4035949B2 (en) 2000-10-05 2000-10-05 Wiring board, semiconductor device using the same, and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2002118197A true JP2002118197A (en) 2002-04-19
JP4035949B2 JP4035949B2 (en) 2008-01-23

Family

ID=18791439

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Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP4035949B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002190548A (en) * 2000-12-20 2002-07-05 Hitachi Cable Ltd Semiconductor device and manufacturing method therefor
JP2007266564A (en) * 2006-03-29 2007-10-11 Hynix Semiconductor Inc Flip chip bonded package
JP2009038142A (en) * 2007-07-31 2009-02-19 Elpida Memory Inc Semiconductor stacked package
US7667317B2 (en) 2006-05-29 2010-02-23 Elpida Memory, Inc. Semiconductor package with bypass capacitor
CN103295989A (en) * 2012-02-29 2013-09-11 联发科技股份有限公司 Flip chip package
US9437534B2 (en) 2012-02-29 2016-09-06 Mediatek Inc. Enhanced flip chip structure using copper column interconnect

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002190548A (en) * 2000-12-20 2002-07-05 Hitachi Cable Ltd Semiconductor device and manufacturing method therefor
JP2007266564A (en) * 2006-03-29 2007-10-11 Hynix Semiconductor Inc Flip chip bonded package
JP2012064991A (en) * 2006-03-29 2012-03-29 Hynix Semiconductor Inc Flip-chip bonded package
US7667317B2 (en) 2006-05-29 2010-02-23 Elpida Memory, Inc. Semiconductor package with bypass capacitor
JP2009038142A (en) * 2007-07-31 2009-02-19 Elpida Memory Inc Semiconductor stacked package
CN103295989A (en) * 2012-02-29 2013-09-11 联发科技股份有限公司 Flip chip package
US9437534B2 (en) 2012-02-29 2016-09-06 Mediatek Inc. Enhanced flip chip structure using copper column interconnect

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