JPH08330340A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH08330340A JPH08330340A JP7130308A JP13030895A JPH08330340A JP H08330340 A JPH08330340 A JP H08330340A JP 7130308 A JP7130308 A JP 7130308A JP 13030895 A JP13030895 A JP 13030895A JP H08330340 A JPH08330340 A JP H08330340A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- solder resist
- resin
- sealing
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 104
- 229920005989 resin Polymers 0.000 claims abstract description 103
- 239000011347 resin Substances 0.000 claims abstract description 103
- 229910000679 solder Inorganic materials 0.000 claims abstract description 100
- 238000007789 sealing Methods 0.000 claims abstract description 89
- 238000000034 method Methods 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000004020 conductor Substances 0.000 claims description 16
- 230000001747 exhibiting effect Effects 0.000 claims description 13
- 239000003795 chemical substances by application Substances 0.000 claims description 12
- 229920002545 silicone oil Polymers 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 230000001678 irradiating effect Effects 0.000 claims description 8
- 238000007747 plating Methods 0.000 abstract description 21
- 229910052737 gold Inorganic materials 0.000 abstract description 18
- 239000010931 gold Substances 0.000 abstract description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 17
- 239000000853 adhesive Substances 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000013022 venting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、更に詳細には基板の一面に搭載された半導体素子
を樹脂封止する半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a semiconductor element mounted on one surface of a substrate is resin-sealed.
【０００２】[0002]
【従来の技術】半導体装置には、基板に搭載された半導
体素子を封止すべく、半導体素子が搭載されている基板
の片側面が樹脂封止されたタイプの半導体装置が使用さ
れている。かかるタイプの半導体装置を製造する際に
は、基板に搭載した半導体素子が配置された封止金型の
キャビティ内に、半導体素子が搭載された基板面に沿っ
て配設された封止金型の樹脂注入路を経由して封止樹脂
を注入し、半導体素子を封止する樹脂封止層を形成す
る。この様にして得られた半導体装置の一例を図７に示
す。図７は、複数個の半導体装置１０、１０・・が、一
枚の短冊状の基板２０上に連なって形成されているもの
であり、各半導体装置１０を形成する樹脂封止層２に
は、ランナー樹脂８が付着している。尚、図７に示す基
板２０には、各半導体装置１０が破線によって囲まれて
いる領域６の個片に分割し易いように、長孔３、３・・
が領域６の外縁に沿って穿設されている。2. Description of the Related Art As a semiconductor device, a semiconductor device of a type in which one side surface of a substrate on which the semiconductor element is mounted is resin-sealed is used to seal the semiconductor element mounted on the substrate. When manufacturing a semiconductor device of this type, a sealing mold is provided along a surface of a substrate on which the semiconductor element is mounted, in a cavity of the sealing mold on which the semiconductor element mounted on the substrate is arranged. A sealing resin is injected through the resin injection path to form a resin sealing layer that seals the semiconductor element. An example of the semiconductor device thus obtained is shown in FIG. 7 shows that a plurality of semiconductor devices 10, 10, ... Are formed in series on one strip-shaped substrate 20, and the resin sealing layer 2 forming each semiconductor device 10 has , Runner resin 8 is attached. It should be noted that in the substrate 20 shown in FIG. 7, the long holes 3, 3, ... To facilitate the division of each semiconductor device 10 into individual pieces of the region 6 surrounded by the broken line.
Are drilled along the outer edge of the region 6.
【０００３】このランナー樹脂８は、封止金型の樹脂注
入路内に流入した封止樹脂によって形成されたものであ
り、製品としては不要なものである。このため、ランナ
ー樹脂８は基板２０から剥離されて除去される。従来、
かかるランナー樹脂８の剥離を容易にすべく、封止金型
の樹脂注入路が配設されて基板２０上にランナー樹脂８
が形成されるランナー部には、例えば銅箔をエッチング
して導体パターンを形成する際に、ランナー部を形成す
る位置に残した銅箔上にニッケルめっきを施した後、金
めっきを施して金属めっき層を形成する。尚、封止金型
のキャビティ内に封止樹脂を注入する際に、キャビティ
内の空気をベントするために封止金型の複数箇所に設け
られたエアベントは、図７に示す様に、矩形状の封止樹
脂層２の角部（ランナー樹脂８ができる角部を除く）に
対応するＡ部の位置となるように配設した。The runner resin 8 is formed by the sealing resin that has flowed into the resin injection passage of the sealing die, and is not necessary as a product. Therefore, the runner resin 8 is separated from the substrate 20 and removed. Conventionally,
In order to facilitate the peeling of the runner resin 8, the resin injection path of the sealing die is provided so that the runner resin 8 is provided on the substrate 20.
In the runner portion where is formed, for example, when a copper foil is etched to form a conductor pattern, nickel is plated on the copper foil left at the position where the runner portion is formed, and then gold plating is applied to the metal. A plating layer is formed. When the sealing resin is injected into the cavity of the sealing mold, the air vents provided at a plurality of positions of the sealing mold for venting the air inside the cavity are rectangular as shown in FIG. The encapsulating resin layer 2 was arranged so as to be located at a position corresponding to a corner (excluding a corner where the runner resin 8 is formed) of the sealing resin layer 2.
【０００４】[0004]
【発明が解決しようとする課題】この様に、ランナー樹
脂８が形成される基板２０のランナー部に、予め金めっ
きを施しておくことによって、形成されたランナー樹脂
８の剥離を容易に行うことができる。しかし、ランナー
部に施される金めっきは、ランナー樹脂８の剥離を容易
に行うためであり、ランナー部は半導体装置の特性に関
与する部分ではなく、高価な金めっきを施すことは経済
的な面からも問題である。また、ランナー部は、半導体
装置の外観に残る部分であるため、半導体装置の外観上
からも金めっきを施したくない部分である。このため、
本発明者等は、ランナー部に施す金めっきを省略すべ
く、基板のランナー部に封止樹脂に対して剥離性を呈す
るソルダーレジストを塗布する方法を試みた。この方法
においては、かかるソルダーレジストを基板の略全面に
塗布すると、封止樹脂と基板との密着性が問題となるた
め、ランナー部のみにソルダーレジストを塗布すること
が必要となる。しかしながら、通常、ランナー部のみに
ソルダーレジストを工業的に塗布することが困難である
ため、依然として、基板のランナー部に金めっきが施さ
れている。そこで、本発明の目的は、基板のランナー部
のみに封止樹脂に対して剥離性を呈するソルダーレジス
ト層を工業的に形成し、樹脂封止の際に、基板上に形成
されるランナー樹脂を基板から容易に剥離し得る半導体
装置の製造方法を提供することにある。Thus, the runner resin 8 formed on the substrate 20 can be easily peeled off by pre-plating the runner portion of the substrate 20 on which the runner resin 8 is formed. You can However, the gold plating applied to the runner portion is to facilitate the peeling of the runner resin 8, and the runner portion is not a part related to the characteristics of the semiconductor device, and it is economical to apply expensive gold plating. It is also a problem from the aspect. Further, since the runner portion is a portion that remains in the appearance of the semiconductor device, it is a portion where gold plating is not desired even from the appearance of the semiconductor device. For this reason,
The present inventors have tried a method of applying a solder resist exhibiting releasability to the sealing resin to the runner portion of the substrate in order to omit the gold plating applied to the runner portion. In this method, if such a solder resist is applied to substantially the entire surface of the substrate, the adhesion between the sealing resin and the substrate becomes a problem, so it is necessary to apply the solder resist only to the runner portion. However, since it is usually difficult to industrially apply the solder resist only to the runner portion, gold plating is still applied to the runner portion of the substrate. Therefore, an object of the present invention is to industrially form a solder resist layer exhibiting releasability with respect to the sealing resin only on the runner portion of the substrate, and to prevent the runner resin formed on the substrate during resin sealing. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be easily peeled from a substrate.
【０００５】[0005]
【課題を解決するための手段】本発明者等は、前記目的
を達成すべく種々検討した結果、ランナー部を含む基板
の略全面に、封止樹脂に対して剥離性を呈するソレダー
レジストを塗布した後、樹脂封止される基板面の封止部
分のみに紫外線を照射したところ、封止部分のソレダー
レジストを封止樹脂に対して密着性に変換でき、且つラ
ンナー部に塗布したソレダーレジストの封止樹脂に対す
る剥離性を維持していることを見出し、本発明に到達し
た。すなわち、本発明は、基板の一面に搭載された半導
体素子が配置された封止金型のキャビティ内に、前記基
板の一面に形成されたランナー部に沿って配設された封
止金型の樹脂注入通路から封止樹脂を注入し、半導体素
子を樹脂封止して半導体装置を製造する際に、該基板の
一面に形成された半導体素子の搭載部及び搭載部近傍に
形成された導体パターンのボンディング部を除く基板面
に、基板に対する密着性と封止樹脂に対する剥離性とを
併有するソルダーレジストを塗布した後、前記基板の搭
載部に搭載された半導体素子と導体パターンのボンディ
ング部とを電気的に接続すると共に、前記基板に塗布さ
れた前記ソルダーレジストのうち、基板のランナー部に
塗布されたソルダーレジストを除く、少なくとも樹脂封
止される基板の封止部分に塗布されたソルダーレジスト
を、紫外線等の光線を照射して封止樹脂に対し密着性を
呈するソルダーレジストに変換し、次いで、前記基板に
搭載された半導体素子が配置された封止金型のキャビテ
ィ内に、基板のランナー部に沿って配設された封止金型
の樹脂注入路から封止樹脂を注入することを特徴とする
半導体装置の製造方法にある。Means for Solving the Problems As a result of various investigations for achieving the above-mentioned object, the present inventors have found that a solderer resist exhibiting releasability with respect to a sealing resin is provided on substantially the entire surface of a substrate including a runner portion. After coating, when only the sealing part of the substrate surface to be resin-sealed was irradiated with ultraviolet rays, the solder resist in the sealing part could be converted into adhesiveness to the sealing resin, and the solder applied to the runner part The present invention has been accomplished by finding that the peelability of the dare resist with respect to the sealing resin is maintained. That is, the present invention provides a sealing die arranged along a runner portion formed on the one surface of the substrate in a cavity of the sealing die in which the semiconductor element mounted on the one surface of the substrate is arranged. When a semiconductor device is manufactured by injecting a sealing resin from a resin injection passage and sealing a semiconductor element with a resin, a semiconductor element mounting portion formed on one surface of the substrate and a conductor pattern formed in the vicinity of the mounting portion After applying a solder resist having both adhesiveness to the substrate and releasability to the sealing resin to the substrate surface excluding the bonding part, the semiconductor element mounted on the mounting part of the substrate and the bonding part of the conductor pattern are Of the solder resist that is electrically connected and that is applied to the substrate, excluding the solder resist that is applied to the runner portion of the substrate, at least the sealing portion of the substrate that is resin-sealed Is converted into a solder resist exhibiting adhesiveness to the sealing resin by irradiating light rays such as ultraviolet rays onto the solder resist coated on the substrate, and then the semiconductor die mounted with the semiconductor element mounted on the substrate. A method for manufacturing a semiconductor device is characterized in that a sealing resin is injected into a cavity from a resin injection path of a sealing die arranged along a runner portion of a substrate.
【０００６】かかる構成を有する本発明において、ソル
ダーレジストに照射する紫外線等の光線として、石英ガ
ラスを透過した紫外線を用いることによって、照射する
紫外線の波長を揃えることができる。また、基板に半導
体素子を搭載した後、少なくとも基板のランナー部及び
半導体素子をマスクによって覆い、ソルダーレジストに
紫外線等の光線を照射すること、或いは基板に半導体素
子を搭載する前に、少なくとも基板のランナー部をマス
クによって覆い、ソルダーレジストに紫外線等の光線を
照射することによって、封止部分に塗布されたソルダー
レジストのみを封止樹脂に対して密着性を呈するソルダ
ーレジストに容易に変換することができる。かかる紫外
線等の光線の照射は、基板を加熱しつつ行うことが効果
的である。更に、基板として、樹脂基板を用いることに
よって、得られた半導体装置の軽量化等を図ることがで
き、樹脂基板を採用した際には、半導体素子が一面に搭
載された基板の他面に、はんだボール等の外部接続端子
が装着される外部接続端子用パッドを除き、基板に対す
る密着性と封止樹脂に対する剥離性とを併有するソルダ
ーレジストを塗布することによって、ソルダーレジスト
の片面塗布に因る基板の反りを防止することができる。
かかる本発明で使用する封止樹脂に対して剥離性を呈す
るソルダーレジストとしては、シリコーンオイル等の剥
離剤が混合されているソルダーレジストが好適である。
尚、本発明において言う、「基板に対する密着性」を有
するソルダレジストとは、半導体素子と導体パターンと
の接続や樹脂封止等の各操作の際に、基板と塗布したソ
ルダレジストとの間に剥離が生じないことをいい、「封
止樹脂に対する剥離性」を有するソルダーレジストと
は、樹脂封止が終了しランナー樹脂を剥離する際に、ソ
ルダーレジストが塗布されたランナー樹脂を基板のラン
ナー部から完全に剥離できることをいう。In the present invention having such a constitution, by using the ultraviolet rays that have passed through the quartz glass as the rays of the ultraviolet rays or the like with which the solder resist is irradiated, the wavelengths of the ultraviolet rays to be irradiated can be made uniform. Further, after mounting the semiconductor element on the substrate, at least the runner portion of the substrate and the semiconductor element are covered with a mask, and the solder resist is irradiated with light rays such as ultraviolet rays, or before mounting the semiconductor element on the substrate, at least the substrate By covering the runner part with a mask and irradiating the solder resist with light rays such as ultraviolet rays, it is possible to easily convert only the solder resist applied to the sealing part to a solder resist that exhibits adhesion to the sealing resin. it can. It is effective to irradiate such light rays such as ultraviolet rays while heating the substrate. Furthermore, by using a resin substrate as a substrate, it is possible to reduce the weight of the obtained semiconductor device, and when a resin substrate is adopted, when a semiconductor element is mounted on the other surface of the substrate, Except for the external connection terminal pads to which external connection terminals such as solder balls are mounted, by applying a solder resist that has both adhesiveness to the substrate and releasability to the sealing resin, it is possible to apply the solder resist on one side. The warp of the substrate can be prevented.
As the solder resist exhibiting releasability with respect to the sealing resin used in the present invention, a solder resist mixed with a releasing agent such as silicone oil is suitable.
In the present invention, the term “solder resist having“ adhesion to the substrate ”” means that the solder resist is applied between the substrate and the applied solder resist during each operation such as connection between the semiconductor element and the conductor pattern and resin sealing. It means that peeling does not occur, and the solder resist having "peelability with respect to the sealing resin" is the runner resin coated with the solder resist when the resin sealing is completed and the runner resin is peeled off. It means that it can be completely peeled off.
【０００７】[0007]
【作用】本発明によれば、半導体素子を搭載する基板の
搭載面の略全面に亘って、基板に対して密着性を呈し且
つ封止樹脂に対して剥離性を呈するソルダーレジストを
塗布することによって、基板面に形成された導体パター
ン等を実質的に空気から遮断できる。その後、樹脂封止
される基板の封止部分に塗布され、封止樹脂に対して剥
離性を呈するソルダーレジストに紫外線等の光線を照射
することによって、封止部分のソルダーレジストを封止
樹脂に対して密着性のソルダーレジストに変換でき、封
止樹脂と基板面との密着を図ることができる。しかも、
基板のランナー部に塗布されたソルダーレジストは、紫
外線等の光線の照射がなされておらず、予めランナー部
に金めっきを施した場合と同程度の剥離性を封止樹脂に
対して呈する。このため、予めランナー部に金めっきを
施さなくても、樹脂封止層と共に形成されたランナー樹
脂をランナー部から容易に剥離して除去できる。According to the present invention, a solder resist exhibiting adhesion to the substrate and peeling property from the sealing resin is applied over substantially the entire mounting surface of the substrate on which the semiconductor element is mounted. Thus, the conductor pattern and the like formed on the substrate surface can be substantially shielded from the air. After that, the solder resist applied to the sealing portion of the substrate to be resin-sealed and irradiating the solder resist exhibiting releasability with respect to the sealing resin with light rays such as ultraviolet rays changes the solder resist in the sealing portion into the sealing resin. On the other hand, it can be converted into an adhesive solder resist, and the sealing resin and the substrate surface can be brought into close contact with each other. Moreover,
The solder resist applied to the runner portion of the substrate is not irradiated with light rays such as ultraviolet rays, and exhibits the same releasability to the sealing resin as when the runner portion is gold-plated in advance. Therefore, the runner resin formed together with the resin sealing layer can be easily peeled and removed from the runner portion without gold plating on the runner portion in advance.
【０００８】[0008]
【実施例】本発明を図面によって更に詳細に説明する。
図１は、本発明の一実施例に係る半導体装置の製造工程
の一部を説明するための説明図である。本実施例におい
ては、先ず、図１に示す様に、ＢＴレジン等から成る樹
脂製基板２０（以下、単に基板２０と称する）の一面側
に、導体パターン２２、２２・・及び半導体素子を搭載
する搭載部２４を形成すると共に、基板２０の他面側
に、導体パターン２２、２２・・と内壁面にスルーホー
ルめっきが施されたスルーホール２６、２６・・によっ
て電気的に接続された外部接続端子用パッド２８、２８
・・を形成する。本実施例の基板２０は、図７に示す様
に、複数個の半導体装置１０が形成される短冊状のもの
を使用した。かかる導体パターン２２のボンディング部
３２、３２、搭載部２４、及び外部接続端子用パッド２
８を除き、基板２０の両面の略全面にソルダーレジスト
をスクリーン印刷等によって塗布し、ソルダーレジスト
層３０を形成する。このソルダーレジスト層３０の形成
によって、導体パターン２２等を実質的に空気から遮断
することができる。本実施例においては、ソルダーレジ
スト層３０を形成するソルダーレジストは、シリコーン
オイル等の離型剤が混合されており、エポキシ樹脂等の
封止樹脂に対する剥離性と基板２０に対する密着性とを
併有するものである。尚、導体パターン２２、搭載部２
４、及び外部接続端子用パッド２８は、基板２０の両面
に貼着された銅箔等の金属箔にエッチングを施すことに
よって、或いはスパッタリングや蒸着等によって形成で
き、スルーホール２６は所定箇所にドリル等で穿設され
た穿設孔の内壁面に無電解めっき等によるスルーホール
めっきを施すことによって形成できる。The present invention will be described in more detail with reference to the drawings.
FIG. 1 is an explanatory diagram for explaining a part of a manufacturing process of a semiconductor device according to an embodiment of the present invention. In the present embodiment, first, as shown in FIG. 1, the conductor patterns 22, 22, ... And semiconductor elements are mounted on one surface side of a resin substrate 20 (hereinafter simply referred to as a substrate 20) made of BT resin or the like. The mounting portion 24 to be formed is formed and is electrically connected to the other surface side of the substrate 20 by the conductor patterns 22, 22 ... And the through holes 26, 26 .. Connection terminal pads 28, 28
.. is formed. As the substrate 20 of this embodiment, as shown in FIG. 7, a strip-shaped substrate on which a plurality of semiconductor devices 10 are formed is used. Bonding portions 32, 32 of the conductor pattern 22, the mounting portion 24, and the external connection terminal pad 2
Except for No. 8, a solder resist is applied to substantially the entire surfaces of both sides of the substrate 20 by screen printing or the like to form a solder resist layer 30. By forming the solder resist layer 30, the conductor pattern 22 and the like can be substantially shielded from the air. In the present embodiment, the solder resist forming the solder resist layer 30 is mixed with a release agent such as silicone oil, and has both releasability with respect to the sealing resin such as epoxy resin and adhesion with the substrate 20. It is a thing. The conductor pattern 22 and the mounting portion 2
4, and the pads 28 for external connection terminals can be formed by etching a metal foil such as a copper foil attached to both surfaces of the substrate 20, or by sputtering or vapor deposition, and the through hole 26 is drilled at a predetermined position. It can be formed by performing through-hole plating such as electroless plating on the inner wall surface of the perforated hole formed by the above method.
【０００９】ソルダーレジスト層３０が両面に形成され
た図１に示す基板２０には、金属部分が露出する導体パ
ターン２２のボンディング部３２、搭載部２４、及び外
部接続端子用パッド２８に、電解めっきによって金めっ
きを施す（電解めっきによるニッケルめっきを施した
後、金めっきを施すことが好ましい）。この金めっきに
よって、ソルダーレジスト層３０から露出した導体パタ
ーン２２等の露出部分を保護できる。かかる金めっきが
施された搭載部２４に、図２に示す様に、半導体素子３
４をエポキシ系の銀ペースト等の接着剤によって固着し
て搭載した後、半導体素子３４と導体パターン２２のボ
ンディング部３２とをワイヤ３６によって電気的に接続
する。この半導体素子３４の搭載は加熱雰囲気下で行わ
れ、且つワイヤ３６による接続も基板２０を加熱しつつ
なされる。尚、搭載部２４の金めっきは部分的でもよ
く、この場合には、金めっきを施す部分を除く搭載部２
４の表面にソルダーレジスト層３０を形成する。On the substrate 20 shown in FIG. 1 having the solder resist layer 30 formed on both sides thereof, electrolytic plating is performed on the bonding portion 32 of the conductor pattern 22 where the metal portion is exposed, the mounting portion 24, and the external connection terminal pad 28. Gold plating is performed (it is preferable to perform gold plating after nickel plating by electrolytic plating). By this gold plating, the exposed portion such as the conductor pattern 22 exposed from the solder resist layer 30 can be protected. As shown in FIG. 2, the semiconductor element 3 is mounted on the mounting portion 24 plated with gold.
4 is fixed and mounted by an adhesive such as an epoxy-based silver paste, and then the semiconductor element 34 and the bonding portion 32 of the conductor pattern 22 are electrically connected by a wire 36. The mounting of the semiconductor element 34 is performed in a heating atmosphere, and the connection by the wire 36 is also performed while heating the substrate 20. The gold plating of the mounting portion 24 may be partial, and in this case, the mounting portion 2 excluding the portion where the gold plating is applied.
A solder resist layer 30 is formed on the surface of No. 4.
【００１０】本実施例では、半導体素子３４の搭載及び
ワイヤ３６による接続が完了した後、基板２０上に形成
されたソルダーレジスト層３０のうち、封止樹脂によっ
て封止される封止部分に形成されたソルダーレジスト層
に対し、紫外線を照射して封止樹脂に対して密着性を呈
するソルダーレジスト層に変換する。この様に、紫外線
を照射することによって、ソルダーレジスト層３０を封
止樹脂に対し密着性を呈するソルダーレジスト層に変換
できる詳細な理由は未だ明確ではないが、以下の様に推
察できる。つまり、ソルダーレジスト中に混合されたシ
リコーンオイル等の離型剤がソルダーレジスト層３０の
表面に滲み出しているため、ソルダーレジスト層３０と
封止樹脂との密着性を低下させる。このため、ソルダー
レジスト層３０の表面に滲み出したシリコーンオイル等
の離型剤を紫外線の照射で分解することによって、両者
の密着性を向上できる。尚、ここで言う「封止樹脂に対
し密着性を呈するソルダーレジスト層」とは、樹脂封止
が終了して形成された封止樹脂層と繋がっているランナ
ー樹脂を基板のランナー部から剥離し、封止樹脂層から
もぎ取る際に、封止樹脂層がソルダーレジスト層から剥
離されないことを言う。In this embodiment, after the mounting of the semiconductor element 34 and the connection with the wires 36 are completed, the solder resist layer 30 formed on the substrate 20 is formed on the sealing portion sealed by the sealing resin. The solder resist layer thus formed is irradiated with ultraviolet rays to be converted into a solder resist layer exhibiting adhesion to the sealing resin. As described above, the detailed reason why the solder resist layer 30 can be converted into the solder resist layer exhibiting adhesiveness to the sealing resin by irradiating the ultraviolet rays is not clear yet, but it can be inferred as follows. That is, since the release agent such as silicone oil mixed in the solder resist oozes to the surface of the solder resist layer 30, the adhesiveness between the solder resist layer 30 and the sealing resin is reduced. Therefore, the adhesiveness between the two can be improved by decomposing the release agent such as silicone oil exuding on the surface of the solder resist layer 30 by irradiating with ultraviolet rays. The "solder resist layer exhibiting adhesion to the sealing resin" here means that the runner resin connected to the sealing resin layer formed after the resin sealing is completed is peeled off from the runner portion of the substrate. It means that the sealing resin layer is not peeled from the solder resist layer when stripped from the sealing resin layer.
【００１１】かかる紫外線の照射は、図３に示す様に、
石英ガラス板３８を透過した紫外線を照射することによ
って、シリコーンオイル等の離型剤を分解する特定波長
の紫外線をソルダーレジスト層に照射することができ
る。本実施例では、２５４〜２５７ｎｍの紫外線を照射
した。また、紫外線の照射を、基板２０の封止部分に形
成されたソルダーレジスト層４４のみに行うべく、樹脂
封止される封止部分を除く基板面を金属製のマスク３０
で覆うと共に、搭載された半導体素子３４もマスクによ
って覆い紫外線の照射から保護する。本実施例では、半
導体素子３５を覆うマスクとして、石英ガラス板３８の
半導体素子３５と対向する位置に、クロム(Cr)をスパッ
タして形成してクロム膜から成るマスク４０を設けた。
かかるマスク４０、４２によって、図６に示す様に、マ
スク４０とマスク４２との間のソルダーレジスト層４
４、つまり封止部分に形成されたソルダーレジスト層４
４のみに紫外線を照射できる。一方、ランナー樹脂８が
形成される基板２０のランナー部５１は、図６に示す様
に、マスク４２によって覆われており、紫外線の照射か
ら保護されている。尚、基板２０のランナー部５１のみ
をマスクによって覆って、紫外線の照射を行ってもよ
い。Irradiation of such ultraviolet rays, as shown in FIG.
By irradiating the ultraviolet rays that have passed through the quartz glass plate 38, it is possible to irradiate the solder resist layer with ultraviolet rays having a specific wavelength that decomposes the release agent such as silicone oil. In this embodiment, ultraviolet rays of 254 to 257 nm are irradiated. Further, in order to irradiate the ultraviolet rays only to the solder resist layer 44 formed on the sealing portion of the substrate 20, the substrate surface except the sealing portion to be resin-sealed has a metal mask 30.
In addition to being covered with, the mounted semiconductor element 34 is also covered with a mask to protect it from the irradiation of ultraviolet rays. In this embodiment, as a mask for covering the semiconductor element 35, a mask 40 made of a chromium film formed by sputtering chromium (Cr) is provided at a position facing the semiconductor element 35 on the quartz glass plate 38.
With such masks 40 and 42, as shown in FIG. 6, the solder resist layer 4 between the mask 40 and the mask 42 is formed.
4, that is, the solder resist layer 4 formed in the sealing portion
Only 4 can be irradiated with ultraviolet rays. On the other hand, the runner portion 51 of the substrate 20 on which the runner resin 8 is formed is covered with a mask 42 as shown in FIG. 6, and is protected from the irradiation of ultraviolet rays. Note that only the runner portion 51 of the substrate 20 may be covered with a mask to irradiate the ultraviolet rays.
【００１２】ソルダーレジスト層中に混入されたシリコ
ーンオイル等の離型剤は、加熱によってソルダーレジス
ト層の表面に滲み出やすいため、半導体素子３４の搭載
やワイヤボンディング等の加熱を伴う工程を完了した
後、図３に示す紫外線照射を行う。また、紫外線照射の
際にも、基板２０を加熱しつつ紫外線照射を行うことに
よって、ソルダーレジスト層中のシリコーンオイル等の
離型剤を可及的にソルダーレジスト層４４の表面に滲み
出させて分解でき、その後の加熱工程でソルダーレジス
ト層４４の表面に滲み出るシリコーンオイル等の離型剤
を可及的に少なくできる。このため、本実施例では、１
００℃の加熱を行いつつ紫外線照射を２〜３分間行っ
た。Since the release agent such as silicone oil mixed in the solder resist layer easily exudes to the surface of the solder resist layer by heating, the steps involving heating such as mounting the semiconductor element 34 and wire bonding are completed. After that, the ultraviolet irradiation shown in FIG. 3 is performed. Also, during the ultraviolet irradiation, the release agent such as silicone oil in the solder resist layer is exuded to the surface of the solder resist layer 44 as much as possible by performing the ultraviolet irradiation while heating the substrate 20. It is possible to decompose, and it is possible to reduce the release agent such as silicone oil that exudes to the surface of the solder resist layer 44 in the subsequent heating step as much as possible. Therefore, in this embodiment, 1
Ultraviolet irradiation was performed for 2 to 3 minutes while heating at 00 ° C.
【００１３】紫外線照射を施した後、基板２０に搭載さ
れた半導体素子３４及び紫外線照射を行ったソルダーレ
ジスト層４４の部分を樹脂封止する。かかる樹脂封止
は、図４に示す様に、封止金型の上金型４６と下金型４
７との型閉によって、半導体素子３４及び紫外線照射を
行ったソルダーレジスト層４４をキャビティ５０内に配
置して行う。この際に、上金型４６に設けられた樹脂注
入路５２からエポキシ樹脂等の封止樹脂を、エアベント
４８から空気を封止金型外に排出しつつキャビティ５０
内に充填し、半導体素子３４を封止する樹脂封止層を形
成する。この樹脂封止層は、ソルダーレジスト層４４が
封止樹脂に対して密着性を有するため、ソルダーレジス
ト層４４と密着することができる。After the UV irradiation, the semiconductor element 34 mounted on the substrate 20 and the portion of the UV-irradiated solder resist layer 44 are resin-sealed. As shown in FIG. 4, such resin encapsulation includes the upper die 46 and the lower die 4 of the sealing die.
By closing the mold with 7, the semiconductor element 34 and the solder resist layer 44 irradiated with ultraviolet rays are arranged in the cavity 50. At this time, while the sealing resin such as epoxy resin is discharged from the resin injection path 52 provided in the upper mold 46 and the air is discharged from the air vent 48 to the outside of the sealing mold, the cavity 50 is discharged.
A resin sealing layer for filling the inside and sealing the semiconductor element 34 is formed. This resin sealing layer can adhere to the solder resist layer 44 because the solder resist layer 44 has adhesion to the sealing resin.
【００１４】また、上金型４６の樹脂注入路５２は、紫
外線照射の際に、マスク４２で覆われて封止樹脂に対し
て剥離性を呈するソルダーレジスト層３０から成るラン
ナー部５１上に位置する。このため、樹脂封止が完了し
て封止金型の上金型４６と下金型４７との型開がなされ
ると、図７と同様に、複数個の半導体装置１０が設けら
れた基板２０が取り出される。本実施例においては、こ
の半導体装置１０には、基板２０のランナー部５１上に
ランナー樹脂８が形成されているが、ランナー部５１は
封止樹脂に対して剥離性を呈するソルダーレジスト層３
０が形成されている。このため、ランナー部５１は、ラ
ンナー樹脂８に対し、ランナー部５１に金めっきを施し
た場合と同程度の剥離性を呈し、ランナー樹脂８をラン
ナー部５１から容易に剥離して除去できる。従って、予
めランナー部５１に金めっきを施すことを要せず、ラン
ナー樹脂８を除去して得られた半導体装置１０の外観も
良好である。尚、樹脂封止の際に、ソルダーレジスト層
３０、４４の加熱時間は、極めて短時間であるため、ソ
ルダーレジスト層４４の表面に滲み出すシリコーンオイ
ル等の離型剤を実質的に無視できる。Further, the resin injection path 52 of the upper mold 46 is located on the runner portion 51 composed of the solder resist layer 30 which is covered with the mask 42 and exhibits peeling property with respect to the sealing resin at the time of ultraviolet irradiation. To do. Therefore, when the resin encapsulation is completed and the upper die 46 and the lower die 47 of the encapsulation die are opened, a substrate having a plurality of semiconductor devices 10 is provided, as in FIG. 7. 20 is taken out. In the present embodiment, in the semiconductor device 10, the runner resin 8 is formed on the runner portion 51 of the substrate 20, but the runner portion 51 has the solder resist layer 3 exhibiting releasability from the sealing resin.
0 is formed. Therefore, the runner portion 51 exhibits the releasability of the runner resin 8 to the same extent as when the runner portion 51 is plated with gold, and the runner resin 8 can be easily peeled and removed from the runner portion 51. Therefore, it is not necessary to perform gold plating on the runner portion 51 in advance, and the appearance of the semiconductor device 10 obtained by removing the runner resin 8 is also good. Since the solder resist layers 30 and 44 are heated for a very short time during resin sealing, the release agent such as silicone oil oozing on the surface of the solder resist layer 44 can be substantially ignored.
【００１５】ランナー樹脂８を除去した後、図５に示す
様に、半導体素子３４が搭載された搭載面の反対面に形
成された外部接続端子用パッド２８、２８・・に、外部
接続端子としてのはんだボール５６、５６・・を装着す
る。はんだボール５６の装着は、外部接続端子用パッド
２８にはんだボール５６を載置し、リフロー処理を施す
ことによって、はんだボール５６を外部接続端子用パッ
ド２８に装着することができる。このリフロー処理にお
ける加熱時間も、極めて短時間であるため、ソルダーレ
ジスト層４４の表面に滲み出すシリコーンオイル等の離
型剤を実質的に無視できる。かかる一枚の基板２０に連
なって形成された複数個の半導体装置１０は、必要に応
じて個片に分割することができる。尚、はんだボール５
６としては、銅ボールの表面がはんだめっき等で形成さ
れたはんだ皮膜によって覆われているものであってもよ
い。After removing the runner resin 8, as shown in FIG. 5, the external connection terminal pads 28, 28, ... Formed on the surface opposite to the mounting surface on which the semiconductor element 34 is mounted are used as external connection terminals. Attach the solder balls 56, 56 ,. To mount the solder balls 56, the solder balls 56 can be mounted on the pads 28 for external connection terminals by placing the solder balls 56 on the pads 28 for external connection terminals and performing a reflow process. Since the heating time in this reflow process is also extremely short, the release agent such as silicone oil that oozes out onto the surface of the solder resist layer 44 can be substantially ignored. The plurality of semiconductor devices 10 formed in series on one substrate 20 can be divided into individual pieces as necessary. Solder balls 5
As 6, the surface of the copper ball may be covered with a solder film formed by solder plating or the like.
【００１６】以上、説明してきた本実施例において、封
止樹脂に対して剥離性を呈するソルダーレジスト層３０
に紫外線を照射し、封止樹脂に対して密着性を呈するソ
ルダーレジスト層４４に変換しているが、ソルダーレジ
スト層３０の表面に滲み出すシリコーンオイル等の離型
剤を分解できる照射光であれば使用でき、例えばレーザ
ー光を使用することができる。また、本実施例では、基
板２０の搭載部２４に半導体素子３４を搭載した後、紫
外線の照射を行っているが、半導体素子３４の搭載前に
紫外線の照射を行ってもよい。この場合には、半導体素
子３４が搭載されておらず、石英ガラス板３８に形成し
たクロム膜から成るマスク４０で半導体素子３４を覆う
ことを要しないため、封止部分を除く基板面を金属製の
マスク３０で覆い、封止部分に紫外線の照射を行う。更
に、外部接続端子としてはんだボール５６を使用した
が、リードピンを使用してもよい。尚、本実施例におい
ては、一枚の基板２０に複数個の半導体装置１０を形成
した場合について説明してきたが、予め個片に分割され
た基板上に半導体素子を搭載し、樹脂封止して半導体装
置１０を形成する場合にも本実施例を適用できることは
勿論のことである。In the embodiment described above, the solder resist layer 30 exhibiting releasability from the sealing resin.
UV rays are radiated onto the solder resist layer 44 to convert it into a solder resist layer 44 that exhibits adhesiveness to the sealing resin. However, if the irradiation light is capable of decomposing the release agent such as silicone oil oozing on the surface of the solder resist layer 30. Can be used, for example, laser light can be used. Further, in the present embodiment, the semiconductor element 34 is mounted on the mounting portion 24 of the substrate 20 and then the ultraviolet irradiation is performed, but the ultraviolet irradiation may be performed before the semiconductor element 34 is mounted. In this case, since the semiconductor element 34 is not mounted and it is not necessary to cover the semiconductor element 34 with the mask 40 formed of the chromium film formed on the quartz glass plate 38, the substrate surface except the sealing portion is made of metal. The mask 30 is covered with the mask 30, and the sealed portion is irradiated with ultraviolet rays. Furthermore, although the solder ball 56 is used as the external connection terminal, a lead pin may be used. In this embodiment, the case where a plurality of semiconductor devices 10 are formed on one substrate 20 has been described. However, semiconductor elements are mounted on a substrate divided into pieces in advance and resin-sealed. It goes without saying that this embodiment can be applied to the case where the semiconductor device 10 is formed.
【００１７】[0017]
【発明の効果】本発明によれば、ランナー樹脂が形成さ
れる基板のランナー部に予め金めっきを施すことを要し
ないため、半導体装置の機能に関与しない部分に高価な
金めっきを施すことを省略でき、半導体装置の製造コス
トの低減と半導体装置の外観の向上とを図ることができ
る。According to the present invention, since it is not necessary to preliminarily perform gold plating on the runner portion of the substrate on which the runner resin is formed, it is possible to perform expensive gold plating on the portion that does not affect the function of the semiconductor device. This can be omitted, and the manufacturing cost of the semiconductor device can be reduced and the appearance of the semiconductor device can be improved.
【図１】本発明の一実施例に係る半導体装置の製造工程
の一工程を説明するための説明図である。FIG. 1 is an explanatory diagram for explaining one step of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例に係る半導体装置の製造工程
の一工程を説明するための説明図である。FIG. 2 is an explanatory diagram for explaining one step in the manufacturing process of the semiconductor device according to the embodiment of the present invention.
【図３】本発明の一実施例に係る半導体装置の製造工程
の一工程を説明するための説明図である。FIG. 3 is an explanatory diagram illustrating a step of manufacturing the semiconductor device according to the embodiment of the present invention.
【図４】本発明の一実施例に係る半導体装置の製造工程
の一工程を説明するための説明図である。FIG. 4 is an explanatory diagram illustrating a step of manufacturing the semiconductor device according to the embodiment of the present invention.
【図５】本発明の一実施例に係る半導体装置の製造工程
の一工程を説明するための説明図である。FIG. 5 is an explanatory diagram illustrating a step of manufacturing the semiconductor device according to the embodiment of the present invention.
【図６】紫外線照射の際に、マスクの基板に対する被着
状態を説明するための説明図である。FIG. 6 is an explanatory diagram for explaining a state in which a mask is adhered to a substrate during ultraviolet irradiation.
【図７】封止金型から取り出された基板の状態を説明す
る説明図である。FIG. 7 is an explanatory diagram illustrating a state of the substrate taken out from the sealing mold.
２ 樹脂封止層 ８ ランナー樹脂 １０ 半導体装置 ２０ 基板 ２２ 導体パターン ２４ 半導体素子の搭載部 ２６ スルーホール ２８ 外部端子用パッド ３０、４４ ソルダーレジスト層 ３２ ボンディング部 ３４ 半導体素子 ３６ ワイヤ ３８ 石英ガラス板 ４０、４２ マスク ４６ 上金型 ４７ 下金型 ５０ キャビティ ５１ ランナー部 ５２ 樹脂注入路 ５６ はんだボール（外部接続端子） 2 resin sealing layer 8 runner resin 10 semiconductor device 20 substrate 22 conductor pattern 24 semiconductor element mounting portion 26 through hole 28 external terminal pad 30, 44 solder resist layer 32 bonding portion 34 semiconductor element 36 wire 38 quartz glass plate 40, 42 Mask 46 Upper Mold 47 Lower Mold 50 Cavity 51 Runner 52 Resin Injection Path 56 Solder Ball (External Connection Terminal)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 林 浩一郎 長野県長野市大字栗田字舎利田711番地 新光電気工業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Koichiro Hayashi Inventor Koichiro Hayashi 711 Rita, Kurita, Nagano, Nagano City Shinko Electric Industry Co., Ltd.
Claims (8)
置された封止金型のキャビティ内に、前記基板の一面に
形成されたランナー部に沿って配設された封止金型の樹
脂注入通路から封止樹脂を注入し、半導体素子を樹脂封
止して半導体装置を製造する際に、 該基板の一面に形成された半導体素子の搭載部及び搭載
部近傍に形成された導体パターンのボンディング部を除
く基板面に、基板に対する密着性と封止樹脂に対する剥
離性とを併有するソルダーレジストを塗布した後、 前記基板の搭載部に搭載された半導体素子と導体パター
ンのボンディング部とを電気的に接続すると共に、 前記基板に塗布された前記ソルダーレジストのうち、基
板のランナー部に塗布されたソルダーレジストを除く、
少なくとも樹脂封止される基板の封止部分に塗布された
ソルダーレジストを、紫外線等の光線を照射して封止樹
脂に対し密着性を呈するソルダーレジストに変換し、 次いで、前記基板に搭載された半導体素子が配置された
封止金型のキャビティ内に、基板のランナー部に沿って
配設された封止金型の樹脂注入路から封止樹脂を注入す
ることを特徴とする半導体装置の製造方法。1. A resin for a sealing die, which is disposed along a runner portion formed on the one surface of the substrate in a cavity of the sealing die in which a semiconductor element mounted on one surface of the substrate is arranged. When a semiconductor device is manufactured by injecting a sealing resin from an injection passage and sealing a semiconductor element with a resin, a semiconductor element mounting portion formed on one surface of the substrate and a conductor pattern formed in the vicinity of the mounting portion are formed. After applying a solder resist having both adhesiveness to the substrate and releasability to the sealing resin to the substrate surface excluding the bonding portion, the semiconductor element mounted on the mounting portion of the substrate and the bonding portion of the conductor pattern are electrically connected. Of the solder resist applied to the substrate, except the solder resist applied to the runner portion of the substrate,
At least the solder resist applied to the sealing portion of the substrate to be resin-sealed is converted into a solder resist that exhibits adhesiveness to the sealing resin by irradiating light rays such as ultraviolet rays, and then mounted on the substrate. Manufacturing of a semiconductor device characterized by injecting a sealing resin into a cavity of a sealing die in which a semiconductor element is arranged from a resin injection path of the sealing die arranged along a runner portion of a substrate. Method.
て、石英ガラスを透過した紫外線を用いる請求項１記載
の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein ultraviolet rays that have passed through quartz glass are used as the light rays for irradiating the solder resist.
とも基板のランナー部及び半導体素子をマスクによって
覆い、ソルダーレジストに光線の照射を行う請求項１又
は請求項２記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein after mounting the semiconductor element on the substrate, at least the runner portion of the substrate and the semiconductor element are covered with a mask, and the solder resist is irradiated with light rays.
くとも基板のランナー部をマスクによって覆い、ソルダ
ーレジストに光線の照射を行う請求項１又は請求項２記
載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein before the semiconductor element is mounted on the substrate, at least the runner portion of the substrate is covered with a mask and the solder resist is irradiated with light rays.
項１〜４のいずれか一項記載の半導体装置の製造方法。5. The method for manufacturing a semiconductor device according to claim 1, wherein the irradiation of the light beam is performed while heating the substrate.
〜５のいずれか一項記載の半導体装置。6. The resin substrate is used as the substrate.
6. The semiconductor device according to any one of items 5 to 5.
面に、はんだボール等の外部接続端子が装着される外部
接続端子用パッドを除き、基板に対する密着性と封止樹
脂に対する剥離性とを併有するソルダーレジストを塗布
する請求項１〜６のいずれか一項記載の半導体装置の製
造方法。7. Except for an external connection terminal pad on which an external connection terminal such as a solder ball is mounted on the other surface of a substrate on which a semiconductor element is mounted on one surface, adhesion to the substrate and releasability to a sealing resin are provided. 7. The method for manufacturing a semiconductor device according to claim 1, wherein a solder resist having both is applied.
ーレジストとして、シリコーンオイル等の離型剤が混合
されたソルダーレジストを使用する請求項１〜７のいず
れか一項記載の半導体装置の製造方法。8. The semiconductor device according to claim 1, wherein a solder resist mixed with a release agent such as silicone oil is used as the solder resist exhibiting releasability from the sealing resin. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7130308A JPH08330340A (en) | 1995-05-29 | 1995-05-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7130308A JPH08330340A (en) | 1995-05-29 | 1995-05-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08330340A true JPH08330340A (en) | 1996-12-13 |
Family
ID=15031220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7130308A Pending JPH08330340A (en) | 1995-05-29 | 1995-05-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08330340A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113737128A (en) * | 2017-01-31 | 2021-12-03 | 堺显示器制品株式会社 | Vapor deposition mask, and method for manufacturing organic semiconductor element |
-
1995
- 1995-05-29 JP JP7130308A patent/JPH08330340A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113737128A (en) * | 2017-01-31 | 2021-12-03 | 堺显示器制品株式会社 | Vapor deposition mask, and method for manufacturing organic semiconductor element |
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