JPH08298292A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To provide a semiconductor integrated circuit capable of reducing a chip area of an internal circuit forming region and preventing a latch-up phenomenon in the internal circuit forming region. CONSTITUTION: A flow of substrate current to the internal circuit from an diffusion element connected to an input terminal or output terminal can be interrupted by forming a diffusion element to be connected to an output terminal or an input terminal at the side (region 2) coming into contact with a region 1 where an input terminal or output terminal is formed, and also forming diffusion elements except the diffusion element formed in the region 2 at the side (region 3) coming into contact with the internal circuit forming region 4 among the diffusion elements constituting the input circuit or output circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to prevention of a latch-up phenomenon in an internal circuit formation region of a CMOS integrated circuit.

[0002]

2. Description of the Related Art The cause of latch-up phenomenon is that when electric charge flows from the outside through an input terminal or an output terminal, the electric charge flows into the substrate from a diffusion region adjacent to the input terminal or the output terminal and becomes a substrate current, which is parasitic. This is for operating the transistor.

A conventional semiconductor integrated circuit will be described below with reference to the drawings. FIG. 4 shows an arrangement example of a conventional semiconductor integrated circuit.

In FIG. 4, 5 is an input terminal or output terminal forming region, 6 is an input circuit or output circuit forming region,
Reference numeral 7 indicates an internal circuit formation region. In the conventional semiconductor integrated circuit, the latch-up phenomenon prevention measures are provided in the input circuit or output circuit formation region 6 and the internal circuit formation region 7, respectively.

The conventional measures for preventing the latch-up phenomenon will be described below. In each of the formation region 6 of the input circuit or the output circuit and the formation region 7 of the internal circuit, a field effect type P channel MOS transistor (hereinafter referred to as P channel MOSFET) and a field effect type N channel MO are formed.
An S-transistor (hereinafter referred to as an N-channel MOSFET) is formed separately, and a diffusion region having the same conductivity type as the substrate is formed between the S-transistor and the substrate current to be absorbed in the diffusion region.
The electrical path to the FET is cut off, and the parasitic transistor is prevented from operating to take a latch-up countermeasure.

[0006]

However, in the conventional semiconductor integrated circuit, as a countermeasure against latch-up, the P-channel MOSFET and the N-channel MO are formed not only in the input circuit or output circuit formation region but also in the internal circuit formation region.
Since the SFET and the SFET are separately formed, it is difficult to reduce the semiconductor substrate (chip) area. Further, although the substrate current is absorbed in the diffusion region to prevent the latch-up, there has been a problem that the conventional latch-up measure cannot sufficiently absorb the substrate current.

The present invention solves the above problems, and an object of the present invention is to provide a semiconductor integrated circuit which can prevent the latch-up phenomenon in the internal circuit formation region and reduce the chip area of the internal circuit formation region. To do.

[0008]

SUMMARY OF THE INVENTION The present invention focuses on the formation of a parasitic transistor that causes a latch-up phenomenon, and a region (first region) where an input terminal or an output terminal is formed on a semiconductor substrate and an internal circuit. In an area (second area) in which an input circuit or an output circuit is formed between the area in which an input circuit or an output circuit is formed (third area), an input terminal or an output terminal among diffusion elements forming the input circuit or the output circuit All the diffusion elements connected to the input terminal or the output terminal are formed in the area on the side in contact with the area where the input terminal or the output terminal is formed (the fourth area). All the diffusion elements except the connected diffusion element are arranged in a region (fifth region) on the side in contact with a region where an internal circuit is formed. In the present invention, since the diffusion element causing the parasitic transistor is not formed in the region in contact with the internal circuit, it is possible to block the substrate current from flowing into the internal circuit from the diffusion element connected to the input terminal or the output terminal. Is.

[0009]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings.

FIG. 1 is a layout view showing an embodiment of the present invention, in which 1 is an input terminal or output terminal forming region, and 2 is an input circuit or a diffusion element forming an output circuit, which is connected to an input terminal or an output terminal. Regions for forming diffusion elements, 3
In the isolation region, all of the diffusion elements forming the input circuit or the output circuit except the diffusion element connected to the input terminal or the output terminal are formed. Reference numeral 4 indicates an internal circuit formation region.

An example of the input circuit or the output circuit formed in the region 2 or the isolation region 3 forming the diffusion element connected to the input terminal or the output terminal will be described below with reference to FIGS. 2 and 3.

FIG. 2 is a diagram showing an example in which the input circuit is composed of a CMOS inverter. Reference numeral 8 is an input terminal, and 14 is a signal line connected to an internal circuit. P-channel MOSFET
12 and N-channel MOSFET 13 constitute a CMOS inverter, and P-channel MOSFET 1
The source of 2 is connected to the power source, and the source of the N-channel MOSFET 13 is grounded. And P channel MOS
The drains of the FET 12 and the N-channel MOSFET 13 are connected to the signal line 14 connecting to the internal circuit. Moreover, the gates of the P-channel MOSFET 12 and the N-channel MOSFET 13 are connected to the input terminal 8. A diode 9 is formed between the source of the P-channel MOSFET 12 and the input terminal 8, and a diode 10 is formed between the source of the N-channel MOSFET 13 and the input terminal 8. Furthermore, P channel MO
A diffusion resistor 11 is formed between the gates of the SFET 12 and the N-channel MOSFET 13 and the input terminal 8.

FIG. 3 is a diagram showing an example in which the output circuit is composed of a CMOS inverter. Reference numeral 15 is an output terminal, and 21 is a signal line connected to an internal circuit. P channel MOSFE
CMOS with T19 and N-channel MOSFET 20
Inverter, P-channel MOSFET
The source of 19 is the power supply and the N-channel MOSFET 20
The source of is grounded. And P channel MO
The gates of the SFET 19 and the N-channel MOSFET 20 are connected to the signal line 21. In addition, P-channel MOSFET 19 and N-channel MOSFET
The drain of 20 is connected to the output terminal 15. A diode 16 is formed between the source of the P-channel MOSFET 19 and the output terminal 15, and the diode 16 is formed.
A diode 17 is formed between the source of the FET 20 and the output terminal 15. In addition, P channel MOSFE
A diffusion resistor 18 is formed between the drain of the T19 and the N-channel MOSFET 20 and the output terminal 15.

Although the input terminal and the output terminal are separately configured in FIGS. 2 and 3, the input terminal and the output terminal may be commonly used to configure the input / output terminal and the input circuit or the output circuit. No problem.

Next, using the example of the input circuit and the output circuit described with reference to FIGS. 2 and 3, the region 2 and the isolation region for forming the diffusion element connected to the input terminal or the output terminal shown in FIG. 1 are formed. The arrangement of No. 3 will be described in detail.

As described above, reference numeral 2 denotes a region for forming the diffusion element connected to the input terminal or the output terminal among the diffusion elements forming the input circuit or the output circuit, which constitutes the input circuit shown in FIG. In the diffusion element, the diodes 9 and 10 and the diffusion resistance 11 are incorporated. And
In the isolation region 3, a P-channel MOSFET 12 and an N-channel MOSFET 13 which are diffusion elements whose diffusion region is not directly connected to the input terminal 8 are formed.

Further, in the diffusion element constituting the output circuit shown in FIG. 3, the diodes 16, 17 and the diffusion resistance 18,
In addition, the drain portion of the P-channel MOSFET 19 and the drain portion of the N-channel MOSFET 20 correspond to the diffusion element in which the output terminal 15 and the diffusion region are connected, and form a diffusion element that connects each of these diffusion elements to the input terminal or the output terminal. Build in Area 2.

As described above, in the embodiment of the present invention, since the diffusion element connected to the input terminal or the output terminal is arranged and formed at a position separated from the internal circuit, the input terminal or the output terminal is connected to the internal circuit. No parasitic transistor is formed. As a result, the internal circuit forming region 4 acts to cut off the electrical path of the substrate current that causes the latch-up phenomenon, and the latch-up phenomenon hardly occurs in the internal circuit forming region 4. Moreover, the P-channel MOSFET and the N-channel M are provided as in the conventional latch-up phenomenon countermeasure
Since the OSFET is not formed separately but only the arrangement of the diffusion elements is limited, the chip area does not increase.

Further, if the input circuit or the output circuit is provided with the latch-up prevention measure as in the conventional technique, the area of the input circuit or the output circuit is the same as the conventional one, but the internal circuit is provided with the latch-up prevention measure. Since it is unnecessary, the chip area as a whole can be reduced. If the input circuit or the output circuit is provided with a latch-up prevention measure, the substrate current in the input circuit or the output circuit is considerably reduced as compared with the case where the latch-up prevention measure is not provided. As a result, a larger effect can be obtained as a countermeasure against the latch-up phenomenon in the internal circuit formation region 4.

[0020]

As described above, according to the present invention, since the internal circuit and the diffusion element connected to the input terminal or the output terminal are not in direct contact with each other, the diffusion element connected to the input terminal or the output terminal is internally connected. The inflow of the substrate current, which causes the latch-up phenomenon, can be cut off into the circuit, and the latch-up phenomenon is less likely to occur in the internal circuit formation region.

Further, if a countermeasure against the latch-up phenomenon is taken in the input circuit or output circuit forming region, the latch-up phenomenon in the internal circuit forming region is almost eliminated, and the latch-up phenomenon preventing measure need not be provided in the internal circuit forming region. It is also possible to reduce the area of the internal circuit.

[Brief description of drawings]

FIG. 1 is a layout drawing showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of an input circuit.

FIG. 3 is a diagram showing an example of an output circuit.

FIG. 4 is a layout drawing showing a conventional example.

[Explanation of symbols]

1 Input terminal or output terminal formation area 2 Area where diffusion element connected to input terminal or output terminal is formed 3 Separation area 4 Internal circuit formation area

Claims (2)

[Claims] 1. A first substrate having an input terminal formed on a semiconductor substrate.
Area, a second area in which an input circuit composed of a diode, a diffusion resistor, and a CMOS inverter is formed, and a third area in which an internal circuit is formed, and the second area is The second region has a fourth region in contact with the first region and a fifth region in contact with the third region, the second region being disposed between the first region and the third region. All of the diffusion elements forming the input circuit connected to the input terminal are arranged in the fourth region, and all the diffusion elements arranged in the fourth region of the input / output circuit are excluded. Disposing the diffusion element in the fifth region,
Of the drain portion and the source portion of the field-effect P-channel MOS transistor and the field-effect N-channel MOS transistor that form the inverter, the electrode of one type is compared with the electrode of the other type, and the first region is formed. A semiconductor integrated circuit, which is arranged on the side. 2. A first substrate having an output terminal formed on a semiconductor substrate.
Area, a second area in which an output circuit composed of a diode, a diffusion resistor, and a CMOS inverter is formed, and a third area in which an internal circuit is formed, and the second area is The second region has a fourth region in contact with the first region and a fifth region in contact with the third region, the second region being disposed between the first region and the third region. All the diffusion elements connected to the output terminal among the diffusion elements forming the output circuit are arranged in the fourth region, and all the diffusion elements arranged in the fourth region of the input / output circuit are excluded. Disposing the diffusion element in the fifth region,
Of the drain portion and the source portion of the field-effect P-channel MOS transistor and the field-effect N-channel MOS transistor that form the inverter, the electrode of one type is compared with the electrode of the other type, and the first region is formed. A semiconductor integrated circuit, which is arranged on the side.