JP3779256B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit technique for preventing electrostatic breakdown of a semiconductor device.
[0002]
[Prior art]
A first input protection circuit for leading positive surge charge applied to the signal input terminal from the outside to the power supply line; and a first input protection circuit for guiding negative surge charge applied to the signal input terminal from the outside to the ground line. 2. Description of the Related Art A semiconductor device (semiconductor integrated circuit) having two input protection circuits is known. Each of the first and second input protection circuits is composed of any one of a diode, a MOS transistor, and a bipolar transistor (see Patent Document 1).
[0003]
[Patent Document 1]
JP-A-9-139466
[Problems to be solved by the invention]
For example, a delay circuit can be configured by a large number of cascaded inverters. Each inverter includes a P channel MOS transistor and an N channel MOS transistor. If the first and second input protection circuits are employed in a semiconductor device having such a delay circuit, even if surge charge is applied to the signal input terminal, the first-stage inverter connected directly to the signal input terminal is a gate. Insulation breakdown can be avoided. However, when a positive surge charge is applied to the signal input terminal with the power supply terminal and the ground terminal open (no voltage state), for example, in the assembly line of the equipment on which the semiconductor device is to be mounted, the internal inverter is gated. Dielectric breakdown sometimes occurred.
[0005]
An object of the present invention is to improve the surge resistance performance of a semiconductor device.
[0006]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a semiconductor device having first, second and third logic circuits each having a function of inverting an input and cascaded directly or indirectly . An internal protection circuit is interposed in a connection portion between the output portion of the logic circuit and the input portion of the third logic circuit, and is led to the power supply line by the input protection circuit and from the power supply line to the second logic circuit. Thus, the internal protection circuit has a path through which the surge charge led to the input part of the third logic circuit can be guided to the ground line. The surge charge discharge path in the internal protection circuit is formed by breakdown of a transistor or a parasitic transistor constituting the internal protection circuit.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0008]
FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device according to the present invention. 1 includes a signal input terminal 10, a power supply terminal 20, a ground terminal 30, a signal input line 11, a power supply line 21, a ground line 31, a first input protection circuit 50, and a second input circuit. Input protection circuit 60, first inverter 100, second inverter 200, internal protection circuit 250, and third inverter 300.
[0009]
The first, second, and third inverters 100, 200, and 300 are connected in cascade. The first inverter 100 is a CMOS inverter composed of a P channel MOS transistor 101 and an N channel MOS transistor 102. Reference numeral 103 denotes an output line of the first inverter 100. The second inverter 200 is also a CMOS inverter composed of a P channel MOS transistor 201 and an N channel MOS transistor 202. Reference numeral 203 denotes an output line of the second inverter 200. The third inverter 300 is also a CMOS inverter composed of a P channel MOS transistor 301 and an N channel MOS transistor 302. Reference numeral 303 denotes an output line of the third inverter 300.
[0010]
The signal input line 11 supplies a signal supplied from the outside via the signal input terminal 10 to the first inverter 100. The power supply line 20 supplies a positive power supply voltage given from the outside via the power supply terminal 20 to the first, second, and third inverters 100, 200, 300. The ground line 31 supplies a ground voltage supplied from the outside via the ground terminal 30 to the first, second, and third inverters 100, 200, and 300.
[0011]
The first input protection circuit 50 is composed of a diode 51 so as to guide positive surge charges given to the signal input terminal 10 from the outside to the power supply line 21. The second input protection circuit 60 is configured by a diode 61 so as to guide negative surge charge given to the signal input terminal 10 from the outside to the ground line 31. The internal protection circuit 250 grounds the positive surge charge that is guided to the power line 21 by the first input protection circuit 50 and flows out from the P-channel MOS transistor 201 in the second inverter 200 toward the third inverter 300. A circuit for leading to the line 31, and a diffusion resistor 251 formed on the semiconductor substrate so as to be interposed in a connection portion between the output portion of the second inverter 200 and the input portion of the third inverter 300. I have. Reference numeral 252 denotes an input line of the third inverter 300.
[0012]
FIG. 2 is a partial cross-sectional view of the semiconductor device of FIG. Second inverter 200, internal protection circuit 250, and third inverter 300 are formed on P-type substrate 70. Reference numerals 71 and 72 denote P-type separation regions, respectively. The P-channel MOS transistor 201 includes a P-type diffusion source region 212, a P-type diffusion drain region 213, and a polysilicon gate electrode 214, each formed in the N-type well region 211. The N-channel MOS transistor 202 includes an N-type diffusion source region 222, an N-type diffusion drain region 223, and a polysilicon gate electrode 224 formed in the P-type well region 221, respectively. The P type diffused resistor 251 is configured by forming a P type diffused resistor region 262 in the N type epitaxial region 261. Therefore, a parasitic PNP transistor having the P-type diffusion resistance region 262 as an emitter, the N-type epitaxial region 261 as a base, and the P-type substrate 70 as a collector is formed. Moreover, the P-type substrate 70 and the P-type separation region 72 are connected to the ground line 31. The P-channel MOS transistor 301 includes a P-type diffusion source region 312, a P-type diffusion drain region 313, and a polysilicon gate electrode 314 formed in the N-type well region 311. The N-channel MOS transistor 302 includes an N-type diffusion source region 322, an N-type diffusion drain region 323, and a polysilicon gate electrode 324, each formed in the P-type well region 321.
[0013]
According to the semiconductor device having the configuration shown in FIGS. 1 and 2, when a positive surge charge is applied to the signal input terminal 10 with the power supply terminal 20 and the ground terminal 30 open, the surge charge is reduced to the first. The input protection circuit 50 leads to the power line 21. Thereby, the gate insulation of the first inverter 100 is protected. However, when the positive surge charge flows into the power supply line 21, it is as if a power supply voltage is applied to the power supply terminal 20 from the outside. Therefore, the first and second inverters 100 and 200 perform input inverting operation. Here, since the signal input line 11 connected to the signal input terminal 10 is at the H (high) level, the first inverter output line 103 is at the L (low) level, and the second inverter output line 203 is at the H (high) level. It becomes. That is, the P channel MOS transistor 201 in the second inverter 200 is turned on. As a result, positive surge charge flows from power supply line 21 to second inverter output line 203 via P-channel MOS transistor 201. Here, when the breakdown voltage between the collector and the emitter of the parasitic PNP transistor formed by the P-type diffusion resistance region 262, the N-type epitaxial region 261, and the P-type substrate 70 is BVCEO (the base circuit is open), As a result of the breakdown of the parasitic PNP transistor when the potential of the P-type diffusion resistance region 262 connected to the second inverter output line 203 exceeds BVCEO, surge charges are bypassed to the ground line 31. Thereby, the gate insulation of the third inverter 300 is protected.
[0014]
When a negative surge charge is applied to the signal input terminal 10 with the power supply terminal 20 and the ground terminal 30 open, the second input protection circuit 60 guides this surge charge to the ground line 31. Thereby, the gate insulation of the first inverter 100 is protected. In addition, since the first and second inverters 100 and 200 do not perform the input inversion operation, the third inverter 300 does not have a problem of gate dielectric breakdown.
[0015]
An N-type diffused resistor may be employed instead of the P-type diffused resistor 251.
[0016]
FIG. 3 is a circuit diagram showing another configuration example of the semiconductor device according to the present invention. The internal protection circuit 250 in FIG. 3 includes an NPN transistor 253 interposed at a connection portion between the output portion of the second inverter 200 and the ground line 31. The NPN transistor 253 has a collector connected to the second inverter output line 203, an emitter connected directly to the ground line 31, and a base connected to the ground line 31 via a P-type diffusion resistor 254.
[0017]
FIG. 4 is a partial cross-sectional view of the semiconductor device of FIG. An NPN transistor 253 and a P-type diffused resistor 254 are formed on the P-type substrate 70. Reference numeral 271 denotes a P-type separation region. The NPN transistor 253 includes an N-type diffusion collector region 273, a P-type diffusion base region 274, and an N-type diffusion emitter region 275 formed in the N-type epitaxial region 272. The P type diffused resistor 254 is configured by forming a P type diffused resistor region 277 in the N type epitaxial region 276. Reference numeral 278 denotes a base wiring.
[0018]
Even in the semiconductor device having the configuration shown in FIGS. 3 and 4, when a positive surge charge is applied to the signal input terminal 10 with the power supply terminal 20 and the ground terminal 30 open, the surge charge is applied to the first input. It flows into the power supply line 21 via the protection circuit 50, and a positive surge charge flows out from the power supply line 21 to the second inverter output line 203 via the P-channel MOS transistor 201. Here, when the breakdown voltage between the collector and the emitter of the NPN transistor 253 is BVCER (the base circuit is resistance grounded), the potential of the N-type diffusion collector region 273 connected to the second inverter output line 203 exceeds BVCER. As a result of the breakdown of the NPN transistor 253 at the time, surge charges are bypassed to the ground line 31. Thereby, the gate insulation of the third inverter 300 is protected.
[0019]
Note that a PNP transistor may be employed instead of the NPN transistor 253.
[0020]
FIG. 5 is a circuit diagram showing still another configuration example of the semiconductor device according to the present invention. The internal protection circuit 250 in FIG. 5 includes an N-channel MOS transistor 255 interposed at a connection portion between the output portion of the second inverter 200 and the ground line 31. The drain of the N channel MOS transistor 255 is connected to the second inverter output line 203, and the gate and source are connected to the ground line 31.
[0021]
FIG. 6 is a partial cross-sectional view of the semiconductor device of FIG. N channel MOS transistor 255 includes an N type diffusion source region 282, an N type diffusion drain region 283, and a polysilicon gate electrode 284 formed in P type well region 281, respectively.
[0022]
Also in the semiconductor device having the configuration shown in FIGS. 5 and 6, when a positive surge charge is applied to the signal input terminal 10 with the power supply terminal 20 and the ground terminal 30 open, the surge charge is applied to the first input. It flows into the power supply line 21 via the protection circuit 50, and a positive surge charge flows out from the power supply line 21 to the second inverter output line 203 via the P-channel MOS transistor 201. Here, if the breakdown voltage between the drain and source of the N-channel MOS transistor 255 is BVDS, when the potential of the N-type diffusion drain region 283 connected to the second inverter output line 203 exceeds BVDS, the N-channel MOS transistor 255 As a result of the breakdown of the MOS transistor 255, surge charges are bypassed to the ground line 31. Thereby, the gate insulation of the third inverter 300 is protected.
[0023]
In place of the N channel MOS transistor 255, a P channel MOS transistor may be employed.
[0024]
Needless to say, the first and second input protection circuits 50 and 60 in FIGS. 1, 3 and 5 are not limited to the diode configuration. According to FIG. 7, the first input protection circuit 50 is configured by a P-channel MOS transistor 52, and the second input protection circuit 60 is configured by an N-channel MOS transistor 62. Further, according to FIG. 8, the first input protection circuit 50 is configured by an NPN transistor 53, and the second input protection circuit 60 is configured by another NPN transistor 63. It is also possible to replace at least one of these NPN transistors 53 and 63 with a PNP transistor.
[0025]
In the above description, the internal protection circuit 250 is inserted between the output unit of the second inverter 200 and the input unit of the third inverter 300. A similar internal protection circuit may be provided at the input of the inverter. The present invention can be applied not only to the inverters 100, 200, and 300 but also to a case where a plurality of logic circuits each having a function of inverting inputs, such as NAND gates and NOR gates, are cascaded.
[0026]
【The invention's effect】
As described above, according to the present invention, in the semiconductor device including the first, second, and third logic circuits each having a function of inverting the input and directly or indirectly connected in cascade, Between the output part of the logic circuit and the input part of the third logic circuit , the charge of the connection part caused by the surge charge led to the power supply line by the input protection circuit to the ground line Since the internal protection circuit having the guide path is further provided, the surge resistance of the semiconductor device is improved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device according to the present invention.
2 is a partial cross-sectional view of the semiconductor device of FIG. 1;
FIG. 3 is a circuit diagram showing another configuration example of the semiconductor device according to the present invention.
4 is a partial cross-sectional view of the semiconductor device of FIG. 3;
FIG. 5 is a circuit diagram showing still another configuration example of the semiconductor device according to the present invention.
6 is a partial cross-sectional view of the semiconductor device of FIG. 5;
7 is a circuit diagram showing a modification of FIGS. 1, 3, and 5. FIG.
FIG. 8 is a circuit diagram showing another modification of FIGS. 1, 3 and 5;
[Explanation of symbols]
10 signal input terminal 11 signal input line 20 power supply terminal 21 power supply line 30 ground terminal 31 ground line 50 first input protection circuit 51 diode 52 P-channel MOS transistor 53 NPN transistor 60 second input protection circuit 61 diode 62 N-channel MOS Transistor 63 NPN transistor 70 P-type substrate 71 P-type isolation region 72 P-type isolation region 100 First inverter 101 P-channel MOS transistor 102 N-channel MOS transistor 103 First inverter output line 200 Second inverter 201 P-channel MOS transistor 202 N-channel MOS transistor 203 Second inverter output line 211 N-type well region 212 P-type diffusion source region 213 P-type diffusion drain region 214 Polysilicon gate electrode 221 P-type well region 222 N-type diffusion source region 223 N-type diffusion drain region 224 Polysilicon gate electrode 250 Internal protection circuit 251 P-type diffusion resistor 252 Third inverter input line 253 NPN transistor 254 P-type diffusion resistor 255 N-channel MOS transistor 261 N-type epitaxial region 262 P-type diffusion resistance region 271 P-type isolation region 272 N-type epitaxial region 273 N-type diffusion collector region 274 P-type diffusion base region 275 N-type diffusion emitter region 276 N-type epitaxial region 277 P-type diffusion resistance region 278 Base wiring 281 P Type well region 282 N type diffusion source region 283 N type diffusion drain region 284 Polysilicon gate electrode 300 Third inverter 301 P channel MOS transistor 302 N channel MOS transistor 303 Third inverter output line 311 N-type well region 312 P-type diffusion source region 313 P-type diffusion drain region 314 Polysilicon gate electrode 321 P-type well region 322 N-type diffusion source region 323 N-type diffusion drain region 324 Polysilicon gate electrode

Claims (15)

First, second and third logic circuits each having a function of inverting an input and cascaded directly or indirectly;
A signal input terminal for supplying an externally applied signal to the first logic circuit;
A power supply line capable of supplying a positive power supply voltage applied from the outside via a power supply terminal to the first, second and third logic circuits;
An input protection circuit having a path capable of guiding surge charges externally applied to the signal input terminal to the power supply line to which the third logic circuit is directly connected without passing through the power supply terminal;
A ground line capable of supplying a ground voltage applied from the outside via a ground terminal to the first, second and third logic circuits;
Interposed in the connection between the output part of the second logic circuit and the input part of the third logic circuit, led to the power line by the input protection circuit, and from the power line to the second A semiconductor device comprising: an internal protection circuit having a path capable of guiding surge charges led to the connection portion via a logic circuit to the ground line. First, second and third logic circuits each having a function of inverting an input and cascaded directly or indirectly;
A signal input terminal for supplying an externally applied signal to the first logic circuit;
A power supply line capable of supplying a positive power supply voltage applied from the outside via a power supply terminal to the first, second and third logic circuits;
An input protection circuit having a path capable of guiding a surge charge applied to the signal input terminal from the outside to the power supply line;
A ground line capable of supplying a ground voltage applied from the outside via a ground terminal to the first, second and third logic circuits;
Interposed in the connection between the output part of the second logic circuit and the input part of the third logic circuit, led to the power line by the input protection circuit, and from the power line to the second An internal protection circuit having a path capable of guiding a surge charge led to the connection part via a logic circuit to the ground line;
The semiconductor device according to claim 1, wherein the path of the internal protection circuit is formed by a breakdown of a transistor or a parasitic transistor constituting the internal protection circuit. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the first and second logic circuits are inverters each composed of a P-channel MOS transistor and an N-channel MOS transistor. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the input protection circuit is composed of any one of a diode, a MOS transistor, and a bipolar transistor. The semiconductor device according to claim 1 or 2,
The internal protection circuit is formed on the semiconductor substrate in the semiconductor region, a first conductivity type semiconductor substrate connected to the ground line, a second conductivity type semiconductor region in contact with the semiconductor substrate, and the semiconductor substrate. A diffusion resistance of the first conductivity type,
At least one end of the diffused resistor is connected to a connection portion between an output portion of the second logic circuit and an input portion of the third logic circuit. The semiconductor device according to claim 5.
The internal protection circuit is
A P-type region connected to the ground wire;
An N-type region formed in contact with the P-type region;
And a P-type diffusion region formed in the N-type region and interposed in a connection portion between the output portion of the second logic circuit and the input portion of the third logic circuit. A semiconductor device. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the internal protection circuit includes a bipolar transistor interposed in a connection portion between the output portion of the second logic circuit and the ground line. The semiconductor device according to claim 7.
2. The semiconductor device according to claim 1, wherein the bipolar transistor is an NPN transistor having a collector connected to the output portion of the second logic circuit, a base, and an emitter connected to the ground line. The semiconductor device according to claim 8.
The internal protection circuit is
An N-type diffused collector region connected to the output of the second logic circuit;
A P-type diffusion base region formed adjacent to the N-type diffusion collector region;
A semiconductor device comprising: an N-type diffusion emitter region diffused in the P-type diffusion base region and connected to the ground line. The semiconductor device according to claim 8.
A semiconductor device, further comprising a resistor interposed in a connection portion between a base of the NPN transistor and the ground line. The semiconductor device according to claim 9.
A semiconductor device, further comprising a P-type diffusion resistance region interposed at a connection portion between the P-type diffusion base region and the ground line. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the internal protection circuit includes a MOS transistor interposed in a connection portion between the output portion of the second logic circuit and the ground line. The semiconductor device according to claim 12, wherein
The semiconductor device according to claim 1, wherein the MOS transistor is an N-channel MOS transistor having a drain connected to an output portion of the second logic circuit, and a gate and a source connected to the ground line. The semiconductor device according to claim 13.
The internal protection circuit is
A P-type region;
An N-type diffusion drain region diffused in the P-type region and connected to the output of the second logic circuit;
A gate electrode connected to the ground line;
A semiconductor device comprising: an N-type diffusion source region diffused in the P-type region and connected to the ground line. First, second and third logic circuits each having a function of inverting an input and cascaded directly or indirectly;
A signal input terminal for supplying an externally applied signal to the first logic circuit;
A power supply line capable of supplying a positive power supply voltage applied from the outside via a power supply terminal to the first, second and third logic circuits;
An input protection circuit having a path capable of guiding a surge charge applied to the signal input terminal from the outside to the power supply line;
A ground line capable of supplying a ground voltage applied from the outside via a ground terminal to the first, second and third logic circuits;
A first conductivity type semiconductor substrate connected to the ground line;
Interposed in the connection between the output part of the second logic circuit and the input part of the third logic circuit, led to the power line by the input protection circuit, and from the power line to the second A method of forming a semiconductor device comprising: an internal protection circuit having a path capable of guiding surge charges led to the connection part via a logic circuit to the ground line,
Forming the second conductive type first semiconductor region on the semiconductor substrate; forming the first conductive type second semiconductor region in the first semiconductor region by diffusion; and A method of forming a semiconductor device, comprising: forming a second semiconductor region between an output portion of the second logic circuit and an input portion of the third logic circuit.

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