JP3941206B2 - High voltage IC - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a high voltage IC used for control drive of a power device.
[0002]
[Prior art]
  Power devices are widely used in many fields such as inverters and converters for motor control. This power device has been driven and controlled by an electronic circuit configured by combining individual semiconductor elements and electronic components. However, in recent years, a high voltage IC exceeding 1000 V utilizing LSI (Large Scale Integrated Circuit) technology has been put into practical use. Further, a power IC integrated on the same semiconductor substrate as the drive / control circuit and the power device is used.
[0003]
  FIG. 10 is a circuit configuration diagram that focuses on the power section of the motor control inverter. The power device used to drive the three-phase motor 70 constitutes a bridge circuit and has a structure of a power module 71 housed in the same package. In this figure, the power module71Is composed of an insulated gate bipolar transistor (hereinafter referred to as IGBT) which is a power device and a diode. In the figure, IGBTs are indicated by Q1 to Q6, and diodes are indicated by D1 to D6. The high potential side VCC2H of the main power supply VCC2 is the collector of Q1, Q2 and Q3(Hereinafter, sometimes referred to as drain)The low potential side VCC2L is the emitter of Q4, Q5 and Q6(Hereafter, sometimes referred to as source)The gate of each IGBT is connected to the output of the main circuit drive circuit 72, the input terminal I / O of the main circuit drive circuit 72 is connected to a normal microcomputer, and the output of the inverter composed of the power module 71 U, V, and W are connected to the three-phase motor 70.
[0004]
  The main power supply VCC2 is normally a high voltage of 100 to 400V. In particular, when Q4, Q5, and Q6 are in the off state, the source potentials of Q1, Q2, and Q3 become high voltages, respectively, so when driving these gates, they must be driven at a voltage higher than the source potential. Therefore, a photocoupler (PC: Photo Coupler) or a high voltage IC (hereinafter referred to as HVIC; HVIC: High Voltage Integrated Circuit) is used for the main circuit driving circuit 72. The input / output terminal I / O (Input / Output) of the main circuit drive circuit 72 is normally connected to a microcomputer, and the microcomputer controls the entire inverter circuit composed of the power module 71. Next, an example of HVIC is shown.
[0005]
  FIG. 11 is an HVIC element configuration diagram. The HVIC forming the main circuit driving circuit 72 exchanges signals with the microcomputer through the input / output terminal I / O, and turns on which IGBT.,A control circuit (hereinafter referred to as CU: Control Unit) for generating a control signal for turning off, a signal from this CU is received to drive the gate of the IGBT, and an overcurrent of the IGBT,OverheatingAnd a gate drive circuit (hereinafter referred to as GDU) that transmits an abnormal signal to the CU.
  Control Unit) and a level shift circuit that functions to mediate the VCC2L level and VCC2H for the gate signals and alarm signals of Q1, Q2, and Q3 connected to the high potential side of the IGBTs constituting the bridge of FIG. Hereinafter, it is referred to as “LSU.” LSU: Level Shift Unit). This GDU is composed of GDU-U, GDU-V, GDU-W connected to Q1, Q2, and Q3, and GDU-X, GDU-Y, and GDU-Z connected to Q4, Q5, and Q6. Next, an example of the LSU is shown.
[0006]
  FIG. 12 is a basic configuration diagram of the LSU. As a basic configuration, a high breakdown voltage n-channel MOSFET 61 and a resistor RL1, and a high breakdown voltage p-channel MOSFET 62 and a resistor RL2 are used. The high breakdown voltage n-channel MOSFET 61 is used for level shifting the signal from the CU to GDU-U, V, and W on the high potential side VCC2H.OverheatingIn order to shift the level of the abnormal signal to the CU on the low potential side VCC2L, in particular, overcurrent detection of Q1, Q2 and Q3OverheatingThe high breakdown voltage p-channel MOSFET 62 is not required when an abnormal signal such as detection is not output. The high breakdown voltage n-channel MOSFET 61 and the high breakdown voltage p-channel MOSFET 62 used in this LSU are required to have a breakdown voltage value of 600 V to 1200 V equivalent to the IGBTs (Q1 to Q6) that drive the three-phase motor 70.
[0007]
  Next, a specific high withstand voltage isolation method for electrically isolating the high withstand voltage circuit from the low withstand voltage circuit will be described. Dielectric separation, junction separation, and self-separation have been reported so far, but dielectric separation and junction separation have a complicated separation structure and a high manufacturing cost. The higher the withstand voltage, the higher the manufacturing cost. On the other hand, the self-separation has an advantage that the manufacturing cost can be kept low.
[0008]
  FIG. 13 is a plan view of a main part of a high voltage IC having a conventional high voltage n channel level shifter and high voltage p channel level shifter formed by self-isolation. In the figure, 100 is p.^-Substrate, 1 is n^-Well region, 2 is p^-Offset region, 3 is n region, 4 is p well region, 5 is n drain region, 6a and 6b are p region, 10 is n region⁺Source region, 13 and 14 are n⁺Regions 15a and 15b are p⁺Region, 17 is p⁺Source region, 18 is p⁺Drain regions 31 and 32 indicate gate electrodes.
[0009]
  The high breakdown voltage n-channel level shifter has n drain region 5 and n for making ohmic contact between n drain region 5 and a drain electrode (not shown).⁺Region 13, gate electrode 31, n⁺A high potential electrode connected to the high potential side of the power source of the source region 10 and the gate drive circuit U-GDU (there are V-GDU, W-GDU, X-GDU, Y-GDU, and Z-GDU) It consists of n regions 3 to be connected.
[0010]
  On the other hand, the high breakdown voltage p-channel level shifter is p⁺Drain region 18, gate electrode 32, p⁺The source region 17 is composed of a p-well region 4 connected to a COM electrode 41 (not shown).
  The high breakdown voltage n-channel level shifter widens the distance between the n drain region 5 and the n region 3.TheThus, the parasitic resistance R1 in FIG. 14 is increased. The high breakdown voltage p-channel level shifter is p⁺The distance between the drain region 18 and the p-well region 4 is increased to increase the parasitic resistance R2 in FIG. Usually, n drain region 5 and p⁺The drain region 18 is laid out so as to be surrounded by the gate electrode 31 and the gate electrode 32.
[0011]
  FIG. 14 is a cross-sectional view of the main part taken along the line C-C ′ of FIG. 13. This figure is a cross-sectional view of the main part of an n-channel level shifter. In the figure, 41 is COM (COM electrode), 42a is a drain electrode, 43 is a high potential electrode of the GDU power supply, 44 is a low potential electrode of the GDU power supply, RL1 is a level shift resistor, R1 is a parasitic resistance, and HVJT is a high voltage. A pressure | voltage resistant structure part is shown. The COM is connected to VCC2L in FIG. Vcc is the power supply for the GDU-U. U-OUT is a terminal connected to the low potential side of VCC, and is connected to U-OUT in FIG. OUT is a drain terminal connected to the drain electrode 42a and is connected to the GDU-U. U-VCC is a terminal connected to the high potential side of VCC. Other reference numerals are the same as those in FIG.
[0012]
  Next, it explains in detail. Each component is n^-A high breakdown voltage n-channel MOSFET formed on the surface of the well region 1 is formed on the gate electrode 31 and the p well region 4.1n ⁺ Source region 11, second n ⁺ Consists of source region 12n⁺Source region 10, p^-High voltage isolation portion (hereinafter referred to as HVJT; HVJT: High Voltage Junction Terminal) and n by double RESURF (reduced-SURface-Field: one type of surface breakdown voltage structure) using the offset region 2⁺The drain region 5 is constituted. N^-Well region 1 and n^-A potential corresponding to the low level (hereinafter referred to as L level) of a complementary MOSFET circuit (hereinafter referred to as CMOS circuit) composed of a low breakdown voltage n-channel MOSFET and a low breakdown voltage p-channel MOSFET configured in the well region 1. The p-well region 4 is connected via a power source VCC for driving the HVIC.^-The pn junction between the well region 1 and the p well region 4 is always reverse-biased. Resistor RL1 is connected to this power source VCC.⁺Provided between the region 14 and the n drain region 5 of the high breakdown voltage n-channel MOSFET, a predetermined voltage is generated by the current passing through the resistor RL1, and an on / off signal at the VCC2L level is turned on / off at the high potential U-VCC level. Output to signal.
[0013]
  FIG. 15 is a cross-sectional view of the main part taken along the line D-D ′ of FIG. 13. This figure is a cross-sectional view of the main part of a high breakdown voltage p-channel level shifter. The reference numerals are the same as those in FIG. 42b is a drain electrode, RL2 is a level shift resistor, R2 is a parasitic resistor, and OUT is a drain terminal connected to the drain electrode 42b and connected to the CU.
  Next, it explains in detail. As above, each component is n^-A high breakdown voltage p-channel MOSFET formed on the surface of the well region 1 includes a gate electrode 32, p⁺P that doubles as source region 17 and drift region^-HVJT and p by offset region 2⁺A drain region 18 is formed. The n region 3 and the p well region 4 at a potential corresponding to the L level of the CMOS are connected via a power supply VCC for driving the HVIC.^-The pn junction between the well region 1 and the p well region 4 is always reverse-biased. Resistor RL2 is a p-well region 4 connected to VCC2L and a p-channel MOSFET of high breakdown voltage p-channel MOSFET.⁺A predetermined voltage is generated by a current passing through the resistor RL2 provided between the drain regions 18, and an abnormal signal of VCC2H level is output to a signal of VCC2L level. As shown in FIG. 15, the layout of the element is p as in the case of the high breakdown voltage n-channel MOSFET.⁺Drain region18Is surrounded by the gate electrode 32.
[0014]
[Problems to be solved by the invention]
  In a level shifter using the high breakdown voltage n-channel MOSFET and the high breakdown voltage p-channel MOSFET (hereinafter referred to as an n-channel level shifter and a p-channel level shifter), the high breakdown voltage is applied to the resistors (RL1, RL2) in order to level shift the input signal. The current from the n-channel and p-channel MOSFETs must flow sufficiently to generate a voltage that can drive the GDU and CU CMOS across the resistors (RL1, RL2). However, when these structures are formed by self-separation, when a high breakdown voltage n-channel MOSFET is formed,As shown in FIG.n^-Well regionThe parasitic resistance R1 is built in 1 and pIn the case where a channel MOSFET is formed,As shown in FIG.p^-Offset area2Parasitic resistance R2 is built in. Specifically, figure14In the case of the high breakdown voltage n-channel MOSFET, the electrons passing through the channel are not only n-drain region 5 but also n on the high potential side VCC2H of the power source VCC.⁺It can also enter the n region 3 connected via the region 14. In the case of a high breakdown voltage p-channel MOSFET, the hole is p.⁺In addition to the drain region 18, the p-type well region 4 connected to the low potential side VCC2L of the power supply VCC can enter. For this reason, the resistance (RL1_,When the resistance values of the parasitic resistances R1 and R2 are smaller than the resistance value of RL2), the current almost flows through the parasitic resistances R1 and R2, and the resistance (RL1)_,Does not flow through RL2). Then, resistance (RL1_,The voltage generated at RL2) does not reach the voltage (threshold voltage) for driving the CMOS formed in the GDU, and does not function as a level shifter.
[0015]
  Increasing parasitic resistance is an effective way to avoid this. That is, for the high breakdown voltage n-channel MOSFET, the distance between the n drain region 5 and the n region 3 is increased, and for the high breakdown voltage p-channel MOSFET, p is set.⁺In this method, the parasitic resistance is increased by increasing the distance between the drain region 18 and the p-well region 4 at the VCC2L level. But this wayImpurity concentration and thickness can not be changed and only the distance can be increased.Disadvantages of increased level shifter area and higher chip costButis there. On the other hand, a large current is passed through a small parasitic resistance to increase the voltage generated in the parasitic resistance, and the resistance (RL1) connected in parallel with this parasitic resistance._,It is possible to increase the voltage generated at RL2), operate the CMOS constituting the GDU, and level-shift the on / off signal. However, in this case, there is a drawback that power consumption is increased.
[0016]
  In order to solve the above-described problems, an object of the present invention is to provide a low-cost and low-power HVIC by reducing the chip size by increasing the parasitic resistance of n-channel and p-channel level shifters. That is.
[0017]
[Means for Solving the Problems]
  To achieve the above objective,pIn the shape of a semiconductor substratenA well region of a shape is formed, and a gate drive circuit of a power device and a lateral n-channel MOSFET are formed in the well region.An n region to which the high potential side of the main power source is connected is provided all around the gate drive circuit;The n-channel MOSFET has a high breakdown voltage isolation portion between the source region, the gate electrode and the drain region, and the high breakdown voltage isolation portion is connected to the gate drive circuit.Outside the n regionIn a high withstand voltage IC that surrounds and is connected to the drain region of the n-channel MOSFET via a level shift resistor on the high potential side of the main power supply, the drain region and then regionIn the well region between, Locally n-type region does not exist throughout the depth direction of the well regionThe opening is formed.
[0018]
The opening of the well region isBy not forming the well region locallyThe semiconductor substrate is exposedIs partThe configuration. Also, the opening of the well regionThrough the well region locallyThe trench groove reaches the semiconductor substrate. Alternatively, the opening of the well regionIsSame as the semiconductor substratepIn shape andPenetrates the well region locally andA diffusion layer that reaches the semiconductor substrateis thereI will do it.
[0019]
[0020]
[0021]
[0022]
[0023]
  As described above, in the well region between the drain region and the gate drive circuit., Locally n-type region does not exist throughout the depth direction of the well regionBy forming the high resistance region by the opening, the parasitic resistance of the level shifter can be increased without increasing the chip size.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
  1 is a plan view of a main part of a part of an HVIC according to a first embodiment of the present invention, FIG. 2 is a plan view of a main part in which the n-channel MOSFET part of FIG. 1 is enlarged, and FIG. FIG. 4 is a cross-sectional view of main parts cut along line AA ′, and FIG. 4 is a cross-sectional view of main parts cut along line BB ′ of FIG.
[0025]
  FIG. 1 shows the GDU-U which is one GDU shown in FIG. 11 and the LSU (RL1 and RL2 are omitted) for driving the Q1 which is the IGBT in the upper arm of FIG. Of course, GDU-V and GDU-W have the same configuration. Further, a plan view in which the gate electrode is projected on the surface of the semiconductor is shown.
  In the figure, one n-channel level shifter and one p-channel level shifter are shown. However, in this one-input system, the n-channel MOSFET and the p-channel MOSFET are turned on for a long period of time, and during the on-period of these MOSFETs. The through current continues to flow and the power consumption increases. In order to avoid this, by adopting a two-input system in which two n-channel MOSFETs and two p-channel MOSFETs are provided, the ON period of the MOSFET is shortened by transmitting the ON signal / OFF signal in a pulse manner, and the level shifter Significantly reduce power consumptionCanThis method is often used because it can. In the embodiment described below, the HVIC corresponding to the one-input method is simplified.Was. Of course, in the same way as the 2-input methodUnfoldit can.
[0026]
  The HVIC according to the first embodiment of the present invention will be described with reference to FIGS. 1, 2, 3 and 4. FIG.
  First, the n-channel level shifter will be described. As shown in FIG. 1, the high breakdown voltage n-channel MOSFET used for the n-channel level shifter is arranged at the corner of GDU-U. N of this high breakdown voltage n-channel MOSFET⁺As shown in FIG.⁺Source region 11 and second n⁺The source region 12 is separated into two parts (the first and second numbers are assigned to n of the same conductivity type).⁺Because the source area was divided into twois there). N between the n drain region 5 of the high breakdown voltage n-channel MOSFET and the n region 3 connected to the high potential side of the power source VCC.^-An opening 21 through which the p substrate 100 is exposed is provided locally in the well region 1 to form a high resistance region 51 shown in FIG. This high resistance region 51 is n^-The well region 1 includes a curved portion. By providing the high resistance region 51, the parasitic resistance R1 from the n drain 5 to the n region 3 of the high breakdown voltage n-channel MOSFET can be increased without increasing the chip area. This is because, through the channel formed directly below the gate electrode 31 from the first and second source regions 11 and 12, n^-A part of the electrons injected into the well region 1 flows into the n region 3 through the parasitic resistance R1, and becomes an unnecessary current. However, by providing the high resistance region 51, this current flows around the high resistance region 51. As a result, the parasitic resistance R1 increases, and unnecessary current can be reduced.
[0027]
  As a method of inserting the high resistance region 51,As shown in FIG.N drain region 5 of high breakdown voltage n-channel MOSFET and n region 3 located on the outer periphery of GDU-UAnd the outer periphery ofThe dotted line connecting,N region 3 located on the outer periphery of GDU-UWhenTriangular area surrounded byInsideAndcentering on the n drain region 5The second n of the high breakdown voltage n-channel MOSFET⁺Source region 12And oppositeWhen it is formed in the place to,This is effective because the length of the detoured electron path is increased. However, when the high resistance region 51 reaches the dotted line, the withstand voltage may be deteriorated. This is because the dotted line becomes the end of the HVJT where the depletion layer spreads, and when the high resistance region 51 reaches this dotted line, the extension of the depletion layer is suppressed and electric field concentration occurs.
[0028]
  N^-When the well region 1 is opened, the high resistance region 51^-Well region 1ButtwoSplitThe region other than the high resistance region 51 is not n^-The well regions 1 are connected. When a voltage is applied between U-VCC and COM, n^-Well region 1 and p^-The pn junction formed by the substrate 100 is reverse-biased, and this high resistance region 51 (this region is p^-The substrate 100) is pinched off at a low voltage. Therefore, n^-Completely divide well region 1Split(Not open, but completely n^-Compared to the case where the well region 1 is separated, there is an advantage that the decrease in breakdown voltage is small. When the shape of the opening 21 is formed in a slit shape, the slit may have a width that does not collapse the opening.
[0029]
  Further, in FIG. 1, the curved opening portion 21 that writes an arc centering on the n drain region 5 is shown, but it may be a collection of a large number of straight lines instead of a curved line, Since parasitic resistance R1 increases, it is effective. In addition, for the sake of overall layout, when GDU-U is laid out in a form close to a square,13As described above, the high breakdown voltage n-channel MOSFET may have a shape in which a region having the gate electrode 10 and the n drain region 5 protrudes.
[0030]
  nextUsing the reference example in Figure 4A p-channel level shifter will be described. In FIG. 1, the high breakdown voltage p-channel MOSFET is arranged at the corner of GDU-U, and the high breakdown voltage pchannelMOSFET p⁺Drain region 18 and p^-P well region 4 on the outer periphery of the offset region 2 (p for making a contact of VCC2L level on the outer periphery)⁺There is a region 16 and p⁺It is formed simultaneously with the drain region 18. P between^-The offset region 2 is locally opened. N at this opening 22^-A slit-like high resistance region 52 where the well region 1 is exposed is provided. The high resistance region 52 is p as shown in FIG.^-The location where the offset region 2 is curved is also included.
[0031]
  By doing this, p of the high voltage p-channel MOSFET⁺The parasitic resistance R2 from the drain region 18 to the p-well region 4 can be increased without increasing the chip area. The high resistance region 52 is p^-A curved portion of the inner peripheral portion of the p well region 4 formed on the outer peripheral side of the offset region 2, and a high breakdown voltage p.channelMOSFET p⁺It is formed in a triangular region surrounded by the drain region 18 and a dotted line extending perpendicularly to the straight line portion of the inner peripheral portion of the p-well region 4. However, for the same reason as described above, when the high resistance region 52 reaches the dotted line (dotted line indicating one end of the HVJT), the breakdown voltage may deteriorate. When the opening 22 is formed in a slit shape, the slit may have a width that does not crush the opening.
[0032]
  In FIG.⁺Although the curved opening 22 having a circular arc centered on the drain region 18 is shown, a large number of straight lines may be used instead of a curved line, and the parasitic resistance R2 increases even when a large number of small independent circles are connected. It is effective. Further, for the sake of overall layout, this may be formed on the side of the GDU-U instead of the corner of the GDU-U.
[0033]
  In the above, the source region of the n-channel MOSFET is the first n⁺Source region 11 and second n⁺Although it is separated into the source region 12, it may be connected.
  Also figure3P^-Offset region 2 is n^-It is isolated inside the well region 1, but p^-P between the n drain region 5 and the n region 3 without separating the offset region 2^-It may be tied in the offset area 2.
[0034]
  Further, the n-type region 3 and the p-well region 4 other than the above are opposed to each other in a straight line^-Well region 1 and p^-Even if the high resistance region 51 and the high resistance region 52 are formed in the offset region 2, the effect of increasing the parasitic resistances R1 and R2 is extremely small, and the breakdown voltage is reduced as compared with the case where the high resistance regions 51 and 52 are not provided. It is better not to form. U-VCC formed in GDU-U is a high potential terminal of power supply VCC, U-OUT is a low potential terminal of power supply VCC, U-GATE is a G terminal, U-OC is an overcurrent detection terminal, U- OTOverheatingIndicates the detection terminal.
[0035]
  Next, a manufacturing method for manufacturing the HVIC of the first embodiment will be described. The substrate is p^-Although the specific resistance greatly depends on the element withstand voltage using the substrate 100, for example, in order to obtain a withstand voltage of 600 V class, about 100 Ωcm is required. This p^-Low concentration (10¹²cm^-2N) by phosphorus diffusion with a junction depth of about 5 to 6 μm.^-P for forming the well region 1 and then forming the RESURF^-The offset amount in the offset region 2 is 10¹³cm^-2In this order, it is formed by ion implantation of boron having a junction depth of about 1 μm. This n^-Well region 1 and p^-In the offset region 2, openings (to be the openings 21 and 22 after diffusion) are selectively provided in the mask during ion implantation so that the high resistance regions 51 and 52 are formed.
[0036]
  This p^-The offset region 2 must be completely depleted at a high voltage, and the electric field concentration balance is large depending on the concentration.DifferentTherefore, in order to realize a high breakdown voltage, this p^-Offset region 2 and n^-It is important to optimize the dose and junction depth during ion implantation of the well region 1. Next, the p-well region 4 for forming the channel of the n-channel MOSFET has a dose of 10¹³cm^-2In this order, a junction depth of about 1 μm is formed by boron ion implantation, and n is applied to the high potential electrode 43 of the power source VCC.⁺N region 3 and n drain region 5 connected through region 14 are¹³cm^-2After that, a junction depth of about 1 μm is formed by phosphorus ion implantation, and then gate electrodes 31 and 32 are formed by the active region and polysilicon. Further, p for making contact with the respective p region 6, n region 3 and n drain region 5.⁺Region 15, n⁺Region 14 or n of n-channel MOSFET⁺N for forming source regions 11 and 12⁺Diffusion with boron fluoride (BF₂) Or arsenic at a surface concentration capable of ohmic contact, and then the aluminum, the COM electrode 41, the drain electrode 42, the high potential electrode 43, and the low potential electrode 44 are formed.
[0037]
  FIG. 5 is a plan view of an essential part of a second embodiment of the present invention. A sectional view taken along the line AA in FIG. The description of this figure is omitted because it has been described in the first embodiment. In this embodiment, the p-channel shift register is unnecessary or provided in another semiconductor chip, and the chip size can naturally be made smaller than that in the first embodiment.
[0038]
  FIG. 6 shows the present invention.Reference exampleFIG. The cross-sectional view taken along the line BB in FIG. The description of this figure is omitted because it has been described in the first embodiment. thisReference exampleIn this case, the n-channel shift register is provided in another semiconductor chip, and the chip size can naturally be made smaller than that in the first embodiment.
  FIG. 7 shows the first aspect of the present invention.3In the embodiment, when the opening portion of the high resistance region is crushed, FIG.^-When a high resistance region is provided in the well regionExamples of(B) in the figure is p^-When a high resistance area is provided in the offset areaReference exampleIt is. 1A is a cross-sectional view of the main part cut along the line A-A ′ in FIG. 1, and FIG. 2B is a cross-sectional view of the main part cut along the line B-B ′ in FIG. 1. As shown in the figure, the openings 21 and 22 are filled with diffusion, and the diffusion depths t1 and t2 of the portions are n.^-Well region 1 diffusion depth Xj1 or p^-Even when the diffusion depth is shallower than the diffusion depth Xj2 of the offset region 2, the sheet resistance of the high resistance regions 53 and 54 at that location is increased, which is effective in increasing the parasitic resistance. However, as in the first embodiment, n^-Well region 1 and p^-The effect is small compared to the case where the offset region 2 is completely open. Although the embodiment corresponding to FIG. 1 has been described here, there are of course embodiments corresponding to FIGS. 5 and 6.
[0039]
  FIG. 8 shows the first aspect of the present invention.4In the embodiment, when the high resistance region is formed by the opposite conductivity type region, FIG.^-When a high resistance region is provided in the well regionExamples of(B) in the figure is p^-When a high resistance area is provided in the offset areaReference exampleIt is. 1A is a cross-sectional view of the main part cut along the line A-A ′ in FIG. 1, and FIG. 2B is a cross-sectional view of the main part cut along the line B-B ′ in FIG. 1. Of course, in the figure, the high resistance regions 55 and 56 penetrate through the junction, but they do not have to penetrate. As shown in FIG. 1, the parasitic resistance increases in this case as well.
[0040]
  FIG. 9 shows the first aspect of the present invention.5In the embodiment, the high resistance region is formed by a trench groove, and FIG.^-When a high resistance region is provided in the well regionExamples of(B) in the figure is p^-When a high resistance area is provided in the offset areaReference exampleIt is. 1A is a cross-sectional view of the main part cut along the line A-A ′ in FIG. 1, and FIG. 2B is a cross-sectional view of the main part cut along the line B-B ′ in FIG. 1. Of course, in the figure, the high resistance regions 57 and 58 penetrate through the junction, but they do not have to penetrate. As shown in FIG.InIn this case also, the parasitic resistance increases.
[0041]
  In FIG. 1, the first high resistance region 51 and the second high resistance region 52 may be formed by combining the above-described embodiments.
[0042]
【The invention's effect】
  According to the invention, n^-Well territoryRegionalProviding a high resistance region in part by forming an open region, forming an opposite conductivity type region, and further forming a trench grooveInTherefore, the high breakdown voltage n-channel MOSFE of each n-channel level shifterT'sN region connected to the power supply without impairing the breakdown voltage characteristicsAreaParasitic resistance existing between the drain region and the drain region can be increased. As a result, the drain region and the n region, which conventionally occupied a large area, can be obtained.InterregionAs a result, the chip size can be reduced and the cost can be reduced. In addition, since the current flowing through the parasitic resistance can be reduced, the power consumption of the HVIC can be reduced.
[Brief description of the drawings]
FIG. 1 is a plan view of a part of an HVIC according to a first embodiment of the present invention.
2 is an enlarged plan view of the main part of the n-channel MOSFET portion of FIG. 1;
3 is a cross-sectional view of the main part taken along the line A-A ′ of FIG. 1;
4 is a cross-sectional view taken along line B-B ′ of FIG.Reference exampleCross section of the main part
FIG. 5 is a plan view of an essential part of a second embodiment of the present invention.
FIG. 6 of the present inventionReference exampleMain part plan view
FIG. 7 shows the first aspect of the present invention.3In the embodiment, when the opening portion of the high resistance region is crushed, FIG.^-When a high resistance region is provided in the well regionExamples of(B) in the figure is p^-When a high resistance region is provided in the offset regionReference exampleCross section of the main part
FIG. 8 shows the first aspect of the present invention.4In the embodiment, when the high resistance region is formed by the opposite conductivity type region, FIG.^-When a high resistance region is provided in the well regionExample ofIt is a cross-sectional view of the main part.^-When a high resistance region is provided in the offset regionReference exampleCross section of the main part
FIG. 9 is a first view of the present invention.5In the embodiment, the high resistance region is formed by a trench groove, and FIG.^-When a high resistance region is provided in the well regionExamples of(B) in the figure is p^-A high resistance area was provided in the offset area.Reference exampleCross section of the main part
FIG. 10 is a circuit configuration diagram that focuses on the power section of the motor control inverter.
FIG. 11 HVIC element configuration diagram
FIG. 12 Basic configuration diagram of LSU
FIG. 13 is a plan view of the main part of a high voltage IC having a conventional high voltage n channel level shifter and high voltage p channel level shifter formed by self-isolation.
14 is a cross-sectional view of the main part taken along the line C-C ′ of FIG. 13;
15 is a cross-sectional view of a principal part taken along the line D-D ′ in FIG. 13;
[Explanation of symbols]
          100 p^-substrate
          1 n^-Well region
          2 p^-Offset area
          3 n region
          4 p-well region
          5 n drain region
          6 p⁺region
        10 n⁺Source area
        11 1n⁺Source area
        12 2n⁺Source area
        13 n⁺region
        14 n⁺region
        15 p⁺region
        16 p⁺region
        17 p⁺Source area
        18 p⁺Drain region
        21 opening
        22 opening
        31, 32 Gate electrode
        41 COM electrode
        42 Drain electrode
        43 High potential electrode
        44 Low potential electrode
        51-58 High resistance region
        61 n-channel MOSFET
        62 p-channel MOSFET
        70 Three-phase motor
        71 Power module
        72 Main circuit drive circuit
        VCC2 Main circuit power supply
        VCC2H Main circuit power supply high potential side / high potential side potential
        VCC2L Main circuit power supply low potential side / low potential side potential
        VCC HVIC power supply
        HVJT high voltage structure
        RL1 Level shift resistor
        RL2 Level shift resistor
        Terminal connected to COM VCC2L
        G Gate terminal
        OUT Drain terminal
        U-VCC VCC / terminal potential connected to the high potential side of VCC
        Terminal / terminal potential connected to low potential side of U-OUT VCC
        V-OUT VCC / terminal potential connected to the low potential side of VCC
        Terminal connected to the low potential side of W-OUT VCC
        Q1-Q6 IGBT
        D1-D6 diode
        GDU gate drive circuit
        CU control circuit
        LSU shift register
        HVIC High voltage IC
        t1 diffusion depth (n^-Where the well region opening is crushed)
        t2 diffusion depth (p^-(Where the offset area opening is crushed)
        Xj1 diffusion depth (n^-Well region)
        Xj2 diffusion depth (p^-Offset area)
        R1 parasitic resistance
        R2 parasitic resistance

Claims (4)

An n-type well region is formed in a p-type semiconductor substrate, a gate drive circuit of a power device and a lateral n-channel MOSFET are formed in the well region, and the n region to which the high potential side of the main power supply is connected is It is provided on the entire periphery of the gate drive circuit, wherein the n of the high withstand voltage separating unit has, the high breakdown voltage isolation unit is the gate drive circuit between the n-channel MOSFET source region, a gate electrode and a drain region In a high voltage IC that surrounds the outside of the region and is connected to the drain region of the n-channel MOSFET via a level shift resistor on the high potential side of the main power supply, a well between the drain region and the n region A high breakdown voltage IC, wherein an opening in which no n-type region exists locally in the entire depth direction of the well region is formed in the region. 2. The high breakdown voltage IC according to claim 1, wherein the opening of the well region is a portion where the semiconductor substrate is exposed because the well region is not locally formed . 2. The high breakdown voltage IC according to claim 1 , wherein the opening of the well region is a trench groove that penetrates the well region locally and reaches the semiconductor substrate. High voltage IC according to claim 1 opening of said well region, wherein the same p-type as the semiconductor substrate, and a diffusion layer through said well region locally reach the semiconductor substrate .

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