JP2005311211A - Horizontal semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a horizontal semiconductor device which is improved on the tradeoff characteristic between the on-state breakdown voltage and the current driving capability of the device. <P>SOLUTION: In a surface layer of an n-type semiconductor substrate 1, a p-type well layer 2 is formed. In a surface layer of the p-type well layer 2, an n-type source layer is formed. An n-type source layer 4a in the linear portion consists of a highly doped diffusion layer 44a while an n-type source layer 4b in the curved portion consists of a lightly doped diffusion layer 44b. In the surface layer of the p-type well layer 2, a p-type contact layer 3 is so formed as to be in contact with the n-type source layer 44a and 44b. Meanwhile, in the surface layer of the n-type semiconductor substrate 1, an n-type drain layer 10 is formed away from the p-type well layer 2. A source electrode is so formed that its end 77 may be in contact with the n-type source layer 4a in the linear portion while being away from the n-type source layer 4b in the curved portion. Due to this structure, resistance (Rn5 to Rn8) in the n-type source layer 4b becomes large, suppressing the concentration of an electron flow Ie in a drain corner 15. Since a channel is not eliminated, the on-state breakdown voltage can be increased without sacrificing the current driving capability. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a lateral semiconductor device formed on a semiconductor layer.

In recent years, with the advancement of isolation technology such as junction isolation and dielectric isolation, high voltage devices such as lateral diodes, insulated gate bipolar transistors (hereinafter referred to as IGBTs), MOSFETs, their drive circuits, control circuits and protection Development of high voltage power ICs in which circuits are integrated on a single silicon substrate has been actively conducted. In particular, the progress of dielectric isolation technology that combines bonded substrates and trench technology (groove technology) enables the integration of multiple high-voltage bipolar devices (for example, bipolar transistors and IGBTs) The field of application of high voltage power ICs has been greatly expanded. For example, an IGBT is applied to an integrated circuit having a multi-output such as a one-chip totem pole circuit to which an IGBT is applied and a display driving IC.
In the development of a high-voltage power IC, it is essential to improve the performance of a high-voltage output device that directly drives a load, and to improve the characteristics of an output circuit including the output device. Since the high voltage MOSFET is an indispensable device in the configuration of the output circuit, even if the MOSFET is not used as an output device, the performance of the high voltage MOSFET is high as well as the performance of the output device that drives the load. This greatly affects the output characteristics of the withstand voltage power IC.

FIG. 15 shows an example of an output circuit of a high voltage power IC. This circuit is mounted on a high voltage power IC that drives a flat panel display. In the figure, VL, Vin1, Vin2, Vss, VH, and Vout indicate respective terminals of the circuit, VL is a high potential terminal of a low voltage source, Vin1, Vin2 are input terminals of the shift register 21, Vss is a low voltage power source, and A common low potential terminal (ground terminal) of the high voltage power supply, VH is a high potential terminal of the high voltage power supply, and Vout is an output terminal. N1 and N2 are IGBTs serving as output devices. D1 and D2 are diodes, P1 is a p-channel MOSFET, N3 is an n-channel MOSFET, ZD is a Zener diode, and R1 and R2 are resistors. Reference numeral 19 denotes a buffer, and 20 denotes a level shifter.
The operation of this circuit will be described. A signal for driving the output devices N1 and N2 is inputted from the Vin1 or Vin2 to the shift register 21, and a signal for driving the N2 is given to the gate of P1 through the level shifter 20. When P1 is turned on, N2 is turned on. At that time, an off signal is input to N1 via the buffer 19, and N1 is turned off. Next, when P1 is turned off and N3 is turned on, N2 is turned off and N1 is turned on. In this circuit, IGBTs N1 and N2 are devices that drive a load as output devices, and N3 and P1 are both high breakdown voltage lateral MOSFETs. N3 and P1 do not directly drive the load, but play an important role of driving the output devices N1 and N2.

Therefore, if the characteristics of both devices, such as the withstand voltage characteristics, are insufficient, even if the characteristics of N1 and N2 are good, the characteristics cannot be fully obtained, and the output characteristics of the high withstand voltage power IC are It will be unsatisfactory. As described above, in the high breakdown voltage power IC, the breakdown voltage characteristics of the high breakdown voltage lateral MOSFETs such as N3 and P1 constituting the output circuit are important as well as the characteristics of the output device.
FIG. 16 is a cross-sectional view of a principal part when a lateral MOSFET is formed on a semiconductor region. In the device of this figure, an n-type semiconductor substrate 1 is considered as the first conductivity type semiconductor layer, and the conductivity type of the channel of the MOSFET is n-type.
A p-type well layer 2, a p-type contact layer 3, and an n-type source layer 4 are formed on the surface layer of the n-type semiconductor substrate 1. An n-type drain layer 10 is formed on the surface layer of the n-type semiconductor substrate 1 at a predetermined distance from the p-type well layer 2. The n-type semiconductor region 1 sandwiched between the p-type well layer 2 and the n-type drain layer 10 becomes an n-type drift region 13. A gate electrode 8 is formed on the p-type well layer 2 via a gate oxide film 6. A source electrode 7 is formed on the n-type source layer 4 and the p-type contact layer 3, and a drain electrode 11 is formed on the n-type drain layer 10. A source terminal S, a gate terminal G, and a drain terminal D are connected to the source electrode 7, the gate electrode 8, and the drain electrode 11, respectively.

As shown in this cross-sectional view, in the lateral MOSFET, all of the source electrode 7, the gate electrode 8, and the drain electrode 11 are formed on the same surface side. Electrons that carry current are injected from the n-type source layer 4 into the n-type drift region 13 through the n-type channel region 5 and enter the n-type drain layer 10.
FIG. 17 is a plan view of an essential part of the lateral MOSFET having the cross-sectional structure of FIG. 16, and is an enlarged detailed view of FIG. In this figure, the surface electrode pattern is omitted. Usually, a pattern in which source / gate regions 9 and drain regions 12 are arranged in a comb-teeth shape as shown in FIG. Here, the source / gate region 9 is a place where the n-type source layer 4, the gate electrode 8 and the source electrode 7 are formed, and the drain region 12 is a place where the n-type drain layer 10 and the drain electrode 11 are formed. is there. When the combination of the n-type source layer 4, the p-type well layer 2, the n-type drift region 13 and the n-type drain layer 10 is called a unit cell, the surface pattern of the device is an arrangement of the unit cells. The number of unit cells to be arranged is determined by the amount of current required for the device. The width of the n-type drift region 13 is determined by the required breakdown voltage of the device.

The cell pattern shown in FIG. 17 is composed of three parts. The first region is a portion where the source / gate region 9 and the drain region 12 are arranged in parallel (the portion where the straight portion 4a of the n-type source layer is arranged). The second region is a portion where the edge portion of the drain region 12 (the tip portion of the teeth of the comb pattern) is surrounded by the source / gate region 9 (the portion where the curved portion 4b of the n-type source layer is disposed). . The third region is a portion where the edge portion of the source / gate region 9 (the tip portion of the teeth of the comb pattern) is surrounded by the drain region 12 (the portion where the convex portion of the n-type source layer 4 is disposed). . Here, the second region is called a drain corner 15, and the third region is called a source corner 14. The present invention relates to this drain corner 15.
When one device is constituted by a large number of unit cells, the surface pattern of the device is formed from the three portions described above. However, when the rated current of the device is small, the n-type drift region 13 is arranged in a ring shape, the source / gate region 9 or the drain region 12 is completely surrounded by one region, and the drain corner 15 or In some cases, only one of the source corners 14 exists and the other does not exist.

For example, as shown in FIG. 18, the source corner 14 does not exist in an element having a surface pattern in which the drain region 12 is completely surrounded by the source / gate region 9. Conversely, in the surface pattern in which the source / gate region 9 is surrounded by the drain region 12, the drain corner 15 does not exist. In general, only the drain corner 15 is often present as shown in FIG.
In the lateral MOSFET, the on-breakdown voltage, that is, the FBSOA (forward safe operating region) characteristics are important as well as the off-breakdown voltage. The on-state breakdown voltage described here refers to the application of a predetermined gate voltage to flow an on-current, the voltage is increased while the on-current is flowing, and the MOSFET enters the avalanche in a conductive state, and is destroyed by avalanche multiplication. It is defined as the voltage just before the occurrence. The off breakdown voltage is an avalanche voltage that causes avalanche multiplication in a state where a leakage current flows without applying a gate voltage, as is generally known.

Normally, the on-breakdown voltage is lower than the off-breakdown voltage at which avalanche multiplication occurs from the leakage current state because avalanche multiplication occurs from a large on-current. Therefore, in the lateral MOSFET, it becomes a problem how to secure an on-breakdown voltage comparable to the off-breakdown voltage.
Here, consider the weak point with respect to the ON breakdown voltage of the lateral MOSFET. In the surface patterns of FIGS. 17 and 18, the drain region 12 is in a convex state at the drain corner 15, so the electric field is high. FIG. 19 is a detailed view in which the drain corner 15 of FIGS. 17 and 18 is enlarged. As shown in FIG. 19, the n-type drain layer 10 at the drain corner 15 is where the electron stream Ie, which is majority carriers injected from the n-type source layer 44a, is concentrated. Therefore, the drain corner 15 is the weakest region with respect to the ON breakdown voltage.

Since the ON breakdown voltage is limited by the drain corner 15, it is necessary to improve the structure of the drain corner 15 with the aim of improving the ON breakdown voltage. As an example of improving the structure of the drain corner 15,
(1) Introduction of an offset region for the purpose of electric field relaxation at the drain corner 15 (for example, Patent Document 1)
(2) A method of deleting the n-type source layer 4 from the drain corner 15 for the purpose of preventing the inflow of the electron flow e (for example, Patent Document 2) has been proposed.
However, the method (1) imposes sacrifices such as an increase in device area due to the introduction of an offset region and a decrease in drive current in (2). As described above, the current driving capability is sacrificed to improve the ON breakdown voltage.

In addition, in order to improve the avalanche resistance and suppress the occurrence of secondary breakdown, an example in which the channel side of the n-type source layer is formed with a low concentration diffusion layer to make it difficult to turn on the parasitic transistor has been reported (for example, Patent Document 3).
Japanese Patent Laid-Open No. 6-244412 JP 2000-156495 A JP-A-8-186254, FIGS. 1 and 12

As described above, the lateral MOSFET has a problem of securing an on-breakdown voltage that is about the same as the off-breakdown voltage, and it is necessary to improve the drain corner 15 that limits the on-breakdown voltage characteristics.
However, in the prior art, the current drive capability of the element, such as an increase in device area due to the introduction of the offset region, or the non-formation of the curved portion 4b for the purpose of channel deletion of the drain corner 15 (not forming the n-type source layer 4). The ON breakdown voltage is improved at the expense of lowering.
Therefore, in the development of the lateral MOSFET, improvement of the trade-off characteristics between the on-breakdown voltage and the current drive capability has become a major issue.
In view of the above problems, an object of the present invention is to provide a lateral semiconductor device such as a high breakdown voltage lateral MOSFET having improved trade-off characteristics between on breakdown voltage and current drive capability of the element.

  To achieve the above object, a second conductivity type well layer selectively formed on the surface layer of the first semiconductor layer, and a high concentration selectively formed on the surface layer of the second conductivity type well layer. A second conductivity type contact layer, a first conductivity type source layer selectively formed on a surface layer of the second conductivity type well layer, and the first conductivity type source layer and the first semiconductor layer. A gate electrode formed on the second conductivity type well layer via a gate insulating film; a source electrode formed on the second conductivity type contact layer; and the first conductivity type source layer; A high-concentration first conductivity type drain layer formed on the surface layer of the semiconductor layer apart from the second conductivity type well layer and a drain electrode formed on the first conductivity type drain layer are provided. In the lateral semiconductor device, the second conductivity type well layer and the first conductivity type The surface pattern of the rain layer is such that the second conductivity type well layer end line and the first conductivity type drain layer end line face each other, and the length of the opposing second conductivity type well layer end line is A corner portion longer than the length of the end line of the first conductivity type drain layer is provided, and the first conductivity type source layer is not in contact with the source electrode at the corner portion.

The first conductivity type source layer at the corner may be formed of a low-concentration diffusion layer having a lower impurity concentration than the other source layers.
The first conductivity type source layer is formed of two diffusion layers of a high concentration diffusion layer and a low concentration diffusion layer having a lower impurity concentration than the high concentration diffusion layer at the corner portion, and the outside of the corner portion A high concentration diffusion layer may be formed, and the low concentration diffusion layer may be formed inside the corner portion.
The first conductivity type source layer is formed of two diffusion layers of a high concentration diffusion layer and a low concentration diffusion layer having a lower impurity concentration than the high concentration diffusion layer at the corner portion, and the outside of the corner portion A high-concentration diffusion layer is formed, the high-concentration diffusion layer is preferably formed with an overhanging portion inward of the corner portion, and the low-concentration diffusion layer is formed so as to sandwich the overhanging portion.

The tip of the overhanging portion may be formed in the second conductivity type contact layer. The tip of the overhanging portion may be formed in a second conductivity type high concentration diffusion layer separated from the second conductivity type contact layer.
Also, a second conductivity type well layer selectively formed on the surface layer of the first semiconductor layer, and a high concentration second conductivity type contact layer selectively formed on the surface layer of the second conductivity type well layer A first conductivity type source layer selectively formed on a surface layer of the second conductivity type well layer, and a second conductivity type well layer sandwiched between the first conductivity type source layer and the first semiconductor layer A gate electrode formed on a gate insulating film, a source electrode formed on the second conductivity type contact layer and the first conductivity type source layer, and a surface layer of the first semiconductor layer; In the lateral semiconductor device, comprising a first conductivity type drain layer of high concentration selectively formed apart from the second conductivity type well layer, and a drain electrode formed on the first conductivity type drain layer. Surface pattern of the second conductivity type well layer and the first conductivity type drain layer However, the second conductivity type well layer end line and the first conductivity type drain layer end line are opposed to each other, and the length of the opposed second conductivity type well layer end line is equal to the first conductivity type drain layer. A corner portion that is longer than the length of the layer end line, and the first conductivity type source layer is formed of two diffusion layers, a high concentration diffusion layer and a low concentration diffusion layer having a lower impurity concentration than the high concentration diffusion layer, The high concentration diffusion layer is formed outside the corner portion, the low concentration diffusion layer is formed inside the corner portion, and the source electrode is in contact with only the high concentration diffusion layer in the source layer. To do.

The first conductivity type source layer is formed of two diffusion layers of a high concentration diffusion layer and a low concentration diffusion layer having a lower impurity concentration than the high concentration diffusion layer at the corner portion, and the outside of the corner portion Forming a high-concentration diffusion layer, wherein the high-concentration diffusion layer has an overhanging portion formed in an inward direction of the corner portion, and the low-concentration diffusion layer is formed so as to sandwich the overhanging portion; The source electrode is in contact with only the high concentration diffusion layer.
Also, a second conductivity type well layer selectively formed on the surface layer of the first semiconductor layer, and a high concentration second conductivity type contact layer selectively formed on the surface layer of the second conductivity type well layer A first conductivity type source layer selectively formed on a surface layer of the second conductivity type well layer, and a second conductivity type well layer sandwiched between the first conductivity type source layer and the first semiconductor layer A gate electrode formed on a gate insulating film, a source electrode formed on the second conductivity type contact layer and the first conductivity type source layer, and a surface layer of the first semiconductor layer; In the lateral semiconductor device, comprising a first conductivity type drain layer of high concentration selectively formed apart from the second conductivity type well layer, and a drain electrode formed on the first conductivity type drain layer. Surface pattern of the second conductivity type well layer and the first conductivity type drain layer However, the second conductivity type well layer end line and the first conductivity type drain layer end line are opposed to each other, and the length of the opposed second conductivity type well layer end line is equal to the first conductivity type drain layer. A corner portion that is longer than the length of the layer end line is provided, and the first conductivity type source layer is alternately in contact with two diffusion layers of a high concentration diffusion layer and a low concentration diffusion layer having a lower impurity concentration than the high concentration diffusion layer. The source electrode is in contact with only the high-concentration diffusion layer in the source layer.

The tip of the high concentration diffusion layer may be formed in the second conductivity type contact layer.
The tip of the high-concentration diffusion layer may be formed adjacent to the second conductivity type inversion prevention layer separated from the second conductivity type contact layer.

According to this invention,
(1) The n-type source layer at the drain corner is not brought into contact with the source electrode.
(2) The n-type source layer at the drain corner is formed of a low concentration diffusion layer, and the low concentration diffusion layer and the source electrode are not brought into contact with each other.
(3) An n-type source layer at the drain corner is formed of a high-concentration diffusion layer and a low-concentration diffusion layer, and only the high-concentration diffusion layer portion is brought into contact with the source electrode.
(4) The low concentration diffusion layer is divided into a plurality of portions, a high concentration diffusion layer is formed in the divided gap, and the high concentration diffusion layer is formed in the n-type contact layer. And source electrode are not in contact.
By forming this low-concentration diffusion layer, the electron flow flowing from the n-type source layer to the n-type drain layer through the channel is suppressed, and the concentration of the electron flow at the drain corner is avoided, thereby improving the on-breakdown voltage. be able to.

Further, since the electron current at the drain corner is not completely removed, the current driving capability can be increased as compared with the case where the n-type source layer is completely removed at the drain corner.
Furthermore, since the planar structure of the drain corner is the same as the conventional one, there is no increase in device area, and current (current density) per unit device area is not sacrificed.
From the above, it is possible to achieve an improvement in the trade-off characteristics between the on-breakdown voltage and current drive capability of the lateral MOSFET.
Further, by forming a low concentration diffusion layer at the drain corner, a voltage drop is generated by an electron flow flowing through the low concentration diffusion layer, and an increase in voltage applied to the pn junction between the n-type source layer and the p-type well layer is suppressed. Thus, the injection of electrons from the n-type source layer to the p-type well layer is suppressed, and the secondary breakdown of the npn transistor composed of the n-type source layer-p-type well layer-n-type semiconductor substrate is prevented, and the ON breakdown voltage Can be improved.

According to the embodiment of the present invention, in a high breakdown voltage lateral semiconductor device in which a planar pattern of a drift region is a comb tooth shape or a ring shape, current (for example, electron current) concentration at a drain corner surrounded by a drain layer by a source layer This is to improve the ON breakdown voltage.
In the drawings described below, the same parts as those in the conventional structure are denoted by the same reference numerals. Further, although an n-channel type MOSFET is described here, the same explanation is valid for a p-channel type MOSFET by reversing the conductivity type.

FIG. 1 is a block diagram of a horizontal semiconductor device according to a first embodiment of the present invention, in which FIG. 1 (a) is a plan view of an essential part, and FIG. 1 (b) is cut along a line aa in FIG. The principal part sectional drawing and the figure (c) are principal part sectional drawings cut | disconnected by the bb line | wire of the figure (a). This figure is a plan view of the drain corner of the lateral MOSFET, and is drawn in consideration of the n-channel MOSFET. FIG. 1A corresponds to FIG. The drain corner 15 is a place where the length of the end line of the p-well layer 2 is longer than the length of the end line of the n-type drain layer 10.
A p-type well layer 2 is formed on the surface layer of the n-type semiconductor substrate 1, and a p-type contact layer 3 is formed on the surface layer of the p-type well layer 2. Next, the straight portion 4a and the curved portion 4b of the n-type source layer 4 are formed on the surface layer of the p-type well layer 2 by the high concentration diffusion layer 44a having the same impurity concentration. Next, apart from the p-type well layer 2, an n-type drain layer 10 is formed on the surface layer of the n-type semiconductor substrate 1. The n-type semiconductor region 1 sandwiched between the p-type well layer 2 and the n-type drain layer 10 becomes an n-type drift region 13. A gate electrode 8 is formed on the p-type well layer 2 via a gate oxide film 6. A source electrode 7 is formed on the n-type source layer 4 and the p-type contact layer 3, and a drain electrode 11 is formed on the n-type drain layer 10. A source terminal S, a gate terminal G, and a drain terminal D are connected to the source electrode 7, the gate electrode 8, and the drain electrode 11, respectively. In the figure, 5 is an n-type channel region.

In the planar pattern, the n-type drain layer 10 is surrounded by the n-type drift region 13, the n-type drift region 13 is surrounded by the p-type well layer 2, and the n-type source layer 4 and a p-type contact not shown in the p-type well layer 2. Layer 3 is formed. The straight portion 4a and the source electrode end 77 are in contact with each other, but the n-type source layer 4b and the source electrode end 77 in the curved portion are separated.
In FIG. 1A, the high-concentration diffusion layer 44a forming the n-type source layer 4 has resistors (Rn1 to Rn4), and the curved portion 4b and the source electrode 7 are not in contact with each other. The flowing electron stream Ie flows from the straight line portion 4a. The resistance along the arc of the n-type source layer 4b increases as the distance from the straight portion 4a increases. That is, in the case of FIG. 1A, the resistance at the point A is the largest.
Accordingly, since the electron flow Ie flows through this resistance, the electron flow Ie is limited at the drain corner 15. In addition, as the electron current Ie increases, the voltage (voltage drop) generated by the resistance increases and the current limiting function increases, and the concentration of the electron current Ie at the drain corner 15 is suppressed, and the ON The breakdown voltage can be improved.

Further, since the potential of the curved portion 4b rises due to the resistance, the rise of the junction potential between the p-type well layer 2 and the curved portion 4b is also suppressed, and secondary breakdown at this location (drain corner 15) is difficult to occur. Therefore, the on-breakdown voltage of the element can be improved. In addition, since the channel is not deleted at the drain corner 15, the ON breakdown voltage can be improved without sacrificing the current driving capability.
However, since the curved portion 4b of the drain corner 15 is a high-concentration diffusion layer 44a having the same high impurity concentration as the straight portion 4a, the resistance (Rn1 to Rn4) is small and the effect of the voltage drop is small. . An embodiment in which this effect is increased will be described below.

2A and 2B are configuration diagrams of a horizontal semiconductor device according to a second embodiment of the present invention, in which FIG. 2A is a plan view of an essential part, and FIG. 2B is cut along a line aa in FIG. The principal part sectional drawing and the figure (c) are principal part sectional drawings cut | disconnected by the bb line | wire of the figure (a). These are diagrams corresponding to FIG.
The difference from FIG. 1 is that the curved portion 4b is formed of a low concentration diffusion layer 44b having a lower impurity concentration than the straight portion 4a. Similar to FIG. 1A, the curved portion 4 b is not in contact with the source electrode 7.
Since the curved portion 4b is formed by the low concentration diffusion layer 44b, the resistance (Rn5 to Rn8) is larger than the resistance (Rn1 to Rn4) shown in FIG. Since the electron current Ie in the drain corner 15 flows through this large resistance (Rn5 to Rn8), the current limiting effect is greater than in the case of FIG. Therefore, if the electron current Ie increases, the current limiting function works more and more, and the concentration of the electron current Ie at the drain corner 15 can be suppressed than in the case of FIG.

Further, since the potential of the curved portion 4b is higher than that in FIG. 1, the increase in the junction potential between the p-type well layer 2 and the curved portion 4b is also suppressed as compared with FIG. 1, and secondary breakdown is less likely to occur than in the case of FIG. This is because the potential drop caused by the electron flow Ie flowing through the low-concentration diffusion layer 44b and the hole current generated by the junction of the n-type drain layer 10 and the n-type drift region 13 entering the avalanche are generated by the p-type well layer. The potential drop generated by flowing through 2 cancels out, and the rise in junction potential between the p-type well layer 2 and the curved portion 4b is suppressed. Therefore, the on-breakdown voltage of the element can be further improved. In addition, since the drain corner 15 does not delete the channel, the ON breakdown voltage can be improved without sacrificing the current driving capability.
The ion implantation process for forming the low concentration diffusion layer 44b may be introduced immediately before the ion implantation process for forming the high concentration diffusion layer 44a. The heat treatment step may be the same as that of the high concentration diffusion layer 44a. Alternatively, it is also possible to apply a CMOS (Complementary MOS) LDD (Light Doped Drain) layer constituting the control circuit to the low concentration diffusion layer 44b.

FIGS. 3A and 3B are configuration diagrams of a horizontal semiconductor device according to a third embodiment of the present invention. FIG. 3A is a plan view of the main part, and FIG. 3B is cut along the line aa in FIG. The principal part sectional drawing and the figure (c) are principal part sectional drawings cut | disconnected by the bb line | wire of the figure (a). This figure is a plan view of the drain corner of the lateral MOSFET, and is drawn in consideration of the n-channel MOSFET. FIG. 3A is a diagram corresponding to FIG.
The difference from FIG. 2 is that the curved portion 4b is not formed of a single low concentration diffusion layer 44b, but a low concentration diffusion layer 44b and a high concentration diffusion layer 44c having an impurity concentration higher than that of the low concentration diffusion layer 44b on the outside. This is the point. Also in this case, the curved portion 4b and the source electrode are prevented from contacting each other.
Even in this case, the same effect as described above can be obtained by using the resistance of the curved portion 4b formed by the low concentration diffusion layer 44b.

Note that the manufacturing cost can be reduced by forming the curved portion 4b formed by the high concentration diffusion layer 44c in the drain corner 15 and the straight portion 4a formed by the high concentration diffusion layer 44a in the straight portion under the same diffusion conditions. Can do.
Further, the high concentration diffusion layer 44c at the drain corner 15 serves to make the electron flow Ie to the low concentration diffusion layer 44b more uniform in the arc portion than in FIG. 2, and the electron flow Ie at the point A is shown in FIG. It can be made larger and the on-resistance can be reduced.

4 and 5 are configuration diagrams of a horizontal semiconductor device according to a fourth embodiment of the present invention. FIG. 4 (a) is a plan view of an essential portion, and FIG. 4 (b) is an enlarged view of a portion K in FIG. 4 (a). FIG. 5 (a) is a cross-sectional view of a main part cut along a line aa in FIG. 4 (a), FIG. 5 (b) is a cross-sectional view of a main part cut along a line bb in FIG. FIG.5 (c) is principal part sectional drawing cut | disconnected by the cc line | wire of Fig.4 (a). FIG. 4A is a diagram corresponding to FIG.
The difference from FIG. 3 is that the low concentration diffusion layer 44b at the drain corner 15 is divided and the high concentration diffusion layer 44c projects between them. The tip of the protruding portion B of the high-concentration diffusion layer 44c is formed in the p-type contact layer 3 (inner side from the p-type contact layer end 3a) that is similarly extended. Since the tip of the overhanging portion B and the end of the low-concentration diffusion layer 44b are on the same circular arc line, the tip of the overhanging portion of the p-type contact layer end 3a is not reliably formed with a channel at the overhanging portion B. It protrudes more convexly than the tip of the high concentration diffusion layer 44c. The protruding portion of the p-type contact layer end 3a is formed to be narrower than the width of the high concentration diffusion layer 44c, and the high concentration diffusion layer 44c and the low concentration diffusion layer 44b are connected when the high concentration diffusion layer 44c is formed. To. Further, even if an island-like p-type inversion preventing layer floating in potential is formed so as to cover the tip of the protruding portion of the high concentration diffusion layer 44c, a channel is not formed.

  Since the electron flow Ie flows from the projecting portion B of the high concentration diffusion layer 44c to the low concentration diffusion layer 44b, the resistance in the high concentration diffusion layer 44c increases from FIG. The effect is increased.

FIGS. 6 and 7 are configuration diagrams of a high breakdown voltage lateral semiconductor device according to a fifth embodiment of the present invention. FIG. 6 (a) is a plan view of an essential part, and FIG. 6 (b) is a diagram K of FIG. 6 (a). FIG. 7A is a cross-sectional view of a main part cut along a line aa in FIG. 6A, and FIG. 7B is a cross-sectional view of a main part cut along a line bb in FIG. 6A. FIG. 7 and FIG. 7C are cross-sectional views of relevant parts cut along the line cc in FIG. FIG. 6A is a view corresponding to FIG.
The difference from FIGS. 4 and 5 is that the tip of the overhanging portion B of the high concentration diffusion layer 44c is located inside the end of the low concentration diffusion layer 44b. Even if it is such a structure, the effect similar to FIG. 4 is acquired.

8A and 8B are configuration diagrams of a horizontal semiconductor device according to a sixth embodiment of the present invention, in which FIG. 8A is a plan view of an essential part, and FIG. 8B is cut along a line aa in FIG. The principal part sectional drawing and the figure (c) are principal part sectional drawings cut | disconnected by the bb line | wire of the figure (a).
The difference from FIG. 3 is that the source electrode 7 is connected to the high concentration diffusion layer 44c of the n-type source layer 4b in the curved portion.
In this case, the electron flow Ie flowing into the low concentration diffusion layer 44b flows from the high concentration diffusion layer 44a of the straight portion 4a and from the curved portion of the source electrode end 77 via the high concentration diffusion layer 44c of the curved portion 4b. Therefore, the electron flow Ie at the drain corner 15 is made more uniform than in the case of FIG. 3, and is effective in reducing the on-voltage.

FIGS. 9 and 10 are configuration diagrams of a horizontal semiconductor device according to a seventh embodiment of the present invention. FIG. 9A is a plan view of an essential part, and FIG. 9B is an enlarged view of a portion K in FIG. FIG. 10 (a) is a cross-sectional view of the main part cut along line aa in FIG. 9 (a), FIG. 10 (b) is a cross-sectional view of the main part cut along line bb in FIG. 9 (a), FIG.10 (c) is principal part sectional drawing cut | disconnected by the cc line | wire of Fig.9 (a). These figures correspond to FIGS. 4 and 5.
4 and 5 is that the source electrode 7 is brought into contact with the high-concentration diffusion layer 44c at the drain corner 15. Therefore, the source electrode end 77 is in contact with the high concentration diffusion layer 44c. Since the source electrode end 77 is in contact with the high-concentration diffusion layer 44c, the electron current Ie at the drain corner 15 is made more uniform than in FIGS. 4 and 5, which is effective in reducing the on-resistance.

11A and 11B are configuration diagrams of a horizontal semiconductor device according to an eighth embodiment of the present invention, in which FIG. 11A is a plan view of the main part, FIG. 11B is an enlarged view of the L part of FIG. FIG. 2C is a cross-sectional view of the main part taken along the line aa in FIG. 11A and 11B are diagrams corresponding to FIGS. 9A and 9B. The main part sectional view cut along line aa in FIG. 11A corresponds to FIG. 10A, and the figure cut along line bb in FIG. The figure taken along the line cc in FIG. 11A corresponds to the case where there is no high concentration diffusion layer 44c in FIG. 10C. 9 and 10 is that the high concentration diffusion layer 44c of the n-type source layer 4b in the curved portion is divided, and the source electrode 7 is connected to the divided high concentration diffusion layer 44c.
In this case, since the electron flow Ie flows only from the side surface of the divided low-concentration diffusion layer 44c, the electron flow Ie at the drain corner 15 is suppressed more than in the case of FIGS.

12 and 13 are configuration diagrams of a horizontal semiconductor device according to a ninth embodiment of the present invention. FIG. 12 (a) is a plan view of the main part, and FIG. 12 (b) is an enlarged view of a portion K in FIG. FIG. 13A is a cross-sectional view of a main part cut along a line aa in FIG. 12A; FIG. 13B is a cross-sectional view of a main part cut along a line bb in FIG. FIG.13 (c) is principal part sectional drawing cut | disconnected by the cc line | wire of Fig.12 (a). These figures correspond to FIGS. 6 and 7.
The difference from FIGS. 6 and 7 is that the source electrode 7 is brought into contact with the high-concentration diffusion layer 44 c at the drain corner 15. Since the source electrode end 77 is in contact with the high-concentration diffusion layer 44c, the electron flow Ie at the drain corner 15 is made more uniform than in FIGS. 6 and 7, and the on-resistance is effectively reduced.

14A and 14B are configuration diagrams of a high breakdown voltage lateral semiconductor device according to the tenth embodiment of the present invention. FIG. 14A is a plan view of the main part, and FIG. 14B is an enlarged view of the L part of FIG. FIG. 4C is a cross-sectional view of the main part taken along line aa in FIG. FIG. 14 corresponds to FIG.
The difference from FIG. 11 is that the tip of the protruding portion B of the high concentration diffusion layer 44c is located inside the end of the low concentration diffusion layer 44b. Even with such a configuration, the same effect as in FIG. 11 can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the horizontal semiconductor device of 1st Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the aa line | wire of (a), (c) is Sectional drawing of the principal part cut | disconnected by the bb line of (a). It is a block diagram of the horizontal semiconductor device of 2nd Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the aa line | wire of (a), (c) is Sectional drawing of the principal part cut | disconnected by the bb line of (a). It is a block diagram of the horizontal semiconductor device of 3rd Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the aa line | wire of (a), (c) is Sectional drawing of the principal part cut | disconnected by the bb line of (a). It is a block diagram of the horizontal semiconductor device of 4th Example of this invention, (a) is a principal part top view, (b) is the K section enlarged view of (a). It is a block diagram of the horizontal semiconductor device of 4th Example of this invention, (a) is principal part sectional drawing cut | disconnected by the aa line of Fig.4 (a), (b) is b of Fig.4 (a). The principal part sectional drawing cut | disconnected by the -b line | wire, (c) is a figure equivalent to principal part sectional drawing cut | disconnected by the cc line | wire of Fig.4 (a). It is a block diagram of the horizontal semiconductor device of 5th Example of this invention, (a) is a principal part top view, (b) is the K section enlarged view of (a). FIG. 10 is a configuration diagram of a horizontal semiconductor device according to a fifth embodiment of the present invention, in which (a) is a cross-sectional view taken along line aa in FIG. 6 (a), and (b) is b in FIG. 6 (a). FIG. 8C is a cross-sectional view of the main part cut along the line -b, and FIG. 6C is a view corresponding to the cross-sectional view of the main part cut along the line cc in FIG. It is a block diagram of the horizontal semiconductor device of 6th Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the aa line | wire of (a), (c) is Sectional drawing of the principal part cut | disconnected by the bb line of (a). It is a block diagram of the horizontal semiconductor device of 7th Example of this invention, (a) is a principal part top view, (b) is the K section enlarged view of (a). It is a block diagram of the horizontal semiconductor device of 7th Example of this invention, (a) is principal part sectional drawing cut | disconnected by the aa line | wire of Fig.9 (a), (b) is b of FIG.9 (a). Sectional view taken along line -b, (c) is a sectional view taken along line cc in FIG. 9 (a). It is a block diagram of the horizontal semiconductor device of 8th Example of this invention, (a) is a principal part top view, (b) is the L section enlarged view of (a), (c) is aa of (a). Cross-sectional view of the main part cut by wire It is a block diagram of the horizontal semiconductor device of 9th Example of this invention, (a) is a principal part top view, (b) is the K section enlarged view of (a). It is a block diagram of the horizontal semiconductor device of 9th Example of this invention, (a) It is principal part sectional drawing cut | disconnected by the aa line, (b) is cut | disconnected by the bb line of Fig.12 (a) Sectional view (c) of the relevant part is a sectional view of the principal part taken along line cc of FIG. It is a block diagram of the horizontal semiconductor device of 10th Example of this invention, (a) is a principal part top view, (b) is the L section enlarged view of the same figure (a), (c) is a of (a). Cross-sectional view of major parts cut along line -a The figure which shows the output circuit example of high voltage power IC Cross-sectional view of the main part when a lateral MOSFET is formed on a semiconductor region FIG. 11 is a plan view of a main part of a lateral MOSFET having the cross-sectional structure of FIG. Surface pattern diagram with only drain corner 15 of lateral MOSFET Diagram showing electron flow concentrated at the drain corner

Explanation of symbols

1 n-type semiconductor substrate 2 p-well layer 3 p-type contact layer 3a p-contact layer edge 4 n-type source layer (whole: 4a + 4b)
4a n-type source layer (straight line)
4b n-type source layer (curved part)
5 n channel region 6 gate oxide film 7 source electrode 8 gate electrode 9 source / gate region 10 n-type drain layer 11 drain electrode 12 drain region 13 n-type drift region 14 source corner 15 drain corner 19 buffer 20 level shifter 21 shift register 44a high Concentration diffusion layer 44b Low concentration diffusion layer 44c High concentration diffusion layer 77 Source electrode end Ie Electron current S Source terminal G Gate terminal D Drain terminals N1, N2 High breakdown voltage n-channel IGBT
N3 High voltage n-channel MOSFET
P1 High voltage p-channel MOSFET
D1, D2 High voltage diode ZD Constant voltage diode R1, R2 Resistors VL, Vin1, Vin2, Vss, VH, Vout Terminal names

Claims (11)

A second conductivity type well layer selectively formed on the surface layer of the first semiconductor layer, and a high concentration second conductivity type contact layer selectively formed on the surface layer of the second conductivity type well layer; A first conductivity type source layer selectively formed on a surface layer of the second conductivity type well layer; and a second conductivity type well layer sandwiched between the first conductivity type source layer and the first semiconductor layer. A gate electrode formed through a gate insulating film, a source electrode formed on the second conductivity type contact layer and the first conductivity type source layer, and a second electrode on the surface layer of the first semiconductor layer. In a lateral semiconductor device comprising a high-concentration first conductivity type drain layer formed separately from a conductivity type well layer and a drain electrode formed on the first conductivity type drain layer,
The surface pattern of the second conductivity type well layer and the first conductivity type drain layer is such that the second conductivity type well layer end line and the first conductivity type drain layer end line are opposed to each other. A corner portion where the length of the two conductivity type well layer end line is longer than the length of the first conductivity type drain layer end line, and the first conductivity type source layer does not contact the source electrode at the corner portion. A lateral semiconductor device characterized by the above. 2. The lateral semiconductor device according to claim 1, wherein the first conductivity type source layer at the corner portion is formed by a low concentration diffusion layer having an impurity concentration lower than that of the source layer at another portion. At the corner portion, the first conductivity type source layer is formed of two diffusion layers, a high concentration diffusion layer and a low concentration diffusion layer having a lower impurity concentration than the high concentration diffusion layer, and the high concentration source layer is formed outside the corner portion. The lateral semiconductor device according to claim 1, wherein a diffusion layer is formed, and the low-concentration diffusion layer is formed inside the corner portion. At the corner portion, the first conductivity type source layer is formed of two diffusion layers, a high concentration diffusion layer and a low concentration diffusion layer having a lower impurity concentration than the high concentration diffusion layer, and the high concentration source layer is formed outside the corner portion. The diffusion layer is formed, the high-concentration diffusion layer is formed with a projecting portion toward the inside of the corner portion, and the low-concentration diffusion layer is formed so as to sandwich the projecting portion. 2. The horizontal semiconductor device according to 1. The lateral semiconductor device according to claim 1, wherein a tip portion of the protruding portion is formed in the second conductivity type contact layer. The lateral semiconductor device according to claim 1, wherein a tip end portion of the protruding portion is formed in a second conductivity type high concentration diffusion layer separated from the second conductivity type contact layer. A second conductivity type well layer selectively formed on the surface layer of the first semiconductor layer, and a high concentration second conductivity type contact layer selectively formed on the surface layer of the second conductivity type well layer; A first conductivity type source layer selectively formed on a surface layer of the second conductivity type well layer; and a second conductivity type well layer sandwiched between the first conductivity type source layer and the first semiconductor layer. A gate electrode formed through a gate insulating film, a source electrode formed on the second conductivity type contact layer and the first conductivity type source layer, and a second electrode on the surface layer of the first semiconductor layer. In a lateral semiconductor device comprising a high-concentration first conductivity type drain layer formed separately from a conductivity type well layer and a drain electrode formed on the first conductivity type drain layer,
The surface pattern of the second conductivity type well layer and the first conductivity type drain layer is such that the second conductivity type well layer end line and the first conductivity type drain layer end line are opposed to each other. A corner portion where the length of the end line of the two conductivity type well layer is longer than the length of the end line of the first conductivity type drain layer, and the first conductivity type source layer is formed by the high concentration diffusion layer and the high concentration diffusion layer; The low concentration diffusion layer having a low impurity concentration is formed from two diffusion layers, the high concentration diffusion layer is formed outside the corner portion, the low concentration diffusion layer is formed inside the corner portion, and the source layer The lateral semiconductor device according to claim 1, wherein the source electrode is in contact only with the high concentration diffusion layer. At the corner portion, the first conductivity type source layer is formed of two diffusion layers, a high concentration diffusion layer and a low concentration diffusion layer having a lower impurity concentration than the high concentration diffusion layer, and the high concentration source layer is formed outside the corner portion. A diffusion layer is formed, and the high-concentration diffusion layer is formed with an overhanging portion inward of the corner portion, and the low-concentration diffusion layer is formed so as to sandwich the overhanging portion. The lateral semiconductor device according to claim 7, wherein the source electrode is in contact only with the high concentration diffusion layer. A second conductivity type well layer selectively formed on the surface layer of the first semiconductor layer, and a high concentration second conductivity type contact layer selectively formed on the surface layer of the second conductivity type well layer; A first conductivity type source layer selectively formed on a surface layer of the second conductivity type well layer; and a second conductivity type well layer sandwiched between the first conductivity type source layer and the first semiconductor layer. A gate electrode formed through a gate insulating film, a source electrode formed on the second conductivity type contact layer and the first conductivity type source layer, and a second electrode on the surface layer of the first semiconductor layer. In a lateral semiconductor device comprising a high-concentration first conductivity type drain layer formed separately from a conductivity type well layer and a drain electrode formed on the first conductivity type drain layer,
The surface pattern of the second conductivity type well layer and the first conductivity type drain layer is such that the second conductivity type well layer end line and the first conductivity type drain layer end line are opposed to each other. A corner portion where the length of the end line of the two conductivity type well layer is longer than the length of the end line of the first conductivity type drain layer, and the first conductivity type source layer is formed by the high concentration diffusion layer and the high concentration diffusion layer; A lateral semiconductor device, wherein the low concentration diffusion layer having a low impurity concentration is formed so as to alternately contact two diffusion layers, and the source electrode is in contact with only the high concentration diffusion layer of the source layer. The lateral semiconductor device according to claim 9, wherein a front end portion of the high concentration diffusion layer is formed in the second conductivity type contact layer. The lateral semiconductor device according to claim 9, wherein a front end portion of the high-concentration diffusion layer is formed adjacent to a second conductivity type inversion prevention layer separated from the second conductivity type contact layer.

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