JP4193680B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device such as a high breakdown voltage lateral MOSFET formed on a semiconductor substrate.

Recent advances in dielectric isolation technology combining SOI substrate and trench isolation have led to high voltage devices such as lateral diodes, insulated gate bipolar transistors (IGBTs) and lateral MOSFETs, and their drive, control and protection. Development of power integrated circuits (hereinafter abbreviated as power ICs) in which circuits are integrated on a single silicon substrate has become active.
A great merit of manufacturing a power IC on a dielectric isolation substrate using an SOI substrate is that a bipolar device can be applied as a high-side switch, and that these can be multi-outputted. Therefore, an inverter IC for driving a three-phase motor and a driver IC for driving a flat panel display have been developed in which a plurality of totem pole circuits composed of IGBTs are mounted on one chip as output circuits.
When driving the high side switch, a level shift circuit is required. By constructing this level shift circuit with a high breakdown voltage lateral p-channel MOSFET (hereinafter abbreviated as HVPMOS), a simple configuration that does not require a separate power source or capacitor can be achieved. In addition, by increasing the thickness of the gate oxide film of the HVPMOS, the HVPMOS can be directly driven by the output side power supply voltage, and a CMOS level shift circuit combined with an n-channel MOSFET can be realized. As a result, low power consumption of the level shift circuit can be achieved.

Against this background, it is important to develop an HVPMOS having a thick gate oxide film that can withstand the application of the output side power supply voltage, unlike the standard gate oxide film to which the input side power supply voltage is applied. . In this specification, an HVPMOS having a gate oxide film having a standard thickness is called a standard gate HVPMOS, and an HVPMOS having a thick gate oxide film is called a thick film gate HVPMOS.
FIG. 3 is a diagram showing an example of a level shift circuit to which the thick gate HVPMOS is applied. A totem pole circuit composed of two IGBTs (N1, N2) is mounted as the output circuit unit A, and a level constituted by two N-channel MOSFETs (N3, N4) and two HVPMOSs (P1, P2) in the preceding stage A shift circuit section B is mounted. The output device N1 is controlled by Vin1, and N2 is controlled by signals Vin2 and Vin3 that drive the level shift circuit. ZD incorporated in the output circuit unit A is a Zener diode for protecting the gate of N2. Since a high voltage is applied to the output side power supply voltage VH, all the devices other than ZD constituting this circuit are high withstand voltage devices.

The level shift circuit B of this circuit is a known circuit, and the description of its operation is omitted here. This level shift circuit is characterized in that the gates of P1 and P2 can be driven by the output side power supply voltage VH. For this reason, the level shift circuit B can be configured by a normal CMOS circuit, and the power consumption of the level shift circuit B can be greatly reduced.
FIG. 4 is a cross-sectional view of a main part of a conventional semiconductor device in which HVPMOS is formed on an SOI substrate.
A region where each element is formed is an n-type substrate 3 among the substrate 1, the oxide film 2, and the n-type substrate 3 constituting the SOI substrate 100. The n-type conductivity type is selected for the purpose of facilitating the formation of an n-channel element constituting the output circuit of the power IC. Hereinafter, a description will be given of the increase in breakdown voltage of the HVPMOS formed on the SOI substrate.

In order to form HVPMOS on the n-type substrate 3, the p-type offset region 16 is indispensable. The device breakdown voltage (device breakdown voltage) is determined by the avalanche breakdown voltage generated at the junction of the p-type offset region 16 and the n-type drift region 4, and this voltage depends on the formation conditions of the p-type offset region 16. . Therefore, the high durability of the element is implemented by optimizing the formation conditions of the p-type offset region 16.
The structural differences between the thick film gate HVPMOS and the standard gate HVPMOS are (1) the thickness of the gate insulating film and (2) the depth of the p-type source region. The thickness of the thick gate insulating film 11 in (1) is determined by the magnitude of the output side power supply voltage. Further, the diffusion depth of the p-type source region 18 in (2) is determined by the manufacturing method, and the description thereof is omitted here.
Here, the item (1) will be described. The output side power supply voltage is applied to the gate electrode 13 in the thick film gate HVPMOS. Therefore, when the output-side power supply voltage is applied to the drain electrode 15 in a state where the output-side power supply voltage is applied to the gate electrode 13, an electric field concentration occurs in the p-type well region 18 (D portion) immediately below the gate electrode 13, The breakdown voltage tends to decrease due to this electric field concentration. That is, in the thick film gate HVPMOS, not only the withstand voltage structure that secures the withstand voltage in the off state (hereinafter referred to as the off withstand voltage) but also in the on state when a high voltage such as the output side power supply voltage is applied to the gate electrode 13. It is necessary to ensure the withstand voltage (hereinafter referred to as the on-withstand voltage).

Although not shown, in the thick film gate HVPMOS, the source electrode is formed on the gate electrode and the p-type offset region by protruding from the gate electrode, and by setting the protruding length to a predetermined length, It has been reported that the off breakdown voltage can be increased without reducing the total charge amount (see Patent Document 1).
Although not shown, in the thick gate HVPMOS, the gate electrode is formed so as to extend on the offset region, and the length of the gate electrode formed on the offset region is set to a predetermined length. It has been reported that the off breakdown voltage can be increased without reducing the total charge amount (see Patent Document 2).
These patent documents describe a technique for increasing the breakdown voltage of a thick film gate HVPMOS formed on an SOI substrate. However, both documents only refer to the off breakdown voltage, and nothing is described about the on breakdown voltage when a high voltage such as the output side power supply voltage is applied to the gate electrode of the thick film gate HVPMOS.
JP-A-11-145462 JP 2000-252467 A

In the circuit of FIG. 3, as described above, in the thick gate HVPMOS formed on the SOI substrate, the output side power supply voltage is applied to the gate electrode 13. For this reason, a state occurs in which the output-side power supply voltage is applied between the source electrode 14 and the gate electrode 13, and in this applied state, it is necessary to examine the ON breakdown voltage.
As described above, when a negative high voltage is applied only to the drain electrode with respect to the source electrode 14, a high electric field is generated at the junction of the p-type offset region 16 and the n-type drift region 4. However, when a negative high voltage is applied also to the gate electrode 13, a high electric field is generated also in the n-type well region (D portion) immediately below the gate electrode 13, and the on breakdown voltage is lowered by this high electric field. It becomes lower than the off breakdown voltage.
An object of the present invention is to provide a semiconductor device capable of solving the above-described problems and improving the on-breakdown voltage.

To achieve the above object, the selectively formed n-type well region in the surface layer of the n-type semiconductor layer, selectively formed away from the well region in a surface layer of said semiconductor layer a p-type offset region; a p-type source region selectively formed in a surface layer of the well region; a p-type drain region selectively formed in a surface layer of the offset region; and the well region An n-type contact region selectively formed on the surface layer, a gate electrode formed on the semiconductor layer and the well region sandwiched between the source region and the offset region via a gate insulating film; In a semiconductor device having a source electrode formed on the contact region and the source region, and a drain electrode formed on the drain region,
The distance (L1) between the source region end on the surface of the well region sandwiched between the source region and the semiconductor layer and the well region end facing the source region end is the distance between the well region and the offset region. The structure is longer than the distance (L2) between the end of the well region on the surface of the sandwiched semiconductor layer and the end of the offset region facing the well region.

The distance (L1 + L2) between the source region and the offset region facing the source region is preferably 2 μm or more and 20 μm or less.
Further, this semiconductor device may be applied as a high-potential side switch element constituting a level shift circuit that drives a high-side switch or push-pull circuit of a totem pole circuit.

According to the present invention, the distance (L1) between the source region end on the surface of the well region sandwiched between the source region and the semiconductor layer and the semiconductor layer end opposite to the source region end is set to the offset from the well region. By making the distance between the end of the well region on the surface of the semiconductor layer sandwiched between the regions and the end of the offset region facing the well region (L2), a high voltage having the same potential as the drain electrode is applied to the gate electrode. Even when a voltage is applied, generation of a high electric field directly under the gate insulating film can be suppressed, and a decrease in the ON breakdown voltage in this region can be prevented. As a result, even when a voltage equivalent to that of the drain electrode is applied to the gate electrode, an ON breakdown voltage equivalent to the OFF breakdown voltage can be secured.
Further, since the configuration of the present invention can be realized only by adjusting the mask pattern of the n-type well region, the number of process steps is not increased by applying the present invention.

  The best mode for carrying out the present invention is to increase the on-breakdown voltage by making the width of the n-type well region formed immediately below the gate electrode wider than the width of the n-type drift region. . Specific examples will be described below.

FIG. 1 is a cross-sectional view of an essential part of a semiconductor device according to one embodiment of the present invention. The same parts as those in FIG.
The surface concentration of the n-type substrate 3 of the SOI substrate 100 in which the n-type or p-type substrate 1 and the n-type substrate 3 are bonded to each other with the oxide film 2 is approximately 2 × 10 ¹⁷ cm ⁻³ and the diffusion depth is about 2 × 10 ¹⁷ cm ^−3. An n-type well region 17 of about 3 μm is formed, and a p-type offset region 16 having a surface concentration of about 1 × 10 ¹⁶ cm ⁻³ and a diffusion depth of about 2 μm is formed apart from the n-type well region 17. The n-type substrate 3 in which the n-type well region 17 and the p-type offset region 16 are not formed becomes the n-type drift region 4.
A p-type source region 18 having a surface concentration of about 1 × 10 ¹⁸ cm ⁻³ and a diffusion depth of about 1 μm is formed on the surface layer of the n-type well region 17, and a high-concentration p is formed on the surface layer of the p-type offset region 16. A shaped drain region 6 is formed. A high-concentration n-type contact region 9 is formed on the surface layer of the n-type well region 17 in contact with the p-type source region 18 (which may not be in contact). A polysilicon gate electrode 13 is formed on the n-type substrate 3 and the n-type well region 17 sandwiched between the p-type offset region 16 and the p-type source region 18 via the thick gate oxide film 11, and the p-type is formed. A source electrode 14 is formed on the source region 18 and the n-type contact region 9, and a drain electrode 15 is formed on the drain region 6. Further, an insulating film is formed on the p-type offset region 16, and the gate electrode 13 extends thereon. The film thickness of the thick gate oxide film 11 (about 400 nm) is thicker than the film thickness (20 nm to 25 nm) of the gate oxide film of the MOSFET of the CMOS circuit and the lateral IGBT which are simultaneously formed. To do. In the n-type substrate 3, a portion where the n-type well region 17 and the p-type offset region 16 are not formed becomes an n-type drift region 4. In the figure, S is a source terminal, G is a gate terminal, and D is a drain terminal.

In the above-described configuration, the p-type source region end 21 on the surface of the n-type well region 17 sandwiched between the p-type source region 18 and the n-type drift region 4 and the n-type well region facing the p-type source region end 21. The distance L1 between the n-type well region 17 and the n-type well region end 22 on the surface of the n-type drift region 4 sandwiched between the n-type well region 17 and the p-type offset region 16 is p. The distance is set to be larger than the distance L2 from the shape offset region end 23. By doing so, the ON breakdown voltage when a high gate voltage is applied can be improved. The basis for this will be described next. L1 corresponds to the length of the p-type channel region formed in the surface layer of the n-type well region 17, and L2 represents the length of the p-type channel region formed in the surface layer of the n-type drift region 4. It corresponds to.
FIG. 2 is a diagram illustrating an example of the relationship between the ON breakdown voltage and L1 and L2. The on-breakdown voltage when the gate voltage is fixed to 170 V and the drain voltage is raised is shown. L1 + L2 = 10 μm. When L1 is as small as 5 μm or less, the potential distribution becomes non-uniform in the n-type well region 17 immediately below the gate electrode, and the electric field strength is increased, so that the on-breakdown voltage is as extremely low as 100V. When L1 exceeds 5 μm (L2 = 5 μm), the potential distribution becomes uniform in the n-type well region 17 immediately below the gate electrode, the electric field strength is relaxed, the ON breakdown voltage is rapidly increased, and L1 is 6 μm (L2 = 4 μm). ), The ON breakdown voltage reaches the gate voltage. When L1 exceeds 6 μm, the ON breakdown voltage becomes higher than the gate voltage. In the circuit of FIG. 3, the gate voltage becomes the power supply voltage, and the drain voltage changes from 0 V to the power supply voltage. Therefore, the on-breakdown voltage needs to be equal to or higher than the gate voltage. In order to satisfy this condition, L1 is made to exceed 5 μm. This is to make L1 larger than L2.

Up to this point, the gate voltage is set to 170 V and L1 + L2 is set to 10 μm. However, even if these values are changed, by setting L1> L2, the ON breakdown voltage is higher than the gate voltage (= output side power supply voltage). can do.
In the case where the gate voltage is 80 V, if L1 + L2 <2 μm, the electric field strength directly under the gate electrode is increased regardless of the condition of L1> L2, so that the OFF breakdown voltage and the ON breakdown voltage are extremely undesirably reduced. Further, when L1 + L2> 6 μm, the equipotential lines directly under the gate electrode become uniform regardless of the condition of L1> L2, and both the off breakdown voltage and the on breakdown voltage are secured.
In addition, when the gate voltage is 300 V, if L1 + L2 <5 μm, the electric field strength directly under the gate electrode is increased regardless of the condition of L1> L2, so that the off breakdown voltage and the on breakdown voltage are extremely undesirably reduced. Further, when L1 + L2> 20 μm, the equipotential lines directly under the gate electrode become uniform regardless of the condition of L1> L2, and both the off breakdown voltage and the on breakdown voltage are secured.

Therefore, when the gate voltage is in the range of 80 V to 300 V, the distance (L1 + L2) between the n-type well region and the p-type offset region where the condition of L1> L2 is remarkable is in the range of 2 μm ≦ L1 + L2 ≦ 20 μm.
Further, when the n-type well region 17 and the p-type offset region 16 are in contact with each other on the surface, the n-type drift region 4 is eliminated on the surface. (Of course, the ON breakdown voltage also decreases). Therefore, it is desirable that the n-type well region 17 and the p-type offset region 16 are separated from each other. Therefore, it is preferable that L2> 0 μm.
In order to make L1 larger than L2, it is only necessary to adjust the overlap length (Lm1) of the n-type well region 17 and the gate electrode 13 in the mask for forming the n-type well region 17, and a new process step There is no need to add.

  Further, by applying the HVPMOS of the present invention to the level shift circuit B of FIG. 3, the level shift circuit can be operated stably. As described above, the level shift circuit B is mounted with an inverter IC for driving a three-phase motor or a driver IC for driving a flat panel display together with an output circuit of a totem pole circuit or push-pull circuit composed of an IGBT or the like. Is done.

Sectional drawing of the principal part of the semiconductor device of one Example of this invention The figure which shows an example of the relationship between ON breakdown voltage and L1 and L2 The figure which shows an example of the level shift circuit to which thick film gate HVPMOS is applied Sectional view of the main part of a conventional semiconductor device when HVPMOS is formed on an SOI substrate

Explanation of symbols

1 n-type or p-type semiconductor substrate 2 oxide film 3 n-type substrate 4 n-type drift region 6 p-type drain region 9 n-type contact region 11 thick gate insulating film 12 insulating film 13 gate electrode 14 source electrode 15 drain electrode 16 p-type offset region 17 n-type well region 18 p-type source region 21 p-type source region end 22 n-type well region end 23 p-type offset region end 100 SOI substrate

Claims (3)

an n-type well region selectively formed in the surface layer of the n-type semiconductor layer; a p-type offset region selectively formed in the surface layer of the semiconductor layer apart from the well region; and the well A p-type source region selectively formed on the surface layer of the region, a p-type drain region selectively formed on the surface layer of the offset region, and a surface layer of the well region. An n-type contact region, a gate electrode formed on the semiconductor layer and the well region sandwiched between the source region and the offset region via a gate insulating film, the contact region, and the source region In a semiconductor device having a source electrode formed on and a drain electrode formed on the drain region,
A distance L1 between the source region end on the surface of the well region sandwiched between the source region and the semiconductor layer and the well region end facing the source region end is sandwiched between the well region and the offset region. Further, the semiconductor device is characterized in that it is longer than a distance L2 between the end of the well region on the surface of the semiconductor layer and the end of the offset region facing the well region. 2. The semiconductor device according to claim 1, wherein L <b> 1 + L <b> 2 is 2 μm or more and 20 μm or less. 2. The semiconductor device according to claim 1, wherein the semiconductor device is applied as a high-potential side switch element constituting a level shift circuit that drives a high-side switch of a totem pole circuit or a push-pull circuit.

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