JPS6064471A - High voltage insulated gate type field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent the permanent breakdown generating on the titled transistor by a method wherein the region, to be turned to the source region 13 opposing to the corner part of a drain region 12, is converted to an earth lead-out region 22, thereby enabling to stop the injection of electrons to a substrate from the above-mentioned part. CONSTITUTION:A high voltage insulated gate type FET is constituted in such a manner that the plane shape wherein the region to be turned to a source region 13 opposing to the corner part of a drain region 12 will be included is an earth lead-out region 22, and that the high withstand voltage drain region opposing to the corner part of the drain region 12 will be pushed out in the direction of the end part on the source region side of an offset gate region 14. As a result, the injection of carrier from the source region opposing to the corner part of the drain region is completely stopped, the source substrate junction is brought in the state where it is hardly forward-biased, and the current concentration in the high voltage drain region is relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high voltage insulated gate field effect transistor with high drain breakdown voltage.

In general, an insulated gate field effect transistor (hereinafter referred to as M
This will be explained using an OS transistor as a representative. ) is a majority carrier element, so it has excellent characteristics such as high-speed operation and no thermal runaway, and can be expected as a high-speed power device. However, the drain breakdown voltage of a normal MOS () transistor is only several tens of VL at most. In order to use it as a power device, it is necessary to improve the drain breakdown voltage, and various structures have been proposed for this purpose.

Among them, offset gate type MOS) transistors are
Since it is easy to integrate on the same chip as logic circuits that operate at low voltages, it is also promising as a high-voltage device for integrated circuits.

FIG. 1 shows a cross-sectional view of a conventional offset gate type MO8 transistor.

In the same figure, 1 indicates a low impurity concentration (for example, 6x1014
2 is a drain region made of a highly doped N-type region, 3 is a source region made of a heavily doped N-type region, 4 is an N-type offset gate region with a low impurity concentration; 5 is a channel region, 6 is a gate electrode made of low resistance polycrystalline silicon, 7 is a drain electrode made of aluminum, 8 is a source electrode, 9 is a gate silicon oxide film, and 10 is a field silicon oxide film.

In the MOS transistor shown in Figure 1, there is a parasitic bipolar transistor with the drain as the collector, the substrate as the base, and the source as the emitter, and when this parasitic bipolar transistor is turned on, it has the disadvantage of causing negative resistance or permanent damage. there were.

As a method to prevent turn-on of a parasitic bipolar transistor, a highly concentrated layer of the same conductivity type as the substrate is provided directly under the source so that the emitter junction (source-substrate junction) is not forward biased, and this layer is made to have the same potential as the source. A method for doing this has been proposed in Japanese Patent Application No. 130143/1983.

The structure of a high voltage MO8) transistor based on this principle is shown in FIG.

This high voltage MO8 transistor, as shown in the figure,
Immediately below the source region 13 is a buried ground region 21 made of a highly doped P-type region, and this buried ground region 21 . A ground lead-out region 22 made of a highly doped P-type region is provided in contact with the source region 13 and the surface of the semiconductor substrate 11, and the ground lead-out region 22 and the source region 13 are electrically connected to form a source electrode 18. . Furthermore, llI/'i,
A semiconductor substrate made of P-type silicon, 12 a drain region, 13 a source region, 14 an offset gate region, 1
5 is a channel region, 16 is a gate electrode, 17 is a drain electrode, 19 is a gate silicon oxide film, and 20 is a field silicon oxide film.

In a high voltage MOS transistor having this structure, if the planar shape of the drain is, for example, a circular shape with a radius of 100 μm or more, negative resistance and permanent breakdown, which are problems in practical use, will not occur at all within the operating range of use.

On the other hand, in order to apply it as a power device, it is necessary to increase the drain current, and therefore the gate width is designed to be large. As a structure for increasing the gate width, it is known to have a comb-shaped planar structure as shown in FIG. In the figure, 31 is a drain region, 32 is an offset gate region, 3:3 is a channel region, 34 is a source region,
35 is a ground drawer area. With such a structure, the channel width can be designed to be large.

The shape of the corner portion of the drain region of the comb tooth portion of the comb-shaped MOS transistor shown in FIG. 3 is rectangular, polygonal, or circular. If a rectangular or polygonal shape is used, strong electric field concentration will occur at the corners, and even if the drain region has a circular shape, if the radius of curvature R of the drain region becomes small, the corner region of the drain region will The electric field concentration becomes stronger. This electric field concentration occurs in the high voltage MOS shown in Figure 2.
It works to weaken the negative resistance of the transistor and its resistance to destruction. FIG. 4 shows an example of the relationship between the radius of curvature of the corner portion of the drain region and the breakdown current IBL determined experimentally. However, IBL here is a current value that causes negative resistance or permanent breakdown in drain current-drain voltage characteristics. As the radius of curvature becomes smaller, negative resistance and permanent destruction become more likely to occur.

FIG. 5 is a cross-sectional view showing an example of a conventional high-voltage MO8 transistor with increased drain breakdown voltage, which is another problem with high-voltage MO8 transistors.

The feature of this MOS transistor is that, in contrast to the conventional MOS transistor shown in FIG. This is because a high voltage drain region 23 consisting of a mold region is provided. This high-voltage drain region 23 is intended to improve drain breakdown voltage by preventing avalanche breakdown due to current concentration on the surface of the drain region, but this effect is still less effective at the corner portions of the drain region where current concentration is severe. It seems that it is not enough.

As explained above, in the conventional high voltage MO8) transistor, due to the corner part of the drain region,
There are disadvantages in that a negative resistance phenomenon occurs, resulting in permanent destruction and a decrease in drain withstand voltage.

An object of the present invention is to provide a field effect transistor (high voltage insulated gate) which does not cause negative resistance or permanent breakdown and has a high gate withstand voltage by eliminating the above-mentioned drawbacks.

The high voltage MO8 transistor of the first invention includes a source region and a drain region of opposite conductivity type provided on the entire surface of a semiconductor substrate of negative conductivity type, and an offset of opposite conductivity type provided in contact with the drain region. a gate region, a channel region formed between the offset gate region and the source region, a highly impurity-concentrated, monoconductive buried ground region provided in contact with the bottom surface of the source region; A high voltage comprising: a source region and a highly impurity-concentrated ground lead-out region of one conductivity type provided in contact with the entire surface of the semiconductor substrate; and a source electrode electrically connecting the ground lead-out region and the source region. The insulated gate field effect transistor has a planar shape in which a region to become the source region, which is opposite to a corner portion of the drain region, is included in the ground lead-out region.

The high voltage MO8) transistor of the second invention comprises a source region and a drain region of opposite conductivity type provided on the entire surface of a semiconductor substrate of negative conductivity type, and a source region and drain region of opposite conductivity type provided in contact with the drain region. an offset gate region, a channel region formed between the offset gate region and the source region, a highly impurity-concentrated, monoconductive buried ground region provided in contact with the bottom surface of the source region, and the buried ground region. A highly impurity-concentrated ground lead-out region of one conductivity type provided in contact with the source region and the entire surface of the semiconductor substrate, and a source electrode that electrically connects the ground lead-out region and the source region. In the voltage insulated gate field effect transistor, a high breakdown voltage drain region of a low impurity concentration and an opposite conductivity type is provided in contact with a portion of the offset gate region and the drain region, and the A region to become a source region is included in the ground lead-out region, and the high voltage drain/region facing the corner portion of the drain region is pushed out toward the end of the offset gate region on the source region side. Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 6 is a plan view of the surface of a semiconductor substrate showing essential parts of the first embodiment of the first invention.

The high voltage MO8 transistor of this embodiment is the high voltage MO8 transistor shown in FIG.
+ type source region 13 and drain region 12, N- type offset gate region 14 provided in contact with this drain region 12, and channel region 15 formed between this offset gate region 14 and source region 13. , a P+ type buried grounding region 21 provided in contact with the bottom surface of the source region 13;
As shown in FIG. It has a planar shape in which 122 regions corresponding to the portions indicated by a in the figure, which are to become source regions 13 facing the corner portions, are included in the ground lead-out region 22. In addition,
In the figure, 14 is an offset gate region, and 15 is a channel region.

In this embodiment, as shown in FIG. 6, the region to become the source region 13 facing the 122 corner portions of the drain region I2, indicated by a, where the electric field is concentrated and negative resistance is likely to occur, is grounded. By changing to the drawer area 22,
Electrons are no longer injected into the substrate from this portion, and no negative resistance occurs, so permanent destruction will not occur.

Also, since this part a is included in the ground lead-out region 22, the source-substrate junction in contact with it is less likely to be forward biased, so the operation of the ground region consisting of the ground lead-out region and the buried ground region is reduced. It is also effective in preventing negative resistance in the area and improving fracture resistance.

FIGS. 7 and 8 are plan views of the surface of a semiconductor substrate showing essential parts of second and third embodiments of the first invention, respectively.

In the second embodiment shown in FIG. 7, the first invention is applied when the corner part of the drain region 12' is circular, and the source region 13' opposite to the corner part of the drain region 12' The area indicated by a' in the same figure, which should be the same, is included in the ground lead-out area 22'. Note that 14' is an offset gate region, and 15' is a channel region.

In the third embodiment shown in FIG. 8, the first invention is applied when the corner part of the drain region 12' is polygonal, and the source region facing the corner part of the drain region 12' is The four areas indicated by a' in the same figure, which should be 13', are included in the ground pull-out area 22'.

Note that 14'' is an offset gate region, and 15' is a channel region.

As is clear from the above description, the basic configuration of the second and third embodiments is the same as that of the first embodiment, and it is a matter of course that the same effects can be obtained.

FIG. 9 is a plan view of the surface of a semiconductor substrate of an embodiment of the second invention, and FIG. 1θ is a cross-sectional view taken along the line AA'.

This embodiment is a high voltage M of the second embodiment of the first invention described above.
O8) Further, in the transistor, an N-type high breakdown voltage drain region 53 is provided in contact with a part of the offset gate region 44 and the drain region 42 for increasing the drain breakdown voltage,
The configuration is such that the region facing the corner portion of the drain/region 42 is buried toward the end of the offset gate region 44 on the source region 43 side (the portion indicated by b in FIG. 9). be done. The semiconductor substrate is made of 4itiP-type silicon, 45 is a channel region, 46 is a gate electrode, 47 is a drain electrode, 48 is a source electrode, 49 is a gate silicon oxide film, 50 is a field silicon oxide film, and 51 is a buried ground region. I'm here. Further, a''' refers to a region opposite to the corner portion of the drain region 42 that should originally become the source region 43 and is included in the ground lead-out region 52.

According to this embodiment, since the high voltage drain region 53 is widened at the corner portion of the drain region 42 where current concentration is severe, current concentration is alleviated and the drain breakdown voltage is improved, thereby preventing breakdown that causes negative resistance. The current (IBL) also increases.

Note that, although the above explanation has been made regarding the n-channel type MOS transistor, the same applies to the p-channel type MO8) transistor.

As explained in detail above, the high voltage insulated gate field effect transistor of the present invention has a planar shape in which a region to become a source region facing a corner portion of a drain region is included in a ground lead-out region, and a drain region. Since the high voltage drain region facing the corner part of the region has a planar shape that is pushed out toward the end of the offset gate region on the source region side, the source region facing the corner part of the drain region The generation of negative resistance and associated permanent damage are prevented by eliminating the injection of carriers from the source, by making the source-substrate junction less likely to be forward biased, and by alleviating current concentration in the high-voltage drain region. This has the effect of increasing drain breakdown voltage.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of a conventional insulated gate field effect transistor, FIG. 2 is a cross-sectional view showing an example of a conventional high voltage insulated gate field effect transistor, and FIG.
FIG. 4 is a plan view showing an example of the planar shape of the semiconductor substrate surface of the transistor shown in FIG. 4. FIG. FIG. 6 is a sectional view showing another example of a conventional high voltage insulated gate field effect transistor. 7 and 8 are the first and second sections of the first invention, respectively.
FIG. 9 is a plan view on the surface of a semiconductor substrate showing the main part of the third embodiment, FIG. 9 is a plan view on the surface of the semiconductor substrate showing the main part of the second embodiment of the present invention, and FIG. It is a diagram. 1... Semiconductor substrate, 2... Drain region, 3... Source region, 4... Offset gate region, 5... Channel region , 6...
...Ge H electrode, 7...Drain electrode, 8
...Source electrode, 9...Gate silicon & (tJ, I O...Field silicon M
chemical film, 11...semiconductor substrate, 12.12',
12"...Drain region, s 3 , 13'
, l 3' ----- Source region, 14.14'
, 14''...Offset gate region, 15.
15', 15'...channel region, 16...
...Gate electrode, 17...Drain electrode,
18...mark source electrode, 19...gate silicon oxide film, 20...field silicon oxide film,
21... Earth embedded area, 22... River/earth extraction area, 23... Drain area, 31...
... Drain region, 32 ... Offset gate region, 33 ... Channel region, 34 ...
... Source region, 35 ... Earth lead-out region, 41 ... Semiconductor substrate, 42 ... Drain region, 43 ... Source region, 44.・・・
...offset gate region, 45...channel region, 46...gate electrode, 47.river...drain electrode, 48...source electrode, 49.mountain...
・Gate silicon oxide film, 50... Field silicon oxide film, 51 ・Old... Earth buried region, 52
...Earth lead-out region, 53...High voltage drain region, a, a', a'', a'...
A region that is to become a source region facing the corner portion of the drain region, b: an extruded region of the high-voltage drain region. 0 70 20 Curvature gear diameter of train inclination J or corner part (/1) mm) Figure 6 (A) Figure 7 Lid Figure 8

Claims (2)

[Claims] (1) - A source region and a drain region of opposite conductivity type provided on the entire surface of a semiconductor substrate of conductivity type, an offset gate region of opposite conductivity type provided in contact with the drain region, and the offset gate region. a channel region formed between the source regions; a highly impurity-concentrated, monoconductive buried ground region provided in contact with the bottom surface of the source region; and a full surface of the buried ground region, the source region, and the semiconductor substrate. A high voltage insulated gate field effect transistor comprising: a highly impurity-concentrated ground lead-out region of one conductivity type provided in contact with the ground lead-out region; and a source electrode electrically connecting the ground lead-out region and the source region; A high voltage insulated gate field effect transistor, wherein a region to become the source region facing a corner portion of the drain region has a planar shape such that it is included in the ground lead-out region. (2) - a source region and a drain region of opposite conductivity type provided on the entire surface of a semiconductor substrate of conductivity type, and an offset gate region of opposite conductivity type provided in contact with the drain region;
a channel region formed between the offset gate region and the source region; a highly impurity-concentrated, monoconductive buried ground region provided in contact with the bottom surface of the source region; A high-voltage insulated gate type electric field comprising a highly impurity-concentrated ground lead-out region of one conductivity type provided in contact with the entire surface of a semiconductor substrate, and a source electrode that electrically connects the ground lead-out region and the source region. In the effect transistor, a high breakdown voltage drain region of an opposite conductivity type and low impurity is provided in contact with a part of the offset gate region and the drain region,
In addition, a region that is to become the source region facing the corner portion of the drain region is included in the ground lead-out region, and the high voltage drain/region facing the corner portion of the drain region is included in the source region of the offset gate region. A high-voltage insulated gate field effect transistor characterized in that it has a planar shape that is pushed out toward an end on a region side.