JPH08279556A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE: To form high-density upper and lower wiring layers by a method wherein a contact region on the lower wiring layers under the lower part of a through hole is formed into a rectangle and a contact region on the upper wiring layers on the upper part of the through hole is formed into a rectangle. CONSTITUTION: A contact region 10a on lower wiring layers 10 under the lower part of a through hole 14 is formed into a rectangle consisting of a lengthwise side of a size A1, which is longer than the line width A of the layers 10, and a lateral side of a size A2, which is longer than the lengthwise side. The intervals between the layers 10, which are arranged in the short side direction of the region 10a, can be set into the minimum size. A contact region 15a on upper wiring layers 15 on the upper part of the through hole 14 is formed into a rectangle consisting of a lengthwise side of a size B1, which is longer than the line width B of the layers 15, and a lateral side of a size B2, which is longer than the lengthwise side. The intervals between the layers 15, which are arranged in the short side direction of the region 15a, can be set into the minimum size. Thereby, the high-density upper and lower wiring layers 15 and 10 can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having a high-density wiring layer.

[0002]

2. Description of the Related Art In semiconductor integrated circuit devices, high integration and fine processing have been promoted, and accordingly, the wiring structure has become fine, and a high density wiring structure has been required.

In recent years, a multilayer wiring structure has been adopted as a wiring layer of a semiconductor integrated circuit device, and a lower wiring layer and an upper wiring layer are electrically connected to each other through through holes in selective regions of an interlayer insulating film. There is something.

The wiring layers in the semiconductor integrated circuit device examined by the present inventor are as follows.

That is, as shown in FIG. 12, a lower wiring layer 17 is arranged at a constant interval on an insulating film on a semiconductor substrate on which a semiconductor element is formed, and an interlayer insulating film 18 is formed on the lower wiring layer 17. The upper wiring layer 20 is electrically connected to the upper wiring layer 20 through the through hole 19.
Are arranged at regular intervals.

As shown in FIG. 13, the lower wiring layer 17 in the lower portion of the through hole 19 has a square contact region 17 having a dimension A ₁ larger than the line width A of the lower wiring layer 17.
It is a. The upper wiring layer 20 above the through holes 19 is a square contact region 20a having a dimension B ₁ larger than the line width B of the upper wiring layer 20.

As a document describing a technique for forming a wiring layer in a semiconductor integrated circuit device, for example, press journal "'90 latest semiconductor process technology" p67-p273, issued on November 2, 1989, is published.
Are listed in.

[0008]

However, the present inventor has found that the semiconductor integrated circuit device having the above-mentioned multilayer wiring layer has various problems as described below.

That is, since the manufacturing process for forming the through hole 19 in the interlayer insulating film 18 is performed by using the photolithography technique, when the pattern of the through hole 19 is formed in the photoresist film in the photolithography technique. The lower wiring layer 17 under the through hole 19 needs to be a square contact region 17a having a size larger than the line width of the lower wiring layer 17 in consideration of the misalignment of each of the lower wiring layers 17. Since the space needs to be widened in consideration of the size of the contact region 17a, a large area occurs when the lower wiring layer 17 is arranged, which causes a problem that the high-density lower wiring layer 17 cannot be formed. .

Further, since the manufacturing process of forming the upper wiring layer 20 electrically connected to the lower wiring layer 17 through the through hole 19 is performed by using the photolithography technique, the photoresist film in the photolithography technique is formed. In consideration of misalignment when forming the pattern of the upper wiring layer 20, the upper wiring layer 20 above the through hole 19 needs to be a square contact region 20a having a size larger than the line width of the upper wiring layer 20. Therefore, the space between each upper wiring layer 20 is
Since it is necessary to widen the size of a in consideration of the size of a, there is a problem that when the upper wiring layer 20 is arranged, the area becomes large and the high-density upper wiring layer 20 cannot be formed.

Further, the manufacturing process for forming the pattern of the lower wiring layer 17 is performed by using a photomask formed by an automatic wiring system using a CAD system for supporting the wiring design of the semiconductor integrated circuit device. Accordingly, the contact region 17a in each lower wiring layer 17
Since the contact area 17a having the maximum size is set to the contact area 17a of each lower wiring layer 17 and the shape of the contact area 17a is set to a square shape having the same vertical and horizontal dimensions, Since the spacing between the lower wiring layers 17a becomes wider than necessary, the lower wiring layer 1
7 has a large area when arranging, and the high-density lower wiring layer 1
There is a problem that 7 cannot be formed.

This kind of problem also occurs in the manufacturing process for forming the patterns of the through holes 19 and the upper wiring layer 20, and it is possible to form a high-density wiring layer of a semiconductor integrated circuit device having a multilayer wiring layer. There is a problem that you cannot do it.

An object of the present invention is to provide a semiconductor integrated circuit device having a high density wiring layer.

Another object of the present invention is to provide a manufacturing technique capable of easily manufacturing a semiconductor integrated circuit device having a high-density wiring layer.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0016]

The typical ones of the inventions disclosed in the present invention will be outlined below.

(1) In the semiconductor integrated circuit device of the present invention, the lower wiring layer on the substrate on which a plurality of semiconductor elements are provided and the through hole formed in the interlayer insulating film in the lower wiring layer are provided. In a semiconductor integrated circuit device having a wiring layer in which an upper wiring layer is electrically connected, a contact area of a lower wiring layer under a through hole is rectangular, and a contact area of the upper wiring layer above a through hole is rectangular. Shall be

(2) In the method of manufacturing a semiconductor integrated circuit device of the present invention, a step of forming a lower wiring layer on the surface of a substrate on which a plurality of semiconductor elements are formed, and a through hole described later by using a photolithography technique. Through a step of forming a pattern of a lower wiring layer having a rectangular contact area in a region where the upper wiring layer is electrically connected through, a step of forming an interlayer insulating film on a substrate including the lower wiring layer, and a photolithography technique. A step of forming a through hole on the contact region in the lower wiring layer using, a step of forming the upper wiring layer on the base body including the interlayer insulating film, and a rectangular shape in the region including the through hole using photolithography technology. And a step of forming a pattern of an upper wiring layer having a contact region.

[0019]

[Action]

(1) According to the semiconductor integrated circuit device of the present invention described above,
The contact area of the lower wiring layer in the lower portion of the through hole is rectangular, and the contact area of the upper wiring layer in the upper portion of the through hole is rectangular, so that the arrangement of each lower wiring layer in the lower wiring layer can be made in each lower wiring layer. The contact regions can be arranged adjacent to each other in the short side direction of the rectangle, and the upper wiring layers can be arranged in the upper wiring layer adjacent to each other in the short side direction of the rectangle of the contact region. Therefore, the distance between the lower wiring layers and the distance between the upper wiring layers can be minimized.

Therefore, a large number of lower wiring layers can be arranged in a small area and a large number of upper wiring layers can be arranged in a small area, so that a high density wiring layer can be obtained. A semiconductor integrated circuit device having a high-density wiring layer can be provided.

(2) According to the method of manufacturing a semiconductor integrated circuit device of the present invention described above, after the lower wiring layer is formed, the upper wiring layer is electrically connected to a region through a through hole which will be described later using a photolithography technique. A step of forming a pattern of a lower wiring layer having a rectangular contact region, and an interlayer insulating film is formed on a substrate including the lower wiring layer, and then a through hole is formed on the contact region in the lower wiring layer by using a photolithography technique. A step of forming
A step of forming an upper wiring layer on a base body including an interlayer insulating film and then forming a pattern of the upper wiring layer having a rectangular contact region in a region including a through hole by using a photolithography technique. By this, the arrangement of each lower wiring layer in the lower wiring layer can be formed adjacent to each other in the short side direction of the rectangle of the contact region in each lower wiring layer, and the arrangement of each upper wiring layer in the upper wiring layer can be arranged in each upper wiring. Since they can be formed adjacent to each other in the short side direction of the rectangle of the contact region in the layer, the distance between the lower wiring layers and the distance between the upper wiring layers can be formed with minimum dimensions.

The step of forming the pattern of the lower wiring layer, the through hole and the pattern of the upper wiring layer can be performed by a photolithography technique using a photomask using an automatic wiring system, so that a simple manufacturing process is possible. Thus, a semiconductor integrated circuit device having a high-density wiring layer can be manufactured.

[0023]

Embodiments of the present invention will now be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and a duplicate description will be omitted.

1 to 9 are sectional views showing a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention. The semiconductor integrated circuit device and the manufacturing method thereof according to the present invention will be specifically described with reference to FIG.

First, as shown in FIG. 1, a field formed of a silicon oxide film is applied to an element isolation region, which is a selective region on the surface of a semiconductor substrate 1 made of, for example, p-type silicon single crystal, by using a thermal oxidation process. The insulating film 2 is formed. Although not shown, a channel stopper layer for preventing inversion is formed under the field insulating film 2.

Next, as shown in FIG. 2, a gate insulating film 3 made of silicon oxide is formed in the active region surrounded by the field insulating film 2, and a gate electrode made of polycrystalline silicon is formed on the gate insulating film 3. 4 is formed. The gate electrode 4 is formed by sequentially depositing an insulating film 5 made of a polycrystalline silicon film and a silicon oxide film on the semiconductor substrate 1 and sequentially etching these. After that, the sidewall insulating film 6 made of silicon oxide is formed on the sidewall of the gate electrode 4.

Next, an n-type impurity such as phosphorus (P) is ion-implanted into the semiconductor substrate 1 to form an n-type semiconductor region 7 serving as a source and a drain.

Next, as shown in FIG. 3, an insulating film 8 is formed on the semiconductor substrate 1. As the insulating film 8, a silicon oxide film or the like formed by the CVD method can be used.

In the manufacturing process of the semiconductor integrated circuit device described above, the p-channel MOSFET is formed on the semiconductor substrate 1, but the p-channel MOSFET is formed on the semiconductor substrate 1.
It is possible to adopt a mode in which various semiconductor elements such as n-channel MOSFETs, bipolar transistors, and capacitive elements other than the above are formed.

The above-described manufacturing process of the semiconductor integrated circuit device can be performed by combining various prior arts. The main part of the semiconductor integrated circuit device and the manufacturing method thereof according to the present invention is the wiring layer of the semiconductor integrated circuit device and the manufacturing method thereof. Based on this, in order to simplify the description hereafter, the semiconductor substrate 1 formed by the above-described manufacturing process is used as the starting material for the p-channel M.
A substrate 9 on which an OSFET is formed is comprehensively illustrated, the internal structure of the substrate 9 having an internal structure is omitted, and the dimensions shown in the drawing are reduced.

Next, as shown in FIG. 4, the lower wiring layer 10 is formed on the surface of the substrate 9. As the lower wiring layer 10, for example, an aluminum layer is formed by CVD (Chemical Vapor Deposition).
It is formed by the method. As a material of the lower wiring layer 10, in order to secure the characteristics of stress migration resistance and electromigration resistance, a high-grade material such as a titanium nitride (TiN) layer as a lower layer or an upper layer of the aluminum layer as the lower wiring layer 10 is secured. A wiring layer in which a wiring structure is laminated using a melting point metal layer can be used. As the lower wiring layer 10, a combination of electrically conductive materials such as a polycrystalline silicon layer or a laminated layer of a polycrystalline silicon layer and a high melting point silicide layer can be used.

The lower wiring layer 10 includes a wiring layer electrically connected through a through hole provided in the insulating film 8 in a region (not shown), and is electrically connected to the n-type semiconductor region 7. It also includes the wiring layers to be connected.

Next, a photoresist film 11 is formed on the surface of the lower wiring layer 10.

Next, as shown in FIG. 5, a pattern for the lower wiring layer is formed on the photoresist film 11 by using a photomask for the lower wiring layer using the photolithography technique.

Next, using the photoresist film 11 as an etching mask, the lower wiring layer 10 is selectively etched by a dry etching method or a wet etching method to pattern the lower wiring layer 10.

In this case, as shown in FIGS. 10 and 11, a contact region 10a is formed in a region where an upper wiring layer, which will be described later, is electrically connected to a selective region of the lower wiring layer 10 through a through hole in the interlayer insulating film. To form.

10 is a schematic plan view showing the manufacturing process of the semiconductor integrated circuit device of this embodiment, and FIG. 11 is shown in FIG.
FIG. 3 is a schematic plan view showing an enlarged upper left contact region 10a at 0.

Contact region 1 in lower wiring layer 10
0a has a rectangular shape with long sides in the wiring direction of the lower wiring layer 10.

The rectangular contact region 10a is a rectangle composed of a vertical side having a dimension A ₁ larger than the line width A of the lower wiring layer 10 and a horizontal side having a dimension A ₂ larger than the vertical side. Adjacent lower wiring layers 10 are arranged at predetermined intervals in the vertical direction of 10a.

That is, the contact region 10a has a rectangular shape in which the wiring direction of the lower wiring layer 10 is lengthened and the direction orthogonal to the wiring direction is shortened. The wiring directions of the lower wiring layers 10 of the lower wiring layer 10 are the same. In this case, the lateral dimension A ₂ of the rectangular contact region 10a is in the wiring direction and has no effect on the dimension of the interval between the adjacent lower wiring layers 10, so it can be increased as necessary. .

The contact region 10a has a rectangular shape, and by arranging the lower wiring layers 10 in the direction of the shorter side thereof, the distance between the lower wiring layers 10 can be set to the minimum dimension, so that the lower layers can be formed. Since many wiring layers 10 can be arranged in a small area, a high-density lower wiring layer 10 can be formed.

Further, the photomask for the lower wiring layer used in the above-mentioned photolithography technique uses the data corresponding to the pattern of the lower wiring layer 10 having the rectangular contact region 10a described above for the wiring of the semiconductor integrated circuit device. Since the pattern is formed by the automatic wiring system using the CAD system that supports the design, the pattern of the high density lower wiring layer 10 can be formed by a simple manufacturing process.

Although the contact region 10a in the lower wiring layer 10 shown in FIG. 10 has the same rectangular shape in each lower wiring layer 10, the contact region 10a in each lower wiring layer 10 has a rectangular shape depending on the arrangement of each lower wiring layer 10. The dimension of the vertical side and the dimension of the horizontal side of the contact region 10a can be set to values corresponding to the respective lower wiring layers 10.

Next, the photoresist film 11 that has become unnecessary
Work to remove.

Next, as shown in FIG. 6, the lower wiring layer 10
An interlayer insulating film 12 is formed on the entire surface so as to cover the.
The inter-layer insulating film 12 is formed by, for example, forming a silicon oxide film by a CVD method, and then performing SOG (Sp
An in on glass) film is formed using a spin coater (spinner). The interlayer insulating film 12 is formed of, for example, a silicon oxide film by a CVD method, and then PSG (Phospho Silicon
cate glass) film or BPSG (Boro Phospho Silicat)
Various embodiments such as an interlayer insulating film having a laminated structure in which an e-Glass film or the like is formed by a CVD method can be adopted.

Next, a photoresist film 13 is formed on the surface of the interlayer insulating film 12.

Next, as shown in FIG. 7, a pattern for through holes is formed in the photoresist film 13 by using a photo mask for through holes using a photolithography technique.

Next, using the photoresist film 13 as an etching mask, the interlayer insulating film 12 is selectively etched by a dry etching method or a wet etching method to pass through a selective region of the interlayer insulating film 12. The hole 14 is formed.

In this case, as shown in FIG. 10, the through hole 14 is formed in the contact region 1 in the lower wiring layer 10.
It is formed at the center of 0a.

The photomask for through holes used in the above-mentioned photolithography technique is an automatic wiring using a CAD system that supports the wiring design of the semiconductor integrated circuit device by using the data corresponding to the pattern of the through holes 14. Since it is formed by the system, a photomask in which the through holes 14 are arranged at accurate positions can be formed, so that a high-density wiring layer pattern can be formed by a simple manufacturing process.

Next, the photoresist film 13 that is no longer needed
Work to remove.

Next, as shown in FIG.
The upper wiring layer 15 is formed on the interlayer insulating film 12 and the interlayer insulating film 12. As the upper wiring layer 15, for example, an aluminum layer is formed by CVD.
It is formed by the method. The upper wiring layer 15 may have various modes such as a wiring layer having a laminated structure made of the same material as that of the lower wiring layer 10 described above.

Next, a photoresist film 16 is formed on the surface of the upper wiring layer 10.

Next, as shown in FIG. 9, a pattern for the upper wiring layer is formed on the photoresist film 16 by using a photomask for the upper wiring layer using the photolithography technique.

Next, using the photoresist film 16 as an etching mask, the upper wiring layer 15 is selectively etched by a dry etching method or a wet etching method to pattern the upper wiring layer 15.

In this case, as shown in FIG. 10, a contact region 15a is formed above the through hole 14 in the upper wiring layer 15.

Contact region 1 in the upper wiring layer 15
5a has a rectangular shape having long sides in the wiring direction of the upper wiring layer 15.

The rectangular contact region 15a is a rectangle composed of a vertical side having a dimension B ₁ larger than the line width B of the upper wiring layer 15 and a horizontal side having a dimension B ₂ larger than the vertical side. Adjacent upper wiring layers 15 are arranged at predetermined intervals in the vertical direction of 15a.

That is, the contact region 15a has a rectangular shape in which the wiring direction of the upper wiring layer 15 is lengthened and the direction orthogonal to the wiring direction is shortened. The wiring directions of the upper wiring layers 15 of the upper wiring layer 15 are the same. In this case, the lateral dimension B ₂ of the rectangular contact region 15a is in the wiring direction and has no effect on the dimension of the interval between the adjacent upper wiring layers 15, so that it can be increased as necessary. .

The contact region 15a has a rectangular shape, and the upper wiring layers 15 are arranged in the direction of the shorter side of the contact region 15a, so that the distance between the upper wiring layers 15 can be set to the minimum dimension. Since many wiring layers 15 can be arranged in a small area, a high-density upper wiring layer 15 can be formed.

In addition, the photomask for the upper wiring layer used in the above-mentioned photolithography technique uses the data corresponding to the pattern of the upper wiring layer 15 having the rectangular contact region 15a described above for the wiring of the semiconductor integrated circuit device. Since the pattern is formed by the automatic wiring system using the CAD system that supports the design, the pattern of the high-density upper wiring layer 15 can be formed by a simple manufacturing process.

Although the contact region 15a in the upper wiring layer 15 shown in FIG. 10 has the same rectangular shape in each upper wiring layer 15, the contact region 15a in each upper wiring layer 15 has a rectangular shape depending on the arrangement of each upper wiring layer 15. The vertical side dimension and the horizontal side dimension of the contact region 15a can be set to values corresponding to the respective upper wiring layers 15.

Next, the photoresist film 16 that has become unnecessary
Work to remove.

Next, if necessary, after forming wiring layers of a multilayer wiring structure and an interlayer insulating film between them on the upper wiring layer 15, a surface protective film (not shown) such as a nitric oxide film is formed. By forming, the manufacturing process of the semiconductor integrated circuit device is completed.

According to the semiconductor integrated circuit device of this embodiment,
Since the contact region 10a of the lower wiring layer 10 below the through hole 14 is rectangular and the contact region 15a of the upper wiring layer 15 above the through hole 14 is rectangular, each lower wiring layer 10 in the lower wiring layer 10 is formed. Can be arranged adjacent to each other in the short side direction of the rectangle of the contact region 10a in each lower wiring layer 10.

Since the upper wiring layers 15 in the upper wiring layer 15 can be arranged adjacent to each other in the short side direction of the rectangle of the contact region 15a in the upper wiring layers 15, the distance between the lower wiring layers 10 can be increased. Also, the distance between the upper wiring layers 15 can be set to the minimum dimension.

Therefore, since it is possible to arrange many lower wiring layers 10 in a small area region and many upper wiring layers 15 in a small area region,
Since a high-density wiring layer can be formed, a semiconductor integrated circuit device including a high-density wiring layer can be obtained.

Further, according to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, after forming the lower wiring layer 10, the rectangular shape is formed in the region where the upper wiring layer 15 is electrically connected through the through hole 14 by using the photolithography technique. Forming a pattern of the lower wiring layer 10 having the contact region 10a, and forming the interlayer insulating film 12 on the substrate 9 including the lower wiring layer 10 and then using the photolithography technique to form the contact region in the lower wiring layer 10. 10a, a step of forming a through hole 14 and, after forming an upper wiring layer 15 on the base body 9 including the interlayer insulating film 12, a rectangular contact region 15a is formed in the region including the through hole 14 using a photolithography technique. And the step of forming a pattern of the upper wiring layer 15 having The arrangement of each lower wiring layer 10 in each lower wiring layer 10 can be formed adjacent to each other in the short side direction of the rectangle of the contact region 10a in each lower wiring layer 10, and the arrangement of each upper wiring layer 15 in each upper wiring layer 15 can be arranged in each upper wiring layer. Since the contact regions 15a in the layer 15 can be formed so as to be adjacent to each other in the direction of the shorter side of the rectangle, the distance between the lower wiring layers 10 and the distance between the upper wiring layers 15 can be minimized.

The step of forming the pattern of the lower wiring layer 10, the through hole 14 and the pattern of the upper wiring layer 15 can be carried out by a photolithography technique using a photomask using an automatic wiring system. A semiconductor integrated circuit device having a high-density wiring layer can be manufactured by various manufacturing processes.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-described embodiment, the MOSF
The semiconductor integrated circuit device has the ET provided on the semiconductor substrate and the manufacturing method thereof. However, a BiMOS or BiCM in which a bipolar transistor is provided on the semiconductor substrate or a MOSFET and a bipolar transistor are combined.
It can be applied to a semiconductor integrated circuit device having various semiconductor elements such as an OS structure and a manufacturing technique thereof.

[0072]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the semiconductor integrated circuit device of the present invention, the contact region of the lower wiring layer below the through hole is rectangular, and the contact region of the upper wiring layer above the through hole is rectangular. ,
The arrangement of each lower wiring layer in the lower wiring layer can be performed adjacent to each other in the short side direction of the rectangle of the contact area in each lower wiring layer, and the arrangement of each upper wiring layer in the upper wiring layer can be performed in each upper wiring layer. Since the contact regions can be arranged adjacent to each other in the short side direction of the rectangle, the distance between the lower wiring layers and the distance between the upper wiring layers can be minimized.

Therefore, a large number of lower wiring layers can be arranged in a small area and a large number of upper wiring layers can be arranged in a small area, so that a high density wiring layer can be obtained. A semiconductor integrated circuit device having a high-density wiring layer can be provided.

(2) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a rectangular wiring is formed in a region where the upper wiring layer is electrically connected through a through hole described later by using a photolithography technique after forming the lower wiring layer. A step of forming a pattern of a lower wiring layer having a contact region, and an interlayer insulating film is formed on a substrate including the lower wiring layer, and then a through hole is formed on the contact region in the lower wiring layer by using a photolithography technique. And a step of forming an upper wiring layer on a substrate including an interlayer insulating film and then forming a pattern of an upper wiring layer having a rectangular contact region in a region including a through hole by using a photolithography technique. By arranging the layout of each lower wiring layer in the lower wiring layer, Can be formed adjacent to each other in the short side direction, and the arrangement of each upper wiring layer in the upper wiring layer can be formed adjacent to each other in the short side direction of the rectangle of the contact region in each upper wiring layer. The space between the lower wiring layers and the space between the respective upper wiring layers can be formed with minimum dimensions.

Further, the steps of forming the pattern of the lower wiring layer, the through holes and the pattern of the upper wiring layer can be performed by the photolithography technique using the photomask using the automatic wiring system, so that a simple manufacturing process is possible. Thus, a semiconductor integrated circuit device having a high-density wiring layer can be manufactured.

(3) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, when the contact region in the lower wiring layer is formed by using the photolithography technique, the contact region extends the wiring direction of the lower wiring layer. , The rectangular shape in which the direction orthogonal to the wiring direction is shortened is adopted, and the wiring direction of each lower wiring layer of the lower wiring layer is formed to be the same, so that the dimension of the long side in the rectangular contact area Is in the wiring direction and has no influence on the size of the interval between adjacent lower wiring layers, so that it can be set to a large size as necessary.

Further, the contact region in the lower wiring layer is rectangular and the lower wiring layers are arranged in the direction of the shorter side thereof, so that the distance between the lower wiring layers can be set to the minimum dimension. As a result, a large number of lower wiring layers can be arranged in a region having a small area, so that a high-density lower wiring layer can be formed.

For the same reason as in the manufacturing process of the lower layer wiring described above, many upper layer wiring layers can be arranged in a small area, so that a high-density upper layer wiring layer can be formed.

Therefore, by forming the high-density lower wiring layer and the high-density upper wiring layer, a semiconductor integrated circuit device having a high-density wiring layer can be manufactured.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 10 is a schematic plan view showing the manufacturing process of the semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 11 is a schematic enlarged plan view showing the manufacturing process of the semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 12 is a schematic plan view showing a wiring layer of a semiconductor integrated circuit device examined by the present inventor.

FIG. 13 is a schematic enlarged plan view showing a wiring layer of a semiconductor integrated circuit device examined by the present inventor.

[Explanation of symbols]

 1 semiconductor substrate 2 field insulating film 3 gate insulating film 4 gate electrode 5 insulating film 6 sidewall insulating film 7 n-type semiconductor region 8 insulating film 9 substrate 10 lower wiring layer 10a contact region 11 photoresist film 12 interlayer insulating film 13 photoresist Film 14 Through Hole 15 Upper Wiring Layer 15a Contact Area 16 Photoresist Film 17 Lower Wiring Layer 17a Contact Area 18 Interlayer Insulating Film 19 Through Hole 20 Upper Wiring Layer 20a Contact Area

Claims (8)

[Claims] 1. A lower wiring layer on a substrate on which a plurality of semiconductor elements are provided and an upper wiring layer are electrically connected to the lower wiring layer through a through hole formed in an interlayer insulating film. A semiconductor integrated circuit device having a wiring layer, wherein a contact region of the lower wiring layer below the through hole is rectangular, and a contact region of the upper wiring layer above the through hole is rectangular. Semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the rectangular contact regions of the lower wiring layers in the lower wiring layer have the same size or different sizes corresponding to the lower wiring layers. A semiconductor integrated circuit device, wherein the rectangular contact regions of the upper wiring layers in the upper wiring layer have the same size or different sizes corresponding to the respective upper wiring layers. 3. The semiconductor integrated circuit device according to claim 1, wherein the contact region of the lower wiring layer has a vertical side having a dimension larger than a line width of the lower wiring layer and a dimension larger than the vertical side. The contact region of the upper wiring layer is a rectangle formed by horizontal sides, and the contact region of the upper wiring layer is a rectangle formed by vertical sides having dimensions larger than the line width of the upper wiring layer and horizontal sides having dimensions larger than the vertical sides. Integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the arrangement of the lower wiring layers in the lower wiring layer is adjacent to each other in the short side direction of the rectangle of the contact region in each of the lower wiring layers. The semiconductor integrated circuit device is characterized in that the upper wiring layers in the upper wiring layer are arranged adjacent to each other in the direction of the shorter side of the rectangle of the contact region in each of the upper wiring layers. 5. A step of forming a lower wiring layer on a surface of a substrate on which a plurality of semiconductor elements are formed, and a step of forming a photoresist film as an etching mask on a part of the surface of the lower wiring layer, By etching a region where the surface of the lower wiring layer is exposed using the photoresist film as an etching mask, the lower layer having a rectangular contact region in a region where the upper wiring layer is electrically connected through a through hole described later. Forming a wiring layer pattern; forming an interlayer insulating film on the substrate including the lower wiring layer; and forming a photoresist film serving as an etching mask on a part of the surface of the interlayer insulating film. After that, by etching the region where the surface of the interlayer insulating film is exposed using the photoresist film as an etching mask, A step of forming a through hole on the contact region in the lower wiring layer, a step of forming an upper wiring layer on the substrate including the interlayer insulating film, and an etching mask on a part of the surface of the upper wiring layer. After forming a photoresist film to be the above, by etching the region where the surface of the upper wiring layer is exposed using the photoresist film as an etching mask, a rectangular contact region is formed in the region including the through hole. A step of forming a pattern of the upper wiring layer, the method for manufacturing a semiconductor integrated circuit device. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the contact region of the lower wiring layer has a vertical side having a dimension larger than a line width of the lower wiring layer and a dimension larger than the vertical side. And the contact region of the upper wiring layer is formed as a rectangle composed of a vertical side having a size larger than the line width of the upper wiring layer and a horizontal side having a size larger than the vertical side. A method for manufacturing a semiconductor integrated circuit device, comprising: 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the lower wiring layers in the lower wiring layer are arranged adjacent to each other in the short side direction of the rectangle of the contact region in each lower wiring layer. And the upper wiring layers in the upper wiring layer are arranged so as to be adjacent to each other in the short side direction of the rectangle of the contact region in each of the upper wiring layers. Production method. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 5, 6 or 7, wherein the step of forming the pattern of the lower wiring layer, the through hole and the pattern of the upper wiring layer is performed by an automatic wiring system. A method for manufacturing a semiconductor integrated circuit device, which is performed by a photolithography technique using the photomask used.