JPH08274213A - Chip carrier and its mounting member - Google Patents
Chip carrier and its mounting memberInfo
- Publication number
- JPH08274213A JPH08274213A JP7073374A JP7337495A JPH08274213A JP H08274213 A JPH08274213 A JP H08274213A JP 7073374 A JP7073374 A JP 7073374A JP 7337495 A JP7337495 A JP 7337495A JP H08274213 A JPH08274213 A JP H08274213A
- Authority
- JP
- Japan
- Prior art keywords
- chip carrier
- electrode
- wiring board
- external connection
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は外部接続用端子をキャリ
ア裏面にグリッド状に有する半導体装置用チップキャリ
ア及びＭＣＭ（マルチ・チップ・モジュール）用基板と
その実装に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device chip carrier having external connection terminals on the back surface of the carrier in a grid pattern, an MCM (multi-chip module) substrate and its mounting.
【０００２】[0002]
【従来の技術】半導体装置の中にＢＧＡ（ボール・グリ
ッド・アレイ）パッケージやＬＧＡ（ランド・グリッド
・アレイ）パッケージというものがある。これらは、半
導体を実装したチップキャリアの外部接続電極がチップ
キャリアの裏面にグリッド状に配置された半導体装置で
ある。この半導体装置は、従来のＱＦＰに比べると外部
接続電極がパッケージの裏面にあるので半導体装置のサ
イズが大幅に小型化されるという利点がある。また外部
接続電極のピッチもＱＦＰの０.３ｍｍや０.５ｍｍに比
べ１.５ｍｍや１.２７ｍｍといったあらいものであり、
容易な実装が可能である。そのためＢＧＡパッケージや
ＬＧＡパッケージは、新たな半導体装置として脚光を浴
びている。ＢＧＡは外部接続電極としてチップキャリア
裏面に格子状に並んだ半田ボールを有しており、この半
田ボールにて回路配線基板との接続をとる。また、ＬＧ
Ａは半田ペーストあるいは、ソケットによって回路配線
基板との接続を行なう。2. Description of the Related Art Among semiconductor devices, there are BGA (ball grid array) package and LGA (land grid array) package. These are semiconductor devices in which external connection electrodes of a chip carrier on which a semiconductor is mounted are arranged in a grid pattern on the back surface of the chip carrier. This semiconductor device has an advantage that the size of the semiconductor device is significantly reduced because the external connection electrode is on the back surface of the package as compared with the conventional QFP. Also, the pitch of the external connection electrodes is as large as 1.5 mm or 1.27 mm compared to 0.3 mm or 0.5 mm of QFP,
Easy implementation is possible. Therefore, BGA packages and LGA packages are in the spotlight as new semiconductor devices. The BGA has solder balls arranged in a grid pattern on the back surface of the chip carrier as external connection electrodes, and the solder balls are used to connect to the circuit wiring board. Also, LG
A is connected to the circuit wiring board by a solder paste or a socket.
【０００３】図４に従来のセラミック基板をチップキャ
リアとしたＢＧＡパッケージをプリント配線基板に半田
にて実装した後の断面図を示す。１はチップキャリア、
２は半田、３は半導体素子、４は絶縁性基板、５はプリ
ント配線基板、３１は電極パッド、３２は半田、４ａは
表面、４ｂは裏面、４１は接続配線、４２は外部電極、
４３はビアホール、５１はプリント配線基板側電極であ
る。FIG. 4 shows a cross-sectional view after mounting a BGA package using a conventional ceramic substrate as a chip carrier on a printed wiring board by soldering. 1 is a chip carrier,
2 is solder, 3 is a semiconductor element, 4 is an insulating substrate, 5 is a printed wiring board, 31 is an electrode pad, 32 is solder, 4a is the front surface, 4b is the back surface, 41 is connection wiring, 42 is an external electrode,
43 is a via hole, and 51 is a printed wiring board side electrode.
【０００４】ＢＧＡは、半田ボールにて実装しているの
でチップキャリアと回路配線基板との実装間隔が広く、
半田実装においてはＬＧＡよりも実装信頼性は高い。そ
のためグリッド状に外部接続電極を有する半導体装置に
おいては、ＢＧＡが主流となっている。しかし、コンピ
ュータのＣＰＵのようにグレードアップが必要な半導体
装置においては、ＬＧＡとソケットという組み合わせの
形態のものも多く使用されている。Since the BGA is mounted with solder balls, the mounting interval between the chip carrier and the circuit wiring board is wide,
Mounting reliability is higher in solder mounting than in LGA. Therefore, BGA is predominant in semiconductor devices having external connection electrodes in a grid pattern. However, in a semiconductor device that needs to be upgraded, such as a CPU of a computer, a combination of an LGA and a socket is often used.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、以下に
示すような問題が明らかとなった。外部接続電極をグリ
ッド状に有するＢＧＡやＬＧＡの半導体装置の場合、半
田により半導体装置と回路配線基板が接続されているた
め、熱衝撃試験というような環境信頼性試験をおこなう
と、チップキャリアと回路配線基板との熱膨張係数の違
いによって外部接続電極部にクラックが入り、信頼性で
の不良が起こってしまう。特に、セラミック基板をチッ
プキャリアとする半導体装置においては、セラミック基
板の強度が弱いためセラミック基板へクラックが入り、
外部接続電極の剥がれが起こってしまう。However, the following problems have become clear. In the case of a BGA or LGA semiconductor device having a grid of external connection electrodes, since the semiconductor device and the circuit wiring board are connected by soldering, when an environmental reliability test such as a thermal shock test is performed, the chip carrier and the circuit are Due to the difference in the coefficient of thermal expansion from the wiring board, the external connection electrode portion is cracked, and reliability defects occur. In particular, in a semiconductor device using a ceramic substrate as a chip carrier, the strength of the ceramic substrate is weak, so the ceramic substrate is cracked,
Peeling of the external connection electrode occurs.
【０００６】[0006]
【課題を解決するための手段】本発明は上記課題を解決
するために、セラミック基板をチップキャリアとした場
合、半田にてチップキャリアをプリント配線基板に実装
するにおいて、チップキャリア裏面に配置された外部接
続用電極を回路配線基板の電極サイズより大きくして半
田付けする事により、チップキャリア側と半田との接続
部の角度を鈍角となるような半田の形状にする事が可能
となる。それにより、チップキャリア部にかかる応力を
軽減する。In order to solve the above problems, according to the present invention, when a ceramic substrate is used as a chip carrier, it is arranged on the back surface of the chip carrier when the chip carrier is mounted on a printed wiring board by soldering. By soldering the electrodes for external connection larger than the electrode size of the circuit wiring board and soldering, it is possible to make the shape of the solder such that the angle between the chip carrier side and the solder is an obtuse angle. This reduces the stress applied to the chip carrier portion.
【０００７】[0007]
【作用】本発明によると、熱衝撃試験における半田接続
部に集中する歪応力をチップキャリアの外部接続用電極
のサイズをチップキャリアの電極と対応するプリント配
線基板の電極のサイズより大きくすることで半田の形状
をチップキャリア側にかかる応力を軽減する形状にする
ことが可能となる。According to the present invention, the strain stress concentrated in the solder connection portion in the thermal shock test is made larger than the size of the external connection electrode of the chip carrier and the size of the electrode of the printed wiring board corresponding to the electrode of the chip carrier. It is possible to change the shape of the solder into a shape that reduces the stress applied to the chip carrier side.
【０００８】[0008]
【実施例】以下本発明の一実施例について、図面を参照
しながら説明する。図１は本発明の一実施例におけるチ
ップキャリアをプリント配線基板に半田にて実装した後
の断面図、図２は本発明の一実施例におけるチップキャ
リアを裏面からみた平面図、図３は本発明の他の実施例
におけるチップキャリアを裏面からみた平面図を示す。An embodiment of the present invention will be described below with reference to the drawings. 1 is a cross-sectional view of a chip carrier according to an embodiment of the present invention after being mounted on a printed wiring board by soldering, FIG. 2 is a plan view of the chip carrier according to an embodiment of the present invention seen from the back surface, and FIG. The top view which looked at the chip carrier in the other Example of the invention from the back surface is shown.
【０００９】１はチップキャリア、３は半導体素子、４
は絶縁性基板、５はプリント配線基板、３１は電極パッ
ド、３３はＡｕバンプ、３４は導電性接着剤、３５は封
止樹脂、４ａは表面、４ｂは裏面、４１は接続配線、４
３はビアホール、４４はプリント配線基板の電極よりも
サイズの大きい外部接続電極、４５は丸形の外部接続電
極、４６は格子状に配置された外部接続電極、４７は角
形の外部接続電極、５１はプリント配線基板側電極であ
る。1 is a chip carrier, 3 is a semiconductor element, 4
Is an insulating substrate, 5 is a printed wiring board, 31 is an electrode pad, 33 is an Au bump, 34 is a conductive adhesive, 35 is a sealing resin, 4a is the front surface, 4b is the back surface, 41 is connection wiring, 4
3 is a via hole, 44 is an external connection electrode having a size larger than the electrode of the printed wiring board, 45 is a round external connection electrode, 46 is an external connection electrode arranged in a grid pattern, 47 is a rectangular external connection electrode, 51 Is a printed wiring board side electrode.
【００１０】基板形成用素材として、ガラスセラミック
（日本電気ガラス社製 ＭＬＳ−１０００平均粒形２μ
ｍ）を無機成分とし、バインダ（アクリル系樹脂）を１
２ｗｔ％加えて粘度が２００００ｃｐｓになるように混
合した後、ドクターブレード法にてシート状に成形し
た。前記シートの厚みは、２００μｍとした。前記グリ
ーンシートにビア孔を形成した。As a material for forming a substrate, glass ceramic (manufactured by Nippon Electric Glass Co., Ltd. MLS-1000 average grain shape 2 μm
m) as an inorganic component and a binder (acrylic resin) 1
After adding 2 wt% and mixing so that the viscosity would be 20000 cps, it was formed into a sheet by the doctor blade method. The thickness of the sheet was 200 μm. Via holes were formed in the green sheet.
【００１１】導体ペーストは、ＣｕＯ粉末（平均粒径３
μｍ）に接着強度を得るためのガラスフリット（日本電
気硝子社製 ＬＳ−０８０３ガラス粉末、平均粒径３μ
ｍ）を２．５ｗｔ％加えたものを無機成分とし、有機バ
インダであるエチルセルロースをターピネオールに溶か
したビヒクルを加えて、３段ロールにより粘度が１７０
００ｃｐｓになるように混合して作製した。The conductor paste is CuO powder (average particle size 3
Glass frit (LS-0803 glass powder manufactured by Nippon Electric Glass Co., Ltd., average particle size 3 μm) for obtaining adhesive strength
2.5 wt% of m) was added as an inorganic component, and a vehicle in which ethyl cellulose, which is an organic binder, was dissolved in terpineol was added.
It was prepared by mixing so as to be 00 cps.
【００１２】前記ビア孔形成済みグリーンシートに前記
ＣｕＯペーストをグリーンシートの裏面から吸引しなが
ら、メタルマスクにてビア孔を埋め、空気中で乾燥し
た。所望の枚数の前記ビア孔埋め後のグリーンシートを
積層し、熱圧着した。While suctioning the CuO paste from the back surface of the green sheet to the green sheet having the via holes formed therein, the via holes were filled with a metal mask and dried in air. A desired number of green sheets after filling the via holes were stacked and thermocompression bonded.
【００１３】次に前記積層体を空気中、６００℃の温度
で脱バインダを行なった。その後前記積層体を水素ガス
１００％雰囲気中で２００℃−５時間で還元した。この
時のＣｕ層をＸ線回折により分析したところ１００％Ｃ
ｕであることを確認した。しかる後、窒素中９００℃の
メッシュベルト炉で焼成した。Next, the laminate was debindered in air at a temperature of 600.degree. Then, the laminated body was reduced in an atmosphere of 100% hydrogen gas at 200 ° C. for 5 hours. When the Cu layer at this time was analyzed by X-ray diffraction, it was 100% C
It was confirmed to be u. Then, it was fired in a mesh belt furnace at 900 ° C. in nitrogen.
【００１４】前記の焼成済みのセラミック基板に配線用
パターン４１を片面に印刷し、またもう一方の面に外部
接続電極４４をチップキャリア側が実装用プリント配線
基板側電極５１より大きいパターン４５でスクリーン印
刷法にて印刷した。配線パターン用導体としては、一般
に市販されているＤｕｐｏｎｔ社製ＱＰ１５３ペースト
を使用した。前記印刷済み焼結体を窒素中９００℃のメ
ッシュベルト炉で焼成して、焼結済みセラミック基板を
得、チップキャリア１とした。A wiring pattern 41 is printed on one surface of the fired ceramic substrate, and external connection electrodes 44 are screen-printed on the other surface with a pattern 45 in which the chip carrier side is larger than the mounting printed wiring board side electrode 51. Printed by the method. As the wiring pattern conductor, a commercially available QP153 paste manufactured by Dupont was used. The printed sintered body was fired in nitrogen in a mesh belt furnace at 900 ° C. to obtain a sintered ceramic substrate, and the chip carrier 1 was obtained.
【００１５】次に、Ａｕバンプ３３の形成された半導体
素子３が、その表面側を下にして前記セラミックからな
るチップキャリア１と接合されている。チップキャリア
１上の電極４１と半導体素子３上のＡｕバンプ３３とは
導電性接着剤３４で接合されている。導電性接着剤３４
は、Ａｕバンプ３３にあらかじめ供給されている。導電
性接着剤３４としては、Ａｇ−Ｐｄを導電フィラーと
し、バインダとしてエポシキ系樹脂を５ｗｔ％加え、適
当な粘度に混合して使用した。そして、接合された半導
体素子３とチップキャリア１との間の隙間は、エポシキ
系の封止樹脂３５にて充填されている。封止樹脂３５
は、エポシキ系樹脂にフィラーとして高熱伝導セラミッ
クである窒化アルミニウム、もしくは窒化珪素を添加し
た樹脂を用いた。チップキャリア１の裏面４ｂには、本
チップキャリア１を実装するプリント配線基板５のチッ
プキャリア１の電極と対応して形成された電極５１より
もサイズの大きい丸形の外部接続電極４４（図２の４
５）、または角形の外部接続電極４４（図３の４７）が
格子状に形成されている。Next, the semiconductor element 3 having the Au bumps 33 formed thereon is joined to the chip carrier 1 made of the ceramic with the front surface side facing down. The electrodes 41 on the chip carrier 1 and the Au bumps 33 on the semiconductor element 3 are joined by a conductive adhesive 34. Conductive adhesive 34
Are previously supplied to the Au bumps 33. As the conductive adhesive 34, Ag-Pd was used as a conductive filler, and 5 wt% of epoxy resin was added as a binder and mixed to have an appropriate viscosity. The gap between the bonded semiconductor element 3 and the chip carrier 1 is filled with epoxy sealing resin 35. Sealing resin 35
As the epoxy resin, a resin obtained by adding aluminum nitride, which is a high thermal conductive ceramic, or silicon nitride as a filler to an epoxy resin is used. On the back surface 4b of the chip carrier 1, a round external connection electrode 44 (see FIG. 2) having a size larger than the electrode 51 formed corresponding to the electrode of the chip carrier 1 of the printed wiring board 5 on which the present chip carrier 1 is mounted. Of 4
5), or the prismatic external connection electrodes 44 (47 in FIG. 3) are formed in a grid pattern.
【００１６】次に、チップキャリア実装用基板として市
販のプリント配線基板５（ＦＲ−４）を使用した。前記
プリント配線基板５上にメタル印刷にて半田ペーストを
印刷した。前記半田ペーストは千住金属（株）社製のＯ
Ｚ−６３−２０１Ｃ−５０−９を使用した。前記印刷済
みプリント配線基板５にプリント配線基板５の電極とチ
ップキャリア１の外部接続電極４４が対応するように前
記半導体素子実装済みチップキャリアを実装した。Next, a commercially available printed wiring board 5 (FR-4) was used as a chip carrier mounting board. A solder paste was printed on the printed wiring board 5 by metal printing. The solder paste is O manufactured by Senju Metal Co., Ltd.
Z-63-201C-50-9 was used. The chip carrier on which the semiconductor elements were mounted was mounted on the printed circuit board 5 on which the semiconductor element was mounted so that the electrodes of the printed circuit board 5 and the external connection electrodes 44 of the chip carrier 1 corresponded to each other.
【００１７】その後、ピーク温度２４０℃−１０秒で大
気中でリフローし、前記プリント配線基板と前記チップ
キャリアとを金属接合させた。After that, reflow was performed in the atmosphere at a peak temperature of 240 ° C. for 10 seconds to metal-bond the printed wiring board and the chip carrier.
【００１８】前記実装済みプリント配線基板をＪＩＳ規
格Ｃ００２５にて示してある、−４０℃（３０分）から
＋１００℃（３０分）の熱衝撃環境信頼性試験にて評価
したところ、従来のチップキャリアの外部接続電極のサ
イズとプリント配線基板の電極サイズとを同じ大きさに
していたものでは、２００サイクルでオープンが発生し
たのに対し、本発明のチップキャリアにおいては、６０
０サイクルでのオープン発生と飛躍的に信頼性が向上し
た。また、前記実装体の断面を観察したところ、実装部
の半田形状がチップキャリアの外部接続電極側が大き
く、プリント配線基板の電極側が小さくなった台形状に
なっていた。The mounted printed wiring board was evaluated in a thermal shock environment reliability test from -40 ° C. (30 minutes) to + 100 ° C. (30 minutes) shown in JIS C0025. In the case where the size of the external connection electrode and the electrode size of the printed wiring board were the same, the open occurred at 200 cycles, whereas in the chip carrier of the present invention,
Opening occurred in 0 cycle and reliability was dramatically improved. Further, when the cross section of the mounting body was observed, the solder shape of the mounting portion was a trapezoidal shape in which the external connection electrode side of the chip carrier was large and the electrode side of the printed wiring board was small.
【００１９】また、チップキャリアに形成された外部接
続電極の形状を角形にする事で電極の絶縁性基板４にお
ける接続面積が増すので、電極の基板４への接着強度を
増加することができる。それにより電極の接着力の強い
チップキャリアを形成できる。Further, by making the shape of the external connection electrode formed on the chip carrier rectangular, the connection area of the electrode on the insulating substrate 4 increases, so that the adhesive strength of the electrode to the substrate 4 can be increased. As a result, a chip carrier having a strong electrode adhesive force can be formed.
【００２０】本発明により、プリント配線基板上での実
装信頼性の高いチップキャリアを実現可能とした。ま
た、本発明で使用したチップキャリアは、内層を有する
多層基板においても実現可能であることはいうまでもな
い。According to the present invention, a chip carrier having high mounting reliability on a printed wiring board can be realized. Further, it goes without saying that the chip carrier used in the present invention can be realized also in a multilayer substrate having an inner layer.
【００２１】また、外部接続電極を図２や図３のように
格子状に外部接続電極を形成することで、側面だけに外
部接続電極をだすよりも多ピン化に対応できるようにな
る。Further, by forming the external connection electrodes in a grid pattern as shown in FIGS. 2 and 3, it is possible to cope with a larger number of pins than when the external connection electrodes are provided only on the side surface.
【００２２】[0022]
【発明の効果】本発明によると、環境信頼性試験におけ
るプリント配線基板への実装信頼性の高いセラミックか
らなるチップキャリアを提供できる。また、チップキャ
リアの外部接続用電極サイズを変えるだけで実装信頼性
の高いチップキャリアとすることができるので、容易に
実施することができる。According to the present invention, it is possible to provide a chip carrier which is made of ceramic and has high mounting reliability on a printed wiring board in an environmental reliability test. Further, since it is possible to obtain a chip carrier with high mounting reliability simply by changing the size of the external connection electrode of the chip carrier, it can be easily implemented.
【図１】本発明の実施例におけるチップキャリアのプリ
ント配線基板への半田実装後の断面図FIG. 1 is a cross-sectional view after mounting a chip carrier on a printed wiring board by soldering in an embodiment of the present invention.
【図２】本発明の実施例におけるチップキャリアの裏面
から見た平面図FIG. 2 is a plan view seen from the back surface of the chip carrier according to the embodiment of the present invention.
【図３】本発明の実施例におけるチップキャリアの裏面
から見た平面図FIG. 3 is a plan view seen from the back surface of the chip carrier according to the embodiment of the present invention.
【図４】従来例のＢＧＡ（ボール・グリッド・アレイ）
パッケージのプリント配線基板への半田実装後の断面図FIG. 4 BGA (ball grid array) of a conventional example
Sectional view of package after solder mounting on printed wiring board
１ チップキャリア ３ 半導体素子 ４ 絶縁性基板 ５ プリント配線基板 ３１ 電極パッド ３３ Ａｕバンプ ３４ 導電性接着剤 ３５ 封止樹脂 ４ａ 表面 ４ｂ 裏面 ４１ 接続配線 ４３ ビアホール ４４ 外部接続電極 ４５ 丸形の外部接続電極 ４６ 格子状に形成された外部接続電極 ４７ 角形の外部接続電極 ５１ プリント配線基板側電極 1 Chip Carrier 3 Semiconductor Element 4 Insulating Substrate 5 Printed Wiring Board 31 Electrode Pad 33 Au Bump 34 Conductive Adhesive 35 Sealing Resin 4a Surface 4b Backside 41 Connection Wiring 43 Via Connection 44 External Connection Electrode 45 Round External Connection Electrode 46 External connection electrodes 47 formed in a grid 47 Rectangular external connection electrodes 51 Printed wiring board side electrodes
Claims (4)
らなる外部接続用電極のサイズを、前記チップキャリア
を実装するプリント配線基板の前記チップキャリアと対
応して接続される電極サイズより大きくする事を特徴と
するチップキャリア。1. A size of an electrode for external connection made of a conductor arranged on the back surface of a chip carrier is made larger than an electrode size connected corresponding to the chip carrier of a printed wiring board on which the chip carrier is mounted. Chip carrier characterized by.
らなる電極の形状を丸形あるいは角形にする事を特徴と
する請求項１に記載のチップキャリア。2. The chip carrier according to claim 1, wherein the shape of the electrode made of a conductor arranged on the back surface of the chip carrier is round or square.
電極が格子状に形成されている事を特徴とする請求項１
に記載のチップキャリア。3. The external connection electrodes arranged on the back surface of the chip carrier are formed in a grid pattern.
The chip carrier described in.
リアとプリント配線基板とを半田にて接続するにおい
て、前記半田の融解硬化後の形状が前記プリント配線基
板側の面積より前記チップキャリア側の面積が大きくな
るような円筒形である事を特徴とするチップキャリアの
実装体。4. When a chip carrier having an electrode for external connection on the back surface and a printed wiring board are connected by solder, the shape of the solder after melting and hardening is closer to the chip carrier side than the area on the printed wiring board side. A chip carrier mounting body having a cylindrical shape with a large area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7073374A JP2932964B2 (en) | 1995-03-30 | 1995-03-30 | Chip carrier and its mounting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7073374A JP2932964B2 (en) | 1995-03-30 | 1995-03-30 | Chip carrier and its mounting |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08274213A true JPH08274213A (en) | 1996-10-18 |
| JP2932964B2 JP2932964B2 (en) | 1999-08-09 |
Family
ID=13516350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7073374A Expired - Fee Related JP2932964B2 (en) | 1995-03-30 | 1995-03-30 | Chip carrier and its mounting |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2932964B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005317790A (en) * | 2004-04-28 | 2005-11-10 | Ibiden Co Ltd | Interposer |
| US8233288B2 (en) | 2007-04-24 | 2012-07-31 | Panasonic Corporation | Electronic component package, electronic component mounted apparatus, method of inspecting bonding portion therein, and circuit board |
-
1995
- 1995-03-30 JP JP7073374A patent/JP2932964B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005317790A (en) * | 2004-04-28 | 2005-11-10 | Ibiden Co Ltd | Interposer |
| JP4489491B2 (en) * | 2004-04-28 | 2010-06-23 | イビデン株式会社 | Interposer |
| US8233288B2 (en) | 2007-04-24 | 2012-07-31 | Panasonic Corporation | Electronic component package, electronic component mounted apparatus, method of inspecting bonding portion therein, and circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2932964B2 (en) | 1999-08-09 |
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