JPH08255814A - Semiconductor device of tape carrier type - Google Patents

Semiconductor device of tape carrier type

Info

Publication number
JPH08255814A
JPH08255814A JP5788195A JP5788195A JPH08255814A JP H08255814 A JPH08255814 A JP H08255814A JP 5788195 A JP5788195 A JP 5788195A JP 5788195 A JP5788195 A JP 5788195A JP H08255814 A JPH08255814 A JP H08255814A
Authority
JP
Japan
Prior art keywords
hole
solder
semiconductor device
tape carrier
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5788195A
Other languages
Japanese (ja)
Other versions
JP2636785B2 (en
Inventor
Yuichi Miyazaki
裕一 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7057881A priority Critical patent/JP2636785B2/en
Publication of JPH08255814A publication Critical patent/JPH08255814A/en
Application granted granted Critical
Publication of JP2636785B2 publication Critical patent/JP2636785B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/361Assembling flexible printed circuits with other printed circuits
    • H05K3/363Assembling flexible printed circuits with other printed circuits by soldering
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To provide a semiconductor device of film carrier type which is simple in manufacturing process, high in connection reliability, and easily checked. CONSTITUTION: A semiconductor device of film carrier type is provided with a hole cut in an insulating film 2 where an LSI 1 is arranged, a wiring connected to the LSI 1, and an external connecting terminal, wherein the external connecting terminal 3 is composed of a through-hole 10 and a metal film formed on the inner wall of the through-hole 10, and solder fed onto a wiring board is made to creep up in the through-hole 10 for making mechanical and electrical connections.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、情報処理装置等の電子
機器に使用される例えばLSIに代表される集積回路テ
ープキャリアを用いた半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using an integrated circuit tape carrier represented by, for example, an LSI, which is used in electronic equipment such as an information processing device.

【0002】[0002]

【従来の技術】近年、情報処理装置等に使用される集積
回路の集積度は増加の一途をたどる一方であり、それに
ともない、LSIのパッケージもデュアル・イン・ライ
ン・パッケージ(Dual in line Pack
age(以下DIPと称す),クワッド・フラット・パ
ック(Quad Flat Pack(以下QFPと称
す),ピン・グリッド・アレイ(Pin Grid A
rray(以下PGA)へと高密度化が進んでいる。近
年では、更に高密度化を行うため絶縁フィルムにLSI
を接続するテープ・キャリア・パッケージ(Tape
CarrierPackage(以下TCPと称す)が
使用されている。
2. Description of the Related Art In recent years, the degree of integration of integrated circuits used in information processing apparatuses and the like has been steadily increasing, and accordingly, LSI packages have also become dual in line packages (Dual in Line Packages).
age (hereinafter, referred to as DIP), Quad Flat Pack (hereinafter, referred to as QFP), Pin Grid Array (Pin Grid A)
The density has been increasing to rray (hereinafter PGA). In recent years, in order to further increase the density, LSI
To connect the tape carrier package (Tape
CarrierPackage (hereinafter referred to as TCP) is used.

【0003】その一例が米国特許第4658331号公
報に示されている。いま、この例を図5を参照して説明
する。この公報によれば、ICチップ105に取り付け
られたリード106は圧力パッド12により回路基板1
03上のアウター・リード・ボンディング(以下OL
B)パッド104へ圧接されて電気的に接続される。圧
力パッド12は熱伝導プレート101と一体になってお
り、ICチップ105から発生した熱は、この熱伝導プ
レート101から排熱される。
One example is shown in US Pat. No. 4,658,331. Now, this example will be described with reference to FIG. According to this publication, the lead 106 attached to the IC chip 105 is connected to the circuit board 1 by the pressure pad 12.
Outer lead bonding on 03 (hereinafter OL
B) The pad 104 is pressed and electrically connected. The pressure pad 12 is integrated with the heat conducting plate 101, and the heat generated from the IC chip 105 is exhausted from the heat conducting plate 101.

【0004】[0004]

【発明が解決しようとする課題】高密度のパッケージと
いわれるPGAは、入出力(以下I/O)ピンを基板の
裏面に設け、配線基板上へ半田付け等で実装していた
が、実装後の状態での半田付けの検査は、PGA自身で
見えなくなり、外観による検査ができなかった。
The PGA, which is called a high-density package, has input / output (I / O) pins on the back surface of the substrate and is mounted on a wiring substrate by soldering or the like. In the inspection of the soldering in the state described above, the PGA itself became invisible, and the inspection based on the external appearance could not be performed.

【0005】また、上述した米国特許第4658331
号公報記載の技術では、配線基板上のOLBパッド10
4とリード106とが圧接して電気的接続を行うので、
接続の信頼性が低く、装置の信頼性を大きく損なう原因
となっていた。
[0005] Also, the above-mentioned US Patent No. 4,658,331.
In the technique described in Japanese Patent Application Laid-Open Publication No.
4 and the lead 106 are pressed against each other to make an electrical connection.
The reliability of the connection was low, causing a great loss in the reliability of the device.

【0006】本発明の目的は、装置の製造工程を簡略化
するようにしたテープキャリアを用いた半導体装置を提
供することにある。
It is an object of the present invention to provide a semiconductor device using a tape carrier which simplifies the manufacturing process of the device.

【0007】本発明の他の目的は、ハンダのすい上げを
外観で確認し検査の効率を向上するようにしたテープキ
ャリアを用いた半導体装置を提供することにある。
Another object of the present invention is to provide a semiconductor device using a tape carrier which is capable of visually confirming the picking up of solder and improving the efficiency of inspection.

【0008】本発明の他の目的はフィルムキャリアと配
線基板との接続の信頼性を向上させるようにしたテープ
キャリアを用いた半導体装置を提供することにある。
Another object of the present invention is to provide a semiconductor device using a tape carrier for improving the reliability of connection between a film carrier and a wiring board.

【0009】[0009]

【課題を解決するための手段】本発明のテープキャリア
を用いた第1の半導体装置は、スルーホールを有し表面
に配線の施された絶縁テープと、この絶縁フィルム上の
前記配線の一端に接続された入出力端子を有する半導体
チップ(以下LSI)と、前記絶縁フィルム上の前記配
線の他端に接続された前記スルーホール側壁に設けられ
た金属膜とを含む。
A first semiconductor device using the tape carrier of the present invention is an insulating tape having a through hole and having wiring on its surface, and one end of the wiring on the insulating film. A semiconductor chip (hereinafter referred to as LSI) having connected input / output terminals, and a metal film provided on the side wall of the through hole connected to the other end of the wiring on the insulating film are included.

【0010】本発明のテープキャリアを用いた第2の半
導体装置は、前記テープキャリアを用いた第1の半導体
装置において前記スルーホール内の金属膜と密着し配線
基板上のパッドと電気的に接続するハンダを備えてい
る。
A second semiconductor device using the tape carrier of the present invention is in close contact with the metal film in the through hole in the first semiconductor device using the tape carrier and is electrically connected to a pad on the wiring board. Equipped with solder.

【0011】本発明のテープキャリアを用いた第3の半
導体装置は、前記テープキャリアを用いた第2の半導体
装置における前記ハンダの組成がスズ,鉛,および金の
少なくとも1つを主成分とすることを特徴とする。
In a third semiconductor device using the tape carrier of the present invention, the composition of the solder in the second semiconductor device using the tape carrier contains at least one of tin, lead and gold as a main component. It is characterized by

【0012】[0012]

【実施例】次に本発明の実施例について図面を参照して
詳細に説明する。
Embodiments of the present invention will now be described in detail with reference to the drawings.

【0013】図1および図2を参照すると、本発明の実
施例は、厚さ100ミクロン(μm)の絶縁フィルム
2,この絶縁フィルム2の中央にあけられた穴に実装さ
れる半導体チップの一例であるLSI1,このLSI1
の入出力端子に接続されるインナーリードボンディング
部(以下ILB部)9,このILB部9を先端にもつイ
ンナーリード4,このインナーリード4と接続されこの
インナーリード4とともにLSI1と配線基板8とを電
気的に接続するアウターリード5,このアウターリード
5の先端に位置し絶縁フィルム2を貫通するスルーホー
ル10およびこのスルーホール10の側壁に設けられた
アウターリード5と同じ種類の金属で形成される金属膜
6からなる外部接続端子部(以下OLB部)3を備えて
いる。
Referring to FIG. 1 and FIG. 2, an embodiment of the present invention is an example of an insulating film 2 having a thickness of 100 μm (μm) and an example of a semiconductor chip mounted in a hole formed in the center of the insulating film 2. LSI1, this LSI1
The inner lead bonding portion (hereinafter referred to as ILB portion) 9 connected to the input / output terminals, the inner lead 4 having the ILB portion 9 at its tip, the LSI 1 and the wiring board 8 connected to the inner lead 4 together with the inner lead 4. Outer leads 5 to be electrically connected, through holes 10 located at the tips of outer leads 5 and penetrating insulating film 2, and the same type of metal as outer leads 5 provided on the side walls of through holes 10. An external connection terminal (OLB) 3 made of a metal film 6 is provided.

【0014】厚さ100ミクロン(μm)の絶縁フィル
ム2上に銅(Cu)等の導体にて幅40ミクロン(μ
m)のアウターリード5が配線される。絶縁フィルム2
の中央にはLSI1が搭載できるようLSI1より大き
な穴がつくられている。この穴へLSI1がセットさ
れ、LSI1の入出力端子とインナーリード4とが接続
されて機械的および電気的にLSIと絶縁フィルムキャ
リア2とが接続される。このインナーリード4とアウタ
ーリード5とはそれぞれLSI1と配線基板8とを電気
的に接続を行うものである。
A conductor of copper (Cu) or the like has a width of 40 microns (μ) on the insulating film 2 having a thickness of 100 μm (μm).
The m) outer leads 5 are wired. Insulation film 2
A hole larger than the LSI1 is formed in the center of the so that the LSI1 can be mounted. The LSI 1 is set in this hole, the input / output terminals of the LSI 1 and the inner leads 4 are connected, and the LSI and the insulating film carrier 2 are mechanically and electrically connected. The inner lead 4 and the outer lead 5 electrically connect the LSI 1 and the wiring board 8, respectively.

【0015】一方、アウターリードの先端にはアウター
・リード・ボンディング部(以下OLB部)3が設けら
れている。このOLB部3は絶縁フィルム2を貫通する
スルーホール10となっており、その側壁にはアウター
リード5と同様の導体でメタライズされている。スルー
ホール10の形状は円状、正方状等制限はない。また、
スルーホール10の断面形状も長方形、台形等制限はな
いが、配線基板との対抗面のスルーホールの開口部の大
きさは約φ100ミクロン(μm)が望ましい。
On the other hand, an outer lead bonding portion (OLB portion) 3 is provided at the tip of the outer lead. The OLB portion 3 is a through hole 10 penetrating the insulating film 2, and its side wall is metallized with the same conductor as the outer lead 5. The shape of the through hole 10 is not limited, such as a circular shape or a square shape. Also,
The cross-sectional shape of the through hole 10 is not limited to a rectangle, a trapezoid, or the like, but the size of the opening of the through hole on the surface facing the wiring board is preferably about φ100 μm (μm).

【0016】次に、OLB部3のスルーホール10内に
ハンダ(半田)を充填する方法について図3を参照して
詳細に説明する。
Next, a method of filling the through hole 10 of the OLB portion 3 with solder (solder) will be described in detail with reference to FIG.

【0017】図3を参照すると、絶縁フィルム2に形成
されたスルーホール10の側壁には、ハンダ(半田)7
が濡れやすいような金属膜6が施されている。また、金
属膜6は、スルーホール10のみではなく絶縁フィルム
2表裏のスルーホールの周辺にもスルーホールを囲むよ
うにしてある。これはハンダ(半田)の密着面積をより
大きくするためである。ハンダ(半田)7はこのスルー
ホール10内に充填されて、配線基板8と絶縁フィルム
2上のOLB部3とを電気的および機械的に接続してい
る。ハンダ(半田)7の組成としては、スズ(Sn)6
3%/鉛(Pb)37%の共晶半田や、スズ(Sn)5
%/鉛(Pb)95%、金(Au)20%/スズ(S
n)80%等の高温ハンダ(半田)等が使用される。
Referring to FIG. 3, solder (solder) 7 is provided on the side wall of through hole 10 formed in insulating film 2.
Is provided with a metal film 6 which is easy to get wet. The metal film 6 surrounds the through hole not only at the through hole 10 but also around the through hole on the front and back of the insulating film 2. This is for further increasing the contact area of the solder (solder). The solder (solder) 7 is filled in the through hole 10 to electrically and mechanically connect the wiring board 8 and the OLB portion 3 on the insulating film 2. The composition of the solder (solder) 7 is tin (Sn) 6
3% / lead (Pb) 37% eutectic solder, tin (Sn) 5
% / Lead (Pb) 95%, gold (Au) 20% / tin (S
n) High-temperature solder (solder) such as 80% is used.

【0018】次にフィルムキャリアと配線基板8との接
続の工程を図4を参照しながら詳細に説明する。
Next, the process of connecting the film carrier to the wiring board 8 will be described in detail with reference to FIG.

【0019】図4(A)を参照すると、配線基板8のパ
ッド11へハンダ(半田)7が供給される。このパッド
11は配線基板8内で配線された内層パターンとつなが
っており、さらに外部へと接続がなされる。
Referring to FIG. 4A, solder (solder) 7 is supplied to pads 11 of wiring board 8. The pad 11 is connected to an inner layer pattern wired in the wiring board 8, and is further connected to the outside.

【0020】次に、図4(B)を参照すると、OLB部
3と基板のパッド11とが11対1となるよう配線基板
8とテープキャリアとの位置あわせが行われる。次に、
全体が200℃〜250℃に加熱されてハンダ(半田)
7が溶かされ、スルーホール10内をハンダ(半田)7
がすい上がらせる。スルーホール10にはハンダ(半
田)が濡れやすいような金属膜6が施してあるため非常
にすい上がりやすくなっている。また、金属膜6はフィ
ルムキャリア上の配線(アウターリード5)とつながっ
ているので電気的にLSI1と接続することができる。
以上のように、本発明の実施例は製造工程を単純にした
という効果がある。また、スルーホール10にハンダ
(半田)7が充填している状態を確認しやすいので、検
査方法が簡単になるという効果がある。
Next, referring to FIG. 4B, the positioning of the wiring board 8 and the tape carrier is performed so that the OLB portion 3 and the pad 11 of the board are 11: 1. next,
The whole is heated to 200 to 250 ° C and solder (solder)
7 is melted, and solder (solder) 7 is formed in the through hole 10.
Let it rise. Since the through-hole 10 is provided with the metal film 6 which makes it easy for the solder (solder) to get wet, it is very easy to lift up. Further, since the metal film 6 is connected to the wiring (outer lead 5) on the film carrier, it can be electrically connected to the LSI 1.
As described above, the embodiment of the present invention has an effect that the manufacturing process is simplified. In addition, since it is easy to confirm the state where the solder (solder) 7 is filled in the through hole 10, there is an effect that the inspection method is simplified.

【0021】[0021]

【発明の効果】以上のように、テープキャリアにスルー
ホールを設け、基板とフィルムキャリアの接続をスルー
ホール内でのハンダ(半田)をすい上がらせて接続させ
たことにより、装置の製造工程を非常に簡単で製造しや
すいものにすることができた。また、ハンダ(半田)8
すい上がりの状態を外観で確認できるので検査が非常に
行いやすいという効果もある。さらに、フィルムキャリ
アと配線基板との接続をハンダ(半田)で行っているの
で信頼性の高いものにできた。また、スルーホールでハ
ンダ(半田)のすい上げを確認することで接続の確認が
できる。このため、検査が非常に簡単になった。
As described above, the through hole is provided in the tape carrier, and the connection between the substrate and the film carrier is made by connecting the solder (solder) in the through hole to thereby increase the manufacturing process of the device. It was very simple and easy to manufacture. Also, solder (solder) 8
There is also an effect that the inspection can be performed very easily because the appearance of the rising state can be confirmed. Further, since the film carrier and the wiring board are connected by solder (solder), the reliability can be improved. Also, the connection can be confirmed by confirming the solder (solder) pick-up in the through hole. This made the inspection much easier.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す斜視図である。FIG. 1 is a perspective view showing an embodiment of the present invention.

【図2】図1の一実施例のA−A′で切断した状態を示
す断面図である。
FIG. 2 is a cross-sectional view showing a state cut along AA ′ in the embodiment of FIG.

【図3】図2に示されるアウターリードボンディング部
の断面を拡大した拡大断面図である。
FIG. 3 is an enlarged sectional view showing an enlarged section of an outer lead bonding portion shown in FIG. 2;

【図4】(A)−(C)は図3に示されたアウターリー
ドボンディング部の製造工程を示す図である。
4 (A) to 4 (C) are views showing a manufacturing process of an outer lead bonding portion shown in FIG. 3;

【図5】従来技術の一例を示す図である。FIG. 5 is a diagram showing an example of a conventional technique.

【符号の説明】[Explanation of symbols]

1 LSI 2 絶縁フィルム 3 OLB部 4 インナーリード 5 アウターリード 6 メタライズ 7 ハンダ(半田) 8 配線基板 9 ILB部 10 スルーホール 11 パッド 12 圧力パッド 101 熱伝導プレート 103 回路基板 104 OLBパッド 105 ICチップ 106 リード DESCRIPTION OF SYMBOLS 1 LSI 2 Insulating film 3 OLB part 4 Inner lead 5 Outer lead 6 Metallization 7 Solder (solder) 8 Wiring board 9 ILB part 10 Through hole 11 Pad 12 Pressure pad 101 Heat conduction plate 103 Circuit board 104 OLB pad 105 IC chip 106 Lead

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 スルーホールを有し表面に配線の施され
た絶縁テープと、 この絶縁フィルム上の前記配線の一端に接続された入出
力端子を有する半導体チップと、 前記絶縁フィルム上の前記配線の他端に接続された前記
スルーホール側壁に設けられた金属膜とを含むことを特
徴とするテープキャリアを用いた半導体装置。
1. An insulating tape having a through hole and having wiring on its surface, a semiconductor chip having an input / output terminal connected to one end of the wiring on the insulating film, and the wiring on the insulating film. And a metal film provided on the side wall of the through hole connected to the other end of the semiconductor device using the tape carrier.
【請求項2】 前記スルーホール内の金属膜と密着し配
線基板上のパッドと電気的に接続するハンダを備えたこ
とを特徴とする請求項1記載のテープキャリアを用いた
半導体装置。
2. A semiconductor device using a tape carrier according to claim 1, further comprising a solder which is in close contact with the metal film in the through hole and is electrically connected to a pad on the wiring board.
【請求項3】 前記ハンダの組成がスズ,鉛および金の
少なくとも1つを主成分とすることを特徴とする請求項
2記載のテープキャリアを用いた半導体装置。
3. A semiconductor device using a tape carrier according to claim 2, wherein the composition of the solder contains at least one of tin, lead and gold as a main component.
JP7057881A 1995-03-17 1995-03-17 Semiconductor device mounting method Expired - Fee Related JP2636785B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7057881A JP2636785B2 (en) 1995-03-17 1995-03-17 Semiconductor device mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7057881A JP2636785B2 (en) 1995-03-17 1995-03-17 Semiconductor device mounting method

Publications (2)

Publication Number Publication Date
JPH08255814A true JPH08255814A (en) 1996-10-01
JP2636785B2 JP2636785B2 (en) 1997-07-30

Family

ID=13068340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7057881A Expired - Fee Related JP2636785B2 (en) 1995-03-17 1995-03-17 Semiconductor device mounting method

Country Status (1)

Country Link
JP (1) JP2636785B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51106641A (en) * 1975-03-17 1976-09-21 Matsushita Electric Ind Co Ltd IONPUREETEINGUSOCHI
JPS6334936A (en) * 1986-07-29 1988-02-15 Nec Corp Mounting structure of tape carrier

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51106641A (en) * 1975-03-17 1976-09-21 Matsushita Electric Ind Co Ltd IONPUREETEINGUSOCHI
JPS6334936A (en) * 1986-07-29 1988-02-15 Nec Corp Mounting structure of tape carrier

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