JPH08249244A - Data holding circuit - Google Patents

Abstract

PURPOSE: To provide a highly reliable data holding circuit capable of inhibiting the generation of the destruction of already stored data and preventing the loss of data to be updated even when the disconnection or the instantaneous break of a power source is generated. CONSTITUTION: When the disconnection or the instantaneous break of the power supply voltage Vcc of a device is generated, the power supply voltages V1 and V2 outputted from a power source regulator 21 are lowered. The decline of the power supply voltage V1 is detected in a voltage decline detector 25, a NAND gate 26 is closed by reset signals outputted from the detector 25 and chip selection signals CSROM outputted from a CPU 22 are interrupted. By the power supply voltage V2a for a memory charged to a capacitor 29, the operating state of the NAND gate 26 and an EEPROM 24 is maintained. As the power supply voltage V2a is lowered, the write of the EEPROM 24 is inhibited by memory reset signals REST2/outputted from the voltage decline detector 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data holding circuit for backing up a data holding memory provided in a portable telephone or the like, which prevents data from being destroyed due to power interruption or momentary interruption.

[0002]

2. Description of the Related Art Conventionally, in a control device using a central processing unit (hereinafter referred to as CPU), it is essential to have a memory for temporarily or semi-permanently holding data. As a memory that semi-permanently retains data, a rewritable nonvolatile memory such as EPR is generally used.
OM (Erasable Programmable Read Only Memory),
OTPROM (One Time Programmable Read Only Memo
ry) etc. are used. This has a device structure in which, in addition to holding data semi-permanently, the data cannot be electrically rewritten. On the other hand, a memory that temporarily holds data needs to be capable of electrically rewriting data for the purpose of use. A typical example is a volatile memory that can be read and written at any time, such as SRAM.
(Static Random Access Memory) and DRAM (Dynamic
RAM (Random Acce) such as Random Access Memory
ss Memory) and the like. However, since the RAM is a volatile memory, it is necessary to supply power to hold the data. As an intermediate position between these, EEPROM is used as a non-volatile memory that can electrically rewrite data and can retain data for a long period of time without supplying power.
(Electrically Erasable Programmable Read Only Mem
ory) etc. In a mobile phone or the like, data set by the user such as registration of abbreviated dial or data that must be stored while being sequentially changed is generated. Since some of these data must be retained even after the power of the device is turned off, it is necessary to retain them until the data is updated. The following two methods (1) and (2) are often used as this type of data holding method.

(1) EEP which is an electrically erasable ROM
A method of using a device, such as a ROM, which is electrically rewritable and can retain data for a long period of time without requiring power supply. (2) Like SRAM, it is electrically rewritable, but it requires power supply to hold data, so a power supply for holding data (using a battery etc.) separate from the main power supply for holding data How to install. In the method of (2),
Since the data cannot be guaranteed when the power for holding (for backup) is turned off, the method (1) is generally adopted. Further, a portable device usually uses a battery as a power source of the device, and many of the batteries have a structure that can be easily replaced. In such a device, a momentary power interruption (or interruption) of the power source easily occurs, and countermeasures against it are also important. Next, referring to FIG. 2, EE
The characteristics of the PROM will be described.

FIG. 2 is a diagram showing a write cycle of a conventional EEPROM. This figure shows Hitachi's EE
The PROM (model number HN58V257) is described in the Hitachi Memory Data Book. When rewriting the data of the EEPROM, as shown in FIG. 2, the following two cycles T1 and T2 can be considered separately. T1: CPU write cycle Considering the case of writing data from the CPU, the CPU
Outputs data and address to EEPROM,
The chip select signal CS and the write enable signal WE are changed from "1" to "0" level. Then, after a lapse of a prescribed time, the CPU returns the chip select signal CS and the write enable signal WE to the "1" level, thereby completing the data transfer of 1 byte. Data can be continuously transferred up to 64 bytes. T2: Internal write cycle After the CPU write cycle T1, the chip select signal CS or write enable signal WE is set to 10
When the level is kept at "1" for 0 μsec, the EEPROM automatically shifts to the internal write operation. The rewriting time is about 15 msec, and during this period, writing from the CPU to the EEPROM and normal reading cannot be performed. The end of the internal write operation is determined by the ready / busy (RDY) of the EEPROM.
/ BUSY) pin. In addition, the EEPRO
M has a reset (RES) pin. Therefore, in order to prevent malfunctions when the power supply voltage goes out of the operating range at the time of turning on / off the power to the EEPROM, etc., when the input of the reset (RES) pin is at “0” level,
The internal write operation is prohibited. Normally, a voltage drop detection signal (internal reset signal) connected to a CPU or the like is connected. It should be noted here that if the EEPROM is powered off during the internal write cycle T2, not only the data to be written is lost, but also the already held data is destroyed. In addition, reset (RE
The same thing may occur when the input of the S) pin becomes active (“0” level).

FIG. 3 is a block diagram showing a configuration example of a data holding circuit using a conventional SRAM, and FIG. 4 is a conventional E circuit.
3 is a block diagram showing a configuration example of a data holding circuit using an EPROM. FIG. These examples are typical when SRAM and EEPROM are used as the peripheral memory of the CPU, and the power supply voltage Vcc of the device is supplied to the circuit as the power supply voltage V1 through the regulator in order to stabilize the circuit power supply. are doing. Further, in FIGS. 3 and 4, signal lines unrelated to the technique of the present invention are omitted. The data holding circuit of FIG. 3 is a circuit in the case where the data to be held is written into the SRAM from the CPU or its peripheral circuits. The data holding circuit includes a power supply regulator 1 that stabilizes the power supply voltage Vcc of the device and outputs a constant power supply voltage V1, a CPU that controls access to a memory and its peripheral circuit (hereinafter, simply referred to as CPU) 2, and , And the SRAM 4 is connected to the CPU 2 via the bus 3. To the output side of the power supply regulator 1, a voltage drop detector 5 and a power supply switching control circuit 7 to which a small battery 6 is connected are connected. The power supply switching control circuit 7 is composed of two to three transistors and two diodes.
The chip select signal CSRAM output from CPU2 is
A chip select signal CSRAMa is supplied to the SRAM 4 via the chip select control circuit 8. The chip select control circuit 8 is composed of several logic gates.

Since the SRAM 4 is a volatile memory and requires a power source to hold data, a small battery 6 is generally used. When the power supply voltage Vcc of the device is present, it is stabilized by the power supply regulator 1 and is kept at a constant power supply voltage Vcc.
It becomes 1 and is supplied to the SRAM 4 via the power supply switching control circuit 7. The SRAM 4 operates at the power supply voltage V1 = V1a. When the voltage drop detector 5 detects disconnection or drop of the power supply voltage Vcc of the device, the inversion reset signal RES1 / (where / represents inversion. The same applies hereinafter) output from the voltage drop detector 5 is active. Then, the power supply voltage V1a of the battery 6 is changed to the SRAM 4 by the voltage switching control circuit 7.
Is supplied to. The chip select control circuit 8 is normally C
The chip select signal CSRAM output from PU2 is input, and it is output as it is in the form of chip select signal CSRAMa and given to SRAM4. However, when the chip select control circuit 8 detects the active state of the reset signal RES1 / output from the voltage drop detector 5, it uses the power supply voltage V1a to put the chip select terminal CS of the SRAM 4 in the non-active state (that is, Fixed to inactive state). By this control, the SRAM 4 enters the data holding state. Power supply voltage V1a for holding data
Can be lower than the power supply voltages Vcc and V1 of a normal device.

The data holding circuit of FIG. 4 is a circuit for writing data to be held in the EEPROM from the CPU. This data holding circuit is a power supply regulator 11
And a CPU (CPU and its peripheral circuits) 12 are provided, and the CPU 12 is connected to an EEPROM 14 via a bus 13. A voltage drop detector 15 is connected to the output side of the power supply regulator 11, and its output side is connected to the CPU 12 and the EEPROM 14. EEPROM14
Is composed of HN58V257 manufactured by Hitachi Ltd., for example. When writing data from the CPU 12 to the EEPROM 14, the inverted chip select signal CS
After outputting ROM / and selecting EEPROM14, bus 1
Data is written from the CPU 12 to the EEPROM 14 via the CPU 3. When the power supply voltage V1 output from the power supply regulator 11 is equal to or lower than a certain voltage when the power is turned on or off, the voltage drop detector 15 detects it.
Inverted reset signal output from the voltage drop detector 15
RES1 / becomes active and the CPU 12 is reset. Also, this reset signal RES1 / is the EEPROM
Since it is given to the inverting reset terminal (inverting reset pin) RES / of 14, it is possible to prevent erroneous operations such as erroneous rewriting at power-on / power-off. The data holding circuit of FIG. 4 is
The circuit configuration is very simple as compared with the data holding circuit using the SRAM in FIG. Therefore, the circuit configuration of the data holding circuit of FIG. 4 is often used in a mobile phone or the like.

[0008]

However, the conventional data holding circuits of FIGS. 3 and 4 have the following problems (a) and (b), and it is difficult to solve them. (A) The data holding circuit using the SRAM of FIG. 3 requires the small battery 6 for holding data and the power supply switching control circuit 7. Considering the case where this data holding circuit is used in, for example, a mobile phone, a small battery 6 for backup,
The power supply switching control circuit 7 composed of transistors, diodes, and the like is required, and the number of parts is increased, so that a problem remains when considering downsizing of the device. Also, considering the voltage drop of the small backup battery 6 and the life of the battery 6,
From a reliability point of view, there is a problem in retaining data only by this method. (B) In the data holding circuit using the EEPROM shown in FIG. 4, the internal write cycle T2 as shown in FIG. 2 is required due to the characteristics of the EEPROM 14, and therefore the power supply is cut off or the power supply voltage Vcc becomes equal to or lower than the operating voltage during this state. If it drops, the write data may be lost and the held data may be destroyed. The internal write cycle T2 is
Since a time of about ten and several msec is required, the held data is frequently updated, and in a device such as a mobile phone in which the power supply voltage Vcc of the device is likely to be instantaneously interrupted, the probability of failure increases. . Further, when a large amount of data is updated in the EEPROM 14, it takes a long time to rewrite all the data depending on the processing state of the CPU 12. This leads to a higher probability of loss of update data. The present invention solves the problems that the above-described conventional technology has, and even when the power to the apparatus is cut off or a momentary interruption occurs, the data already stored is not destroyed or the data to be updated is lost as much as possible. An object of the present invention is to provide a highly reliable data holding circuit that can be prevented.

[0009]

In order to solve the above-mentioned problems, a first aspect of the present invention, in a data holding circuit, operates with a memory power supply voltage, is selected by a chip select signal, and is written by a memory reset signal. Rewritable non-volatile memory that is prohibited (eg EE
PROM or the like) and a memory access unit that operates at a first power supply voltage, outputs the chip select signal to select the memory, specifies an address in the memory, and controls reading and writing of data from and to the memory. For example, the CPU and its peripheral circuits) and the first power supply voltage supplied to the memory access means are detected, and a reset signal is output when the first power supply voltage drops below a certain value. And a first voltage drop detecting means. Further, in the data holding circuit according to the first aspect of the present invention, the chip selection signal output from the memory access unit is transferred to the memory by operating at the memory power supply voltage, and the first voltage drop detection unit outputs the chip select signal. Transfer means for blocking the chip select signal when the output reset signal is input, and charge for the first power supply voltage or charge for a second power supply voltage different from the first power supply voltage to accumulate the memory power supply voltage Is output in a fixed direction to supply the memory power supply voltage to the memory and the transfer means,
A second voltage drop detecting means for detecting the voltage drop of the memory power supply voltage and outputting the memory reset signal when the memory power supply voltage drops below a certain value to prohibit writing to the memory; It is provided.

According to a second aspect of the present invention, in the data holding circuit, a non-rewritable non-rewritable non-rewritable nonvolatile memory which operates at the memory power supply voltage, is selected by the first chip select signal, and is prohibited from being written by the memory reset signal. One memory (for example, EEPROM), a second memory (for example, RAM) that operates at the power supply voltage for the memory and can be read and written at any time selected by a second chip select signal, a CPU and its peripherals And a memory access unit composed of a circuit or the like. The memory access unit operates at a first power supply voltage, and has the first and second power supply voltages.
Of the chip select signal to select the first and second memories, control the reading and writing of data from and to the first and second memories, and update the data held in the first memory. Data is written in the second memory, a data valid flag is set in the second memory, it is determined whether or not the data valid flag is set, and if "setting is present", the data is set in the second memory. The new data stored is read and transferred to the first memory, and then the data valid flag is cleared.

Further, in the data holding circuit according to the second aspect of the present invention, when the voltage drop of the first power supply voltage supplied to the memory access means is detected and the first power supply voltage drops below a certain value. A first voltage drop detecting means for outputting a reset signal and operating with the memory power supply voltage;
The first chip select signal output from the memory access unit is transferred to the first memory, and the first chip select signal is transferred to the first memory.
Transfer means for interrupting the first chip select signal when the reset signal output from the voltage drop detecting means is input, and a charge of the first power supply voltage or a charge of a second power supply voltage different from the charge. Is stored and the power supply voltage for memory is output in a fixed direction, and the power supply voltage for memory is
And a second memory, a charge accumulating means for supplying to the transfer means, a voltage drop of the memory power supply voltage, and when the memory power supply voltage drops below a certain value, the memory reset signal is output. Second voltage drop detecting means for prohibiting writing to the first memory is provided. According to a third invention, in the data holding circuit according to the first or second invention, the transfer means is constituted by a logic gate, and the charge storage means is applied with the first or second power supply voltage on the anode side. And a capacitor connected between the cathode side of the diode and the ground.

[0012]

According to the first and third aspects of the invention, since the data holding circuit is constructed as described above, when the first and second power supply voltages are applied, the memory access means is driven by the first power supply voltage. Becomes the operable state, and the first or second
The electric charge of the power supply voltage is stored in the charge storage means. The memory access means selects a memory by a chip select signal and writes or reads data to or from the memory. When a power failure or momentary power failure occurs, the memory operating state is maintained by the memory power supply voltage output from the charge storage means. When the first power supply voltage becomes a certain value or less due to power interruption or momentary power interruption, the transfer means is closed by the reset signal output from the first voltage drop detection means, and the chip select signal output from the memory access means is shut off. And not transferred to memory. When the memory power supply voltage supplied from the charge storage means drops below a certain value, writing to the memory is prohibited by the memory reset signal output from the second voltage drop detection means. As a result, it is possible to prevent the data held in the memory from being destroyed when the power is turned off or when there is an instantaneous interruption.

According to the second and third inventions, when the data held in the first memory is updated by the memory access means, new data is written in the second memory and then the data in the second memory is written. A valid flag is set to indicate that data that needs to be transferred to the first memory exists in the second memory. Then, the memory access means checks whether or not the data valid flag on the second memory is set, and when it is “set”, the data stored in the second memory is read and transferred to the first memory. After that, the data valid flag is cleared to indicate that there is no data to be transferred on the second memory. If the power supply is interrupted or the power is interrupted during the setting of the data valid flag, the memory power supply voltage output from the charge accumulating means is supplied to the first and second memories. Maintained. Therefore, the update data held in the second memory is not lost even when the power is cut off or a momentary cut occurs. Therefore, the above problem can be solved.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram of a data holding circuit showing a first embodiment of the present invention. In this configuration diagram, signal lines not related to this embodiment are omitted. This data holding circuit is a circuit used in, for example, a mobile phone, and stabilizes the power supply voltage Vcc of the device to generate a first power supply voltage (main power supply inside the device) V1 and a second power supply voltage V2 of two systems. It has a power supply regulator 21 for outputting. A CPU as a memory access unit and its peripheral circuit (hereinafter, simply referred to as CPU) 22 are connected to the power supply voltage V1 side output from the power supply regulator 21. CPU
22 is a non-volatile memory that can be rewritten via the bus 23 (for example, HN58V257T3 manufactured by Hitachi, Ltd.).
5SR EEPROM) 24 is connected. CPU
22 is an active "1" and a chip select signal CSROM
Is output to select the EEPROM 24, and the EEPROM
It has a function of controlling reading / writing (access) of M24. The EEPROM 24 has an inverted chip select signal CS
Inversion chip select terminal CS / for inputting ROMa /, Inversion reset terminal R for inputting inverted memory reset signal RES2 /
It has a power supply terminal + V for inputting ES / and a memory power supply voltage V2a. The reset terminal RES / is a terminal for prohibiting writing in order to prevent malfunction of the internal circuit due to a decrease in power supply voltage or the like.

The input side of a voltage drop detector 25, which is a first voltage drop detection means, is connected to the side of the first power supply voltage V1 output from the power supply regulator 21.
The voltage drop detector 25 detects the voltage drop of the power supply voltage V1, outputs an inverted reset signal RES1 /, and outputs the power supply voltage V1.
Is a circuit that sets the reset signal RES1 / to the "0" level when the voltage drops below a certain value. The output side of the voltage drop detector 25 is connected to the reset input terminal of the CPU 22 and is also connected to one input side of the 2-input NAND gate 26 which is the transfer means. This NAND gate 26
The other input side is connected to the chip select signal CSROM side output from the CPU 22. The chip select signal CSROM side is connected to the ground through the resistor 27 so as not to be in an undefined signal state when the CPU 22 is powered off. The NAND gate 26 operates at the memory power supply voltage V2a to operate as the inverted chip select signal CSROMa.
This circuit outputs /, and its output side is EEPROM2
4 chip select terminals CS /. On the side of the second power supply voltage V2 output from the power supply regulator 21, a charge storage means including a backflow prevention diode 28 and a large-capacity capacitor 29 is connected to store the charge of the power supply voltage V2. . The diode 28 is
The anode side is connected to the second power supply voltage V2 side of the power supply regulator 21, and the cathode side is connected to the capacitor 29.
Is connected to ground via. The cathode side of the diode 28 is connected to the power supply terminal + V of the EEPROM 24.
And a voltage drop detector 30 which is a second voltage drop detection means and is connected to the power supply terminal of the NAND gate 26.
Is connected to the input side of. The voltage drop detector 30 detects a voltage drop of the memory power supply voltage V2a output from the capacitor 29, and when the power supply voltage V2a drops below a certain value, the inverted memory reset signal RES2 / is set to EEP.
This is a circuit for outputting to the reset terminal RES / of the ROM 24.
Next, a normal write operation (1) and a write operation (2) when the power is cut off of the data holding circuit configured as described above will be described with reference to FIGS. 2 and 5. Figure 5
FIG. 3 is a diagram showing operation waveforms of respective signals in the data holding circuit of FIG. 1 when power-off of the device occurs during a CPU write cycle.

(1) Normal write operation When data is rewritten in the EEPROM 24 by the CPU 22, it is carried out by the following two cycles T1 and T2, as in the conventional case of FIG. T1: CPU write cycle When the power supply voltage Vcc of the device is applied, it is stabilized by the power supply regulator 21, and the power supply regulator 21 outputs the power supply voltages V1 and V2 of two systems. The power supply voltage V1 is supplied to the CPU 22, and the CPU 22 becomes operable. The power supply voltage V2 passes through the diode 28 in the forward direction and is EEPR as the memory power supply voltage V2a.
The power is supplied to the power supply terminal + V of the OM24, and the NAND
It is supplied to the power supply terminal of the gate 26. In the normal operating state, the power supply voltage V output from the power supply regulator 21
Since 1 and V2 are predetermined voltage values, the voltage drop detector 2
The reset signal RES1 / output from 5 becomes "1",
NAND gate 26 is open. When data is written to the EEPROM 24 by the CPU 22, the CPU 2
2 outputs data and an address to the EEPROM 24 through the bus 23, and outputs the chip select signal CSROM from "0" to "1" level (chip select signal C in FIG. 2).
At S, the level is changed from "1" to "0"), and the write enable signal WE (not shown) is changed from "1" to "0" level. The "1" level chip select signal CSROM is
It passes through the NAND gate 26 and is input to the chip select terminal CS / of the EEPROM 24 as the active "0" chip select signal CSROMa /.

After that, after a lapse of a prescribed time, the CPU 2
2 returns the chip select signal CSROM to the “0” level (“1” level in the chip select signal CS of FIG. 2) and the write enable signal WE (not shown) to the “1” level to transfer 1-byte data. Ends. Data can be continuously transferred up to 64 bytes. T2: Internal write cycle After the CPU write cycle T1, the chip select signal CSROM is kept at "0" level for about 100 μsec (see FIG. 2).
Of the chip select signal CS of "1" level) or a write enable signal (not shown) of about 10
If the "1" level is maintained for 0 μsec, the EEPROM 24
Automatically shifts to the internal write operation. The rewriting time is about 15 msec.
Writing to the ROM 24 and normal reading cannot be performed. The internal write operation is terminated by the ready / busy terminal (RDY / BU) (not shown) provided in the EEPROM 24.
It is output to the SY pin).

(2) Write operation when power is cut off As shown in FIG. 5, when the power supply voltage Vcc of the device is cut off during the CPU write cycle T1, the power supply regulator 2
Similarly, the power supply voltages V1 and V2 output from 1 are also cut off. The voltage drop detector 25 drives the reset signal RES1 / to the “0” level at the time when the drop in the power supply voltage V1 is detected. The detection level of the voltage drop detector 25 is usually
It is set near the lower limit of the operating voltage of the circuit. Reset signal
When RES1 / becomes “0”, the CPU 22 enters the reset state and stops its operation thereafter, and the NAND gate 2
6 is closed and the chip select signal CSROM is cut off. Even if the power supply voltage V2 is cut off, the memory power supply voltage V2a charged in the capacitor 29 is continuously supplied to the power supply terminal + V of the EEPROM 24 and the power supply terminal of the NAND gate 26. Immediately after the power supply is cut off, the power supply voltage V2 = V2a, and the diode 28 prevents the current from flowing into the power supply regulator 21 side. This is the memory power supply voltage V
This is because the voltage drop time of the power supply voltage V2a is extended by supplying 2a only to the minimum necessary circuit. C
The chip select signal CSROM output from PU22 is
The CPU 22 is grounded through a resistor 27 so as to prevent an indefinite signal state when the power is cut off.

When the "0" level of the reset signal RES1 / output from the voltage drop detector 25 is input to the NAND gate 26, the NAND gate 26 is closed. Therefore, the chip select signal CSROMa / output from the NAND gate 26 is always fixed at "1" level regardless of the state of the chip select signal CSROM. This operation prevents a malfunction due to a transient level change of the chip select signal CSROM, and the CPU write cycle T
1 is quickly ended, and the operation of shifting to the internal write cycle T2 is performed. About 100μsec + 15 from this point
Writing ends after msec. The capacitance value of the capacitor 29 is determined so that the voltage can be maintained for about 15 msec. Therefore, CPU2
Regarding the data transferred from 2, surely EEPRO
The operation of writing to M24 is completed. After this operation, the level of the memory power supply voltage V2a drops to enter the internal circuit protection state, and the EEPROM 24 is driven by the memory reset signal RES2 / output from the voltage drop detector 30 before the voltage falls below the operating voltage of the EEPROM 24. The write-protected state is set, and malfunction is prevented. Here, the detection level of the voltage drop detector 30 is set within the range of the operating voltage of the EEPROM 24.

As described above, the first embodiment has the following advantages. (A) When a power failure or momentary power failure occurs, E is generated by the memory power supply voltage V2a charged in the capacitor 29.
The internal write cycle T2 of the EPROM 24 is guaranteed, and then EEPR is generated by the memory reset signal RES2 /.
Since writing to the OM24 is prohibited, the EEPROM
It is possible to accurately prevent the destruction of the data already stored in 24. (B) In order to realize the above (a), a simple circuit such as the NAND gate 26, the diode 28, the capacitor 29, and the voltage drop detector 30 is added to the conventional data holding circuit. Can be converted.

Second Embodiment FIG. 6 is a block diagram of a data holding circuit showing a second embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are common to the elements. Is attached. When the CPU 22 as in the first embodiment (FIG. 1) is used, R
The AM is mounted as a memory around the CPU. For example, in the case of a mobile phone, SRAM is generally used as its RAM. Therefore, in the second embodiment, the device of the first embodiment and the SRAM are used to prevent the loss of the data to be held. In this data holding circuit, the CPU 2 that outputs the first chip select signal CSROM or the like shown in FIG.
2, a CPU 22A having a function of outputting a second chip select signal CSRAM is used, and the CPU 22A is connected to a second memory SRAM 31 in addition to the first memory EEPROM 24 via a bus 23. are doing. The CPU 22A operates at the first power supply voltage V1 and outputs the first chip select signal CSROM and the second chip select signal CSRAM to the EEPROM 24 and SRAM.
31 has a function of controlling read / write (access) of data with respect to the EEPROM 24 and the SRAM 31. Furthermore, this CPU 22A is EEPRO
When updating the data stored in M24, S
After writing to the RAM 31, a data valid flag is set in the EEPROM 24, and then it is determined whether or not the data valid flag is set.
The new data stored in M31 is read and the bus 2
It has a function of clearing the data valid flag after the data is transferred to the EEPROM 24 via No. 3. CPU22
The second chip select signal CSRAM side output from A is connected to the chip select terminal CS of the SRAM 31 and is connected to the ground through the resistor 32 so that the CPU 22A does not have an indefinite signal state when the power is cut off. Has been done. The cathode side of the diode 28 is also connected to the power supply terminal + V of the SRAM 31.
Therefore, even if the power supply voltage Vcc of the device is cut off or momentarily cuts off, the memory power supply voltage V2a charged in the capacitor 29 is applied to the SRAM 31 as well.
The data of M31 is held.

FIG. 7 is a flowchart of the operation procedure of the data holding circuit shown in FIG. 6, and the operation of the control method for preventing the loss of data to be held will be described with reference to this figure.
The CPU 22A normally temporarily holds the data to be held and accumulated in the EEPROM 24 on the SRAM 31.
This is because it is necessary to organize / calculate the data to be written and format conversion before the data is stored in the EEPROM 24, and it takes several msec to write to the EEPROM 24.
This is because it may be difficult to perform the write operation immediately depending on the operating state of U22A. The flow starting from the start of step 41 in FIG. 7 is a flow chart of the operation of writing data to the EEPROM 24. CPU22
When the update of the held data occurs in step 42, A changes the SRAM 31 by the chip select signal CSRAM.
Is selected, an address in the SRAM 31 is selected through the bus 23, and data is written to the selected address in step 43. When writing data to the SRAM 31, calculations such as data rearrangement and change to a format for holding in the EEPROM 24 are also performed, and SRA is performed later.
When the data is transferred from the M31 to the EEPROM 24, the data is not processed and only the transfer work can be performed. In step 44, all necessary data is S
When the data is written in the RAM 31, the CPU 22A executes step 4
In step 5, the data valid flag DFL is set on the SRAM 31 to indicate that the data that needs to be transferred to the EEPROM 24 exists on the SRAM 31. The data valid flag DFL is, for example, a bit pattern of several bits or several bytes. The content of the data valid flag DFL is not particularly defined here, but it is desirable to use a method of reducing such a probability so that a malfunction does not occur due to coincidence of patterns by accident. When the power is cut off before the data valid flag DFL is set on the SRAM 31, the device cannot receive the data, and the data is naturally lost. Therefore, when it is necessary to return the response that the data is received to the external device,
After setting the data valid flag DFL, a response of data reception is returned.

Since the CPU 22A periodically checks the data valid flag DFL at a certain timing (start step 51), after the power supply voltage Vcc is turned on in step 52, the data valid flag DFL is set to S in step 53.
It is checked whether or not it is set in the RAM 31.
If it is confirmed that the data valid flag DFL is valid, the CPU 22A proceeds to step S54 to execute SRA.
Data is read from the specified address of M31 (address where data is stored) and the chip select signal CSRO is read.
Data is transferred to the EEPROM 24 selected by M and CSROMa /. When all the transfers in step 55 are completed, the CP
The U22A clears the data valid flag DFL in step 56 to indicate that there is no data to be transferred in the SRAM 31. In this embodiment, when the power supply is interrupted while the data valid flag DFL is valid, the capacitor 2
SRA by the memory power supply voltage V2a charged to 9
Since the M31 continues to operate, it is possible to prevent the data held in the SRAM 31 from being lost. The capacity value of the capacitor 29 determines how long the data held in the SRAM 31 is valid until the power is cut off to prevent data loss. Therefore, although the capacitor 29 having the largest capacity has not been mounted, if the capacity value of the capacitor 29 is appropriately determined in consideration of the specifications and application of the mobile phone provided with the data holding circuit of this embodiment. Good. EEPROM 24
After updating the data for the EEPROM
When reading the data held in 24, the CPU 2
2A may read the data directly from the EEPROM 24, or may transfer the data read from the EEPROM 24 to the SRAM 31 and then read the data from the SRAM 31.

As described above, the second embodiment has the following advantages (i) and (ii) in addition to the advantages substantially similar to those of the first embodiment. (I) As a peripheral memory of the CPU 22A, for example, SRA
When the M31 is used, the update data of the EEPROM 24 is held in the SRAM 31 in advance, and then the held data is transferred to the EEPROM 24.
It is possible to prevent the loss of updated data when a power failure occurs. In this embodiment, for example, it was confirmed that the capacitor 29 has a capacity of 0.03 F and can be backed up for 1 hour or more. (Ii) The EEPROM 24 used in FIG.
Since the page rewrite mode function capable of continuously writing up to 4 bytes is installed, it is possible to reduce the transfer time from the SRAM 31 to the EEPROM 24. Therefore, the speed of updating the data in the EEPROM 24 can be expected to increase. The present invention is not limited to the above embodiment, and various modifications can be made. For example, there are the following modifications (1) to (6).

(1) In FIGS. 1 and 6, the power supply voltage Vcc of the apparatus is stabilized by the power supply regulator 21 and the two power supply voltages V1 and V2 are output. In practice, for example, since the voltage values of the power supply voltages V1 and V2 are set to be the same, it is not necessary to divide the power supply voltages V1 and V2 into two systems. (2) In FIGS. 1 and 6, access control is performed using the CPUs 22 and 22A, but other memory access means may be used. For example, instead of the CPU 22A in FIG. 6, a direct memory access controller (DMA)
Alternatively, the above-described embodiment can be realized by using a memory access circuit or the like configured by hardware. (3) Although HN58V257T35SR manufactured by Hitachi Ltd. is used as the EEPROM 24 in FIGS. 1 and 6, other types of EEPROM may be used. Further, other rewritable nonvolatile memory may be used instead of these EEPROMs. In addition, E of FIG.
SRAM for data backup of EPROM 24
Although 31 is used, other readable / writable memories such as DRAM may be used. (4) In FIGS. 1 and 6, the chip select signal CS
Although the ROM is transferred to the EEPROM 24 by the NAND gate 26, other logic gates such as a NOR gate and a NAND gate may be used, or another transfer means composed of a transistor or the like may be used. (5) The charge storage means for memory backup is composed of the diode 28 and the capacitor 29, but charge storage means of other circuit configuration may be used. (6) In the above embodiment, the data holding circuit provided in the mobile phone has been described, but the data holding circuit used in the above embodiment can be mounted in a device other than the mobile phone.

[0026]

As described in detail above, according to the first aspect of the present invention, since the power storage means is provided, the charge storage means maintains the operating state of the memory when the power supply is interrupted or momentary interruption occurs. it can. When the memory power supply voltage output from the charge storage means drops below a certain value, the second voltage drop detection means prohibits writing to the memory. Therefore, when a power failure or momentary power failure occurs, it is possible to accurately prevent the destruction of the data already held in the memory. Moreover, in the conventional data holding circuit,
Since the destruction of data can be prevented only by adding a simple circuit configuration such as the transfer means, the charge storage means, and the second voltage drop detection means, the circuit can be downsized. According to the second invention, in addition to the configuration of the first invention, the second memory is added and the memory is controlled by the memory access control means. Therefore, in addition to the effect of the first invention, By the second memory, it is possible to accurately prevent the update data from being lost to the first memory when the power supply is interrupted. According to the third invention, the transfer means is composed of the logic gate and the charge storage means is composed of the diode and the capacitor, so that the circuit structure can be simplified.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data holding circuit showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a write cycle of a conventional EEPROM.

FIG. 3 is a configuration block diagram of a conventional data holding circuit using SRAM.

FIG. 4 is a configuration block diagram of a conventional data holding circuit using an EEPROM.

5 is an operation waveform diagram in the data holding circuit of FIG. 1 when the power supply to the device is cut off.

FIG. 6 is a configuration diagram of a data holding circuit showing a second embodiment of the present invention.

7 is a flowchart of an operation procedure in the data holding circuit of FIG.

[Explanation of symbols]

 22, 22A CPU 24 EEPROM 25, 30 voltage drop detector 26 NAND gate 28 diode 29 capacitor 31 SRAM CSRAM, CSROM, CSROMa / chip select signal DFL data valid flag RES1 / reset signal RES2 / memory reset signal V1, V2, V2a, Vcc power supply voltage

Claims (3)

[Claims] 1. A rewritable non-volatile memory that operates at a power supply voltage for a memory, is selected by a chip select signal, and is prohibited from being written by a memory reset signal, and operates at a first power supply voltage. A memory access unit that outputs a chip select signal to select the memory, and specifies an address in the memory to control reading and writing of data from and to the memory; and a first power supply voltage supplied to the memory access unit. First voltage drop detection means for detecting a voltage drop and outputting a reset signal when the first power supply voltage drops below a certain value, and operating from the memory power supply voltage and output from the memory access means. The chip select signal is transferred to the memory, and the reset signal output from the first voltage drop detecting means is input. A transfer unit that cuts off the chip select signal when input, and a charge of the first power supply voltage or a charge of a second power supply voltage different from the first charge voltage is accumulated to output the memory power supply voltage in a fixed direction, A charge storage unit that supplies the memory power supply voltage to the memory and the transfer unit; and a memory reset signal when the memory power supply voltage drops below a certain value by detecting a voltage drop of the memory power supply voltage. Data holding means for outputting and prohibiting writing to the memory. 2. A rewritable non-volatile first memory which operates at a memory power supply voltage, is selected by a first chip select signal, and is write-protected by a memory reset signal, and the memory power supply. A second memory that operates at a voltage and is readable and writable at any time selected by a second chip select signal; and a first memory that operates at a first power supply voltage and outputs the first and second chip select signals. When selecting the first and second memories, controlling the reading and writing of data from and to the first and second memories, and updating the data held in the first memory, write new data to the second memory. After that, the data valid flag is set in the second memory, the presence or absence of the setting of the data valid flag is judged, and when the setting is "present", the new data stored in the second memory is stored. Memory access means for clearing the data valid flag after reading the appropriate data and transferring it to the first memory; and a first power supply for detecting a voltage drop of the first power supply voltage supplied to the memory access means. First voltage drop detection means for outputting a reset signal when the voltage drops below a certain value, and the first chip select signal output from the memory access means for operating with the memory power supply voltage. Transfer means for transferring to the first memory, shutting off the first chip select signal when the reset signal output from the first voltage drop detecting means is input, and charge of the first power supply voltage or An electric charge of a second power supply voltage different from that is accumulated and the memory power supply voltage is output in a fixed direction, and the memory power supply voltage is supplied to the first and second memories. Charge storage means for supplying to the transfer means, and detecting the voltage drop of the memory power supply voltage and outputting the memory reset signal to write the first memory when the memory power supply voltage drops below a certain value. And a second voltage drop detecting means for prohibiting the data holding means. 3. The data holding circuit according to claim 1, wherein the transfer unit is composed of a logic gate, and the charge storage unit is applied with the first or second power supply voltage on an anode side. A data holding circuit comprising a reverse current preventing diode and a capacitor connected between the cathode side of the diode and the ground.