CN111273864A - Method and system for reducing NAND FLASH erasing times - Google Patents

Method and system for reducing NAND FLASH erasing times Download PDF

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CN111273864A
CN111273864A CN202010053933.2A CN202010053933A CN111273864A CN 111273864 A CN111273864 A CN 111273864A CN 202010053933 A CN202010053933 A CN 202010053933A CN 111273864 A CN111273864 A CN 111273864A
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configuration data
power supply
external power
nand flash
data block
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CN111273864B (en
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张瑞金
刘强
孙志正
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Shandong Inspur Scientific Research Institute Co Ltd
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Jinan Inspur Hi Tech Investment and Development Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The application discloses a method and a system for reducing erasing times of a NAND flash memory NAND FLASH, which can obtain the working state of an external power supply of electronic equipment; determining whether the configuration data in the temporary storage medium of the electronic device is consistent with the configuration data in NAND FLASH of the electronic device when the working state of the external power supply is a power-off state; in the case that the configuration data in the temporary storage medium is not consistent with the configuration data in the NAND FLASH, the master control module writes the configuration data in the temporary storage medium to the NAND FLASH. Based on the technical scheme, the erasing times of the NANDFLASH can be reasonably reduced, and the service life of the electronic equipment is prolonged.

Description

Method and system for reducing NAND FLASH erasing times
Technical Field
The present application relates to the field of data storage technologies, and in particular, to a method and a system for reducing NAND FLASH erasing times.
Background
The NAND FLASH memory (NAND FLASH ) is a FLASH memory, has the advantages of large capacity and fast rewriting speed, and is suitable for storing a large amount of data, and thus, is increasingly widely used, such as embedded products including digital cameras, MPS walkman memory cards, and compact-sized U disks.
However, due to the manufacturing process, the number of erasures of NANDFLASH is limited, for example, the number of erasures of SLC NAND FLASH in the market is usually 3000-6000, the number of erasures of MLCNAND FLASH is usually only several hundreds, and bad blocks can be formed by using the number of erasures exceeding NAND FLASH in the process.
If the electronic device needs to erase NAND FLASH once after the configuration data is modified each time, frequent erasing of NANDFLASH and bad blocks are formed, so that the configuration data cannot be stored, the electronic device fails, and the service time of NAND FLASH is reduced.
Based on this, how to store the configuration data of the electronic device in NAND FLASH by way of erasing after modification, reasonably reducing the number of times of erasing of the nand flash becomes an urgent problem to be solved.
Disclosure of Invention
The embodiment of the specification provides a method and a system for reducing the erasing times of NANDFLASH, and is used for solving the problem that in the prior art, the service time of NAND FLASH is shortened due to the fact that NAND FLASH is frequently erased and written to cause a bad block.
The embodiment of the specification adopts the following technical scheme:
a method of reducing the number of erasures of a NAND flash memory NAND FLASH, the method comprising:
acquiring the working state of an external power supply of the electronic equipment;
when the working state of the external power supply is a power-off state, determining whether the configuration data in the temporary storage medium of the electronic equipment is consistent with the configuration data in the NANDFLASH of the electronic equipment;
writing the configuration data in the temporary storage medium to the NAND FLASH if the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH.
Optionally, the obtaining of the working state of the external power supply of the electronic device specifically includes:
acquiring an output voltage of an external power supply of the electronic equipment;
and determining the working state of the external power supply according to the output voltage of the external power supply.
Optionally, the writing the configuration data in the temporary storage medium into the NAND FLASH specifically includes:
writing the configuration data in the temporary storage medium into the main data block of NAND FLASH; and
and writing the configuration data in the temporary storage medium into the spare data block of NAND FLASH.
Optionally, in a case that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH, the method further includes:
updating the writing times of the NANDFLASH under the condition that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH;
and writing the updated writing times and the configuration data in the temporary storage medium into the main data block and the standby data block of the NANDFLASH.
Optionally, the method further comprises: in the process of starting up the electronic device, the main control module obtains configuration data in the main data block and the standby data block of NAND FLASH;
judging whether the configuration data in the main data block and the configuration data in the standby data block are valid or not;
comparing the number of writes in the main data block with the number of writes in the spare data block if both the configuration data in the main data block and the configuration data in the spare data block are valid;
under the condition that the writing times in the main data block are greater than the writing times in the standby data block, performing starting operation according to the configuration data in the main data block;
and under the condition that the writing times in the main data block are less than the writing times in the standby data block, carrying out starting operation according to the configuration data in the standby data block.
Optionally, the method further comprises: under the condition that the configuration data in the main data block is invalid, starting up operation is carried out according to the configuration data in the standby data block;
and under the condition that the configuration data in the standby data block is invalid, executing boot-up operation according to the configuration data in the main data block.
A system for reducing the number of erasures to a NAND flash memory NAND FLASH, the system comprising:
an external power supply;
NAND FLASH；
the main control module is respectively connected with the external power supply NAND FLASH and is used for acquiring the working state of the external power supply of the electronic equipment; and for
When the working state of the external power supply is a power-off state, determining whether the configuration data in the temporary storage medium of the electronic equipment is consistent with the configuration data in the NANDFLASH of the electronic equipment; and for
And under the condition that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH, the main control module writes the configuration data in the temporary storage medium into the NAND FLASH.
Optionally, the main control module includes: the device comprises a DC-DC chip, a power failure detection unit and a microcontroller;
one end of the DC-DC chip is connected with the anode of the external power supply, and the other end of the DC-DC chip is respectively connected with the microcontroller and the NANDFLASH and used for providing corresponding working voltage for the microcontroller and the NANDFLASH;
one end of the power-off detection unit is connected with the anode of the external power supply, and the other end of the power-off detection unit is connected with the microcontroller and is used for generating a trigger signal and sending the trigger signal to the microcontroller under the condition that the output voltage of the external power supply meets the preset condition;
the microcontroller is connected with the NANDFLASH and used for determining whether the configuration data in the temporary storage medium of the electronic device is consistent with the configuration data in the NANDFLASH of the electronic device or not under the condition that a trigger signal is received; and for
And under the condition that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH, the main control module writes the configuration data in the temporary storage medium into the NAND FLASH.
Optionally, the power outage detection unit includes: the reset circuit comprises a first resistor, a second resistor and a reset chip;
one end of the first resistor is connected with the anode of the external power supply, the other end of the first resistor is respectively connected with one end of the reset chip and one end of the second resistor, and the other end of the second resistor is connected with the cathode of the external power supply;
the other end of the reset chip is connected with the microcontroller and is used for generating a trigger signal under the condition that the output voltage of the external power supply meets a preset condition.
Optionally, the voltage of the external power supply meets a preset condition, and specifically includes:
Figure BDA0002372155550000041
and U is>uDC
Wherein U is a voltage of the external power supply, U1Is the reset voltage of the reset chip, R1Is the resistance value of the first resistor, R2Is the resistance value of the second resistor, uDCIs the working voltage of the DC-DC chip.
The embodiment of the specification adopts at least one technical scheme which can achieve the following beneficial effects: the modified updates are not immediately updated to NAND FLASH after the configuration data of the electronic device is modified, but the final configuration data can be written NAND FLASH when the electronic device is powered down. On the basis of ensuring that the configuration data is written in NAND FLASH, the erasing frequency of NAND FLASH is reasonably reduced, the service life of the electronic equipment is prolonged, and the user experience is improved
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The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a flow chart of a method for reducing NAND FLASH erase counts provided by embodiments of the present description;
fig. 2 is a flowchart of a method for detecting configuration data used when an electronic device is powered on according to an embodiment of the present disclosure;
FIG. 3 is a block diagram illustrating a system for reducing NAND FLASH erase counts according to embodiments of the present disclosure;
fig. 4 is a schematic diagram of another structure of a system for reducing NAND FLASH times of erasing according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure will be clearly and completely described below with reference to the specific embodiments of the present disclosure and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person skilled in the art without making any inventive step based on the embodiments in the description belong to the protection scope of the present application.
The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.
FIG. 1 is a flow chart of a method for reducing NAND FLASH erase counts provided by embodiments of the present description. As shown in fig. 1, the method comprises the steps of:
s101, acquiring the working state of an external power supply of the electronic equipment.
In some embodiments of the present application, the operating state of the external power supply of the electronic device may be obtained by:
acquiring output voltage of an external power supply of the electronic equipment;
and determining the working state of the external power supply according to the output voltage of the external power supply.
In the power-off process of the electronic equipment, the output voltage of the external power supply can be changed, so that the working state of the external power supply can be judged through the output voltage of the external power supply. Generally, when the output voltage of the external power supply gradually decreases, the external power supply of the electronic device is determined to be in a power-off process.
And S102, respectively acquiring configuration data in a temporary storage medium of the electronic device and configuration data in NANDFLASH of the electronic device when the working state of the external power supply is a power-off state.
The configuration data of the electronic device may be changed according to the operation of the user during the operation, and the changed configuration data may be stored in a temporary storage medium of the electronic device, for example: a random access memory. When the configuration data of the electronic device is changed again, the configuration data in the temporary storage medium may be updated to the latest configuration data.
S103, determining whether the configuration data in the temporary storage medium of the electronic device is consistent with the configuration data in the NANDFLASH of the electronic device.
And comparing the configuration data in the temporary storage medium of the electronic equipment with the configuration data in the NANDFLASH of the electronic equipment to confirm whether the configuration data and the NANDFLASH are consistent.
And S104, writing the configuration data in the temporary storage medium into the NANDFLASH under the condition that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH.
It can be understood that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH, which indicates that the configuration data in the NANDFLASH is no longer the latest configuration data, and the configuration data in the NANDFLASH needs to be updated.
Since the number of erasures of the nand flash is limited, in order to avoid writing the configuration data into the bad block of NAND FLASH, in some embodiments of the present application, the configuration data in the temporary storage medium may be written into the main data block and the spare data block of NAND FLASH in sequence.
Since data cannot be synchronously written NAND FLASH in the main data block and the spare data block, the configuration data in the temporary storage medium may be written NAND FLASH in the main data block before being written in the spare data block, or the spare data block may be written first in the main data block, which is not limited in the embodiments of the present specification.
It should be noted that NAND FLASH, the main data block and the spare data block have no substantial difference, and both are NAND FLASH data blocks, named as the main data block and the spare data block only for convenience of distinction.
In some embodiments of the present application, the writing times of the NANDFLASH may also be updated in a case where the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH;
and writing the updated writing times and the configuration data in the temporary storage medium into the main data block and the standby data block of the NANDFLASH.
Through the scheme, the erasing times of the NANDFLASH can be conveniently known, and the uneven erasing times of each data block in the NANDFLASH can be avoided.
To avoid incomplete configuration data writes or inconsistent main/spare data blocks when power is off. Therefore, as shown in fig. 2, an embodiment of the present specification further provides a method for detecting configuration data used when an electronic device is powered on:
s201, in the process of starting up the electronic device, the main control module obtains NAND FLASH configuration data in the main data block and the standby data block.
S202, judging whether the configuration data in the main data block is valid.
And under the condition that the configuration data in the main data block is invalid, performing boot-up operation according to the configuration data in the standby data block.
It should be noted that whether the configuration data is valid refers to whether the configuration data of NAND FLASH can be called to complete a boot operation when the electronic device is booted, and if the configuration data is valid, the configuration data is invalid if the configuration data is not valid.
Since the order of writing the configuration data into the main data block and the spare data block is not limited, if the configuration data is written into the spare data block first, the main data block is likely to be incomplete, and the configuration data in the main data block is invalid at this time.
S203, if the configuration data of the main data block is valid, determining whether the configuration data in the spare data block is valid.
In the case of invalid configuration data in the spare data block, performing a boot operation based on the configuration data in the main data block
S204, under the condition that the configuration data in the standby data block is valid, comparing the writing times in the main data block with the writing times in the standby data block.
And S205, under the condition that the writing times in the main data block are greater than the writing times in the standby data block, carrying out starting operation according to the configuration data in the main data block.
And S206, under the condition that the writing times in the main data block are less than the writing times in the standby data block, carrying out starting operation according to the configuration data in the standby data block.
Through the scheme, the validity of the configuration data NAND FLASH can be detected when the electronic device is powered on, and the valid and latest configuration data can be selected for power-on operation.
The method for reducing NAND FLASH erasing times provided by the embodiment of the application can not update the modified configuration data to NAND FLASH immediately after the configuration data is modified, but write the final configuration data into NAND FLASH when the electronic device is powered off. On the basis of ensuring that the configuration data are written into the NANDFLASH, the erasing times of NAND FLASH are reasonably reduced, the service life of the electronic equipment is prolonged, and the user experience is improved.
Based on the same idea, some embodiments of the present application further provide a system corresponding to the above method.
FIG. 3 is a system for reducing NAND FLASH the number of erasures provided by embodiments of the present description. As shown in fig. 3, the system includes: the external power supply 310, NAND FLASH320, and the main control module 330, one end of the main control module 330 is connected with the external power supply 310, and the other end of the main control module 330 is connected with NAND FLASH 320.
The main control module 330 is used for acquiring the working state of the external power supply 310 of the electronic device. And also for determining whether the configuration data in the temporary storage medium (not shown in the figure) of the electronic device is consistent with the configuration data in NAND FLASH320 of the electronic device, in the case where the operating state of the external power supply 310 is a power-off state. And for writing NAND FLASH320 the configuration data in the temporary storage medium to the master control module 330 in the event that the configuration data in the temporary storage medium is inconsistent with the configuration data in NAND FLASH 320.
In some embodiments of the present application, as shown in fig. 4, the main control module 310 may include: a DC-DC chip 410, a power-off detection unit 420, and a microcontroller 430.
As shown in fig. 4, one end of the DC-DC chip 410 is connected to the positive electrode of the external power source 310, and the other end of the DC-DC chip 410 is connected to the microcontroller 430 and the NANDFLASH 320, respectively. The power-off detection unit 420 has one end connected to the positive electrode of the external power supply 310 and the other end connected to the microcontroller 430. The microcontroller 430 is also connected to the NANDFLASH 420.
And the DC-DC chip 410 is used for providing corresponding working voltages for the microcontroller 430 and the NANDFLASH 320.
The power failure detection unit 420 is configured to generate a trigger signal and send the trigger signal to the microcontroller 430 when the output voltage of the external power supply 310 meets a preset condition.
The preset condition may be a condition for determining whether the external power supply 310 is in a power-off state, for example, a certain threshold is set, and the trigger signal may be generated when the output voltage of the external power supply 310 is consistent with the preset threshold.
The microcontroller 430, in case of receiving the trigger signal, determines whether the configuration data in the temporary storage medium of the electronic device is consistent with the configuration data in the NANDFLASH 320 of the electronic device; and for
In the case that the configuration data in the temporary storage medium is not consistent with the configuration data in the NANDFLASH 320, the main control module 330 writes NAND FLASH 420 the configuration data in the temporary storage medium.
With the above scheme, the power-off detection unit 420 may generate the trigger signal when the operating state of the external power supply 310 is the power-off state. The microcontroller 430 can determine the operation state of the external power source 310 to be the power-off state upon receiving the trigger signal.
In some embodiments of the present application, as shown in fig. 4, the power outage detection unit 410 includes: a first resistor 411, a second resistor 412, and a reset chip 413.
One end of the first resistor 411 is connected to the positive electrode of the external power source 310, the other end is connected to one end of the reset chip 413 and one end of the second resistor 412, and the other end of the second resistor 412 is connected to the negative electrode of the external power source 310. The other end of the reset chip 412 is connected to the microcontroller 430.
The reset chip 412 is configured to generate a trigger signal when the output voltage of the external power supply 310 meets a preset condition.
Specifically, the output voltage of the external power supply 310 meets a preset condition, specifically:
Figure BDA0002372155550000091
and U is>uDC
Where U is the output voltage of the external power supply 310, U1To reset the reset voltage, R, of the chip 4131Is the resistance value of the first resistor 411, R2Is the resistance value of the second resistor 412, uDCIs the operating voltage of the DC-DC chip 410.
It will be appreciated that the output voltage of the external power supply 310 drops to
Figure BDA0002372155550000101
In this case, the reset chip 413 may generate a trigger signal. At this time, the output voltage U of the external power supply 310 is also required to be greater than the operating voltage of the DC-DC chip 410 to ensure the normal operation of the microcontrollers 430 and NAND FLASH 320.
Through the above scheme, the operating state of the external power supply 310 can be determined.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The system and the method provided by the embodiment of the application are in one-to-one correspondence, so that the system also has the beneficial technical effects similar to the corresponding method, and the beneficial technical effects of the method are explained in detail above, so the beneficial technical effects of the system are not described again here.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, temporary storage medium (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static temporary storage media (SRAM), dynamic temporary storage media (DRAM), other types of temporary storage media (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (10)

1. A method for reducing erasure times of a NAND flash memory NAND FLASH, the method comprising:
acquiring the working state of an external power supply of the electronic equipment;
when the working state of the external power supply is a power-off state, determining whether the configuration data in the temporary storage medium of the electronic equipment is consistent with the configuration data in the NANDFLASH of the electronic equipment;
writing the configuration data in the temporary storage medium to the NAND FLASH if the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH.
2. The method according to claim 1, wherein obtaining the operating state of the external power supply of the electronic device specifically comprises:
acquiring an output voltage of an external power supply of the electronic equipment;
and determining the working state of the external power supply according to the output voltage of the external power supply.
3. The method according to claim 1, wherein writing the configuration data in the temporary storage medium to NAND FLASH specifically comprises:
writing the configuration data in the temporary storage medium into the main data block of NAND FLASH; and
and writing the configuration data in the temporary storage medium into the spare data block of NAND FLASH.
4. The method of claim 3, wherein in the event that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH, the method further comprises:
updating the writing times of the NANDFLASH under the condition that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH;
and writing the updated writing times and the configuration data in the temporary storage medium into the main data block and the standby data block of the NANDFLASH.
5. The method of claim 4, further comprising:
in the process of starting up the electronic device, the main control module obtains configuration data in the main data block and the standby data block of NAND FLASH;
judging whether the configuration data in the main data block and the configuration data in the standby data block are valid or not;
comparing the number of writes in the main data block with the number of writes in the spare data block if both the configuration data in the main data block and the configuration data in the spare data block are valid;
under the condition that the writing times in the main data block are greater than the writing times in the standby data block, performing starting operation according to the configuration data in the main data block;
and under the condition that the writing times in the main data block are less than the writing times in the standby data block, carrying out starting operation according to the configuration data in the standby data block.
6. The method of claim 5, further comprising:
under the condition that the configuration data in the main data block is invalid, starting up operation is carried out according to the configuration data in the standby data block;
and under the condition that the configuration data in the standby data block is invalid, executing boot-up operation according to the configuration data in the main data block.
7. A system for reducing the number of erasures to a NAND flash memory NAND FLASH, the system comprising:
an external power supply;
NAND FLASH；
the main control module is respectively connected with the external power supply NAND FLASH and is used for acquiring the working state of the external power supply of the electronic equipment; and for
When the working state of the external power supply is a power-off state, determining whether the configuration data in the temporary storage medium of the electronic equipment is consistent with the configuration data in the NANDFLASH of the electronic equipment; and for
And under the condition that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH, the main control module writes the configuration data in the temporary storage medium into the NAND FLASH.
8. The system of claim 7, wherein the master module comprises: the device comprises a DC-DC chip, a power failure detection unit and a microcontroller;
one end of the DC-DC chip is connected with the anode of the external power supply, and the other end of the DC-DC chip is respectively connected with the microcontroller and the NANDFLASH and used for providing corresponding working voltage for the microcontroller and the NANDFLASH;
one end of the power-off detection unit is connected with the anode of the external power supply, and the other end of the power-off detection unit is connected with the microcontroller and is used for generating a trigger signal and sending the trigger signal to the microcontroller under the condition that the output voltage of the external power supply meets the preset condition;
the microcontroller is connected with the NANDFLASH and used for determining whether the configuration data in the temporary storage medium of the electronic device is consistent with the configuration data in the NANDFLASH of the electronic device or not under the condition that a trigger signal is received; and for
And under the condition that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH, the main control module writes the configuration data in the temporary storage medium into the NAND FLASH.
9. The system of claim 8, wherein the power outage detection unit comprises: the reset circuit comprises a first resistor, a second resistor and a reset chip;
one end of the first resistor is connected with the anode of the external power supply, the other end of the first resistor is respectively connected with one end of the reset chip and one end of the second resistor, and the other end of the second resistor is connected with the cathode of the external power supply;
the other end of the reset chip is connected with the microcontroller and is used for generating a trigger signal under the condition that the output voltage of the external power supply meets a preset condition.
10. The system according to claim 9, wherein the voltage of the external power supply meets a preset condition, specifically comprising:
Figure FDA0002372155540000031
and U is>uDC
Wherein U is a voltage of the external power supply, U1Is the reset voltage of the reset chip, R1Is the resistance value of the first resistor, R2Is the resistance value of the second resistor, uDCIs the working voltage of the DC-DC chip.
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08249244A (en) * 1995-03-13 1996-09-27 Oki Electric Ind Co Ltd Data holding circuit
US20090150597A1 (en) * 2007-12-07 2009-06-11 Phison Electronics Corp. Data writing method for flash memory and controller using the same
US20100061133A1 (en) * 2008-09-05 2010-03-11 Genesys Logic, Inc. Memory module and method of performing the same
CN102939593A (en) * 2010-03-05 2013-02-20 艾菲股份有限公司 Endless memory
WO2014201865A1 (en) * 2013-06-20 2014-12-24 深圳市瑞耐斯技术有限公司 Nand flash memory device and random writing method therefor
WO2014201864A1 (en) * 2013-06-20 2014-12-24 深圳市瑞耐斯技术有限公司 Nand flash memory device and operation method therefor
CN105788637A (en) * 2015-12-24 2016-07-20 北京兆易创新科技股份有限公司 Erasing and writing recession compensation method and device for NAND FLASH
CN106598484A (en) * 2016-11-17 2017-04-26 华为技术有限公司 Data storage method, flash memory chip and storage device
CN106843959A (en) * 2017-01-18 2017-06-13 株洲变流技术国家工程研究中心有限公司 A kind of FPGA remotely updating devices and method
CN110399094A (en) * 2019-06-06 2019-11-01 浙江大华技术股份有限公司 Block processing method, device, solid state hard disk and the storage medium of solid state hard disk

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08249244A (en) * 1995-03-13 1996-09-27 Oki Electric Ind Co Ltd Data holding circuit
US20090150597A1 (en) * 2007-12-07 2009-06-11 Phison Electronics Corp. Data writing method for flash memory and controller using the same
US20100061133A1 (en) * 2008-09-05 2010-03-11 Genesys Logic, Inc. Memory module and method of performing the same
CN102939593A (en) * 2010-03-05 2013-02-20 艾菲股份有限公司 Endless memory
WO2014201865A1 (en) * 2013-06-20 2014-12-24 深圳市瑞耐斯技术有限公司 Nand flash memory device and random writing method therefor
WO2014201864A1 (en) * 2013-06-20 2014-12-24 深圳市瑞耐斯技术有限公司 Nand flash memory device and operation method therefor
CN105788637A (en) * 2015-12-24 2016-07-20 北京兆易创新科技股份有限公司 Erasing and writing recession compensation method and device for NAND FLASH
CN106598484A (en) * 2016-11-17 2017-04-26 华为技术有限公司 Data storage method, flash memory chip and storage device
CN106843959A (en) * 2017-01-18 2017-06-13 株洲变流技术国家工程研究中心有限公司 A kind of FPGA remotely updating devices and method
CN110399094A (en) * 2019-06-06 2019-11-01 浙江大华技术股份有限公司 Block processing method, device, solid state hard disk and the storage medium of solid state hard disk

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
张鹏;孙甲松;陈从华;: "基于NOR FLASH的嵌入式FAT文件系统" *
彭卓文;杨新民;王胜红;: "基于FPGA控制的高速大容量NAND FLASH存储模块设计" *

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