CN111273864B - Method and system for reducing NAND FLASH erasing times - Google Patents

Method and system for reducing NAND FLASH erasing times Download PDF

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Publication number
CN111273864B
CN111273864B CN202010053933.2A CN202010053933A CN111273864B CN 111273864 B CN111273864 B CN 111273864B CN 202010053933 A CN202010053933 A CN 202010053933A CN 111273864 B CN111273864 B CN 111273864B
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configuration data
nand flash
external power
data block
temporary storage
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CN111273864A (en
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张瑞金
刘强
孙志正
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Shandong Inspur Scientific Research Institute Co Ltd
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Shandong Inspur Scientific Research Institute Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The application discloses a method and a system for reducing the erasing times of a NAND flash memory NAND FLASH, which can acquire the working state of an external power supply of electronic equipment; determining whether configuration data in a temporary storage medium of the electronic equipment is consistent with configuration data in NAND FLASH of the electronic equipment when the working state of the external power supply is a power-off state; in the event that the configuration data in the temporary storage medium does not match the configuration data in NAND FLASH, the master module writes the configuration data in the temporary storage medium to NAND FLASH. Based on the technical scheme, the erasing times of NANDFLASH can be reasonably reduced, and the service life of the electronic equipment is prolonged.

Description

Method and system for reducing NAND FLASH erasing times
Technical Field
The present disclosure relates to the field of data storage technologies, and in particular, to a method and system for reducing NAND FLASH erasing times.
Background
The NAND FLASH memory (NAND FLASH ) is a FLASH memory, has the advantages of larger capacity, high rewriting speed and the like, and is suitable for storing a large amount of data, so that the NAND FLASH memory is widely applied to embedded products such as digital cameras, MPS walkman memory cards, small-size U discs and the like.
However, due to the manufacturing process, the number of times of erasing NANDFLASH is limited, for example, the number of times of erasing SLC NAND FLASH on the market is generally 3000-6000 times, the number of times of erasing MLCNAND FLASH is generally only hundreds, and bad blocks are formed when the number of times of erasing exceeds NAND FLASH in the process of use.
If the electronic device is to write once NAND FLASH after each modification of the configuration data, frequent writing of NAND FLASH is caused, and bad blocks are formed, so that the configuration data cannot be stored, and the electronic device is failed, thereby reducing the service time of NAND FLASH.
Based on this, how to reasonably reduce the erasing times of NANDFLASH is a problem to be solved on the basis of storing the configuration data of the electronic device in NAND FLASH in an erasing manner after the configuration data is modified.
Disclosure of Invention
The embodiment of the specification provides a method and a system for reducing NANDFLASH erasing times, which are used for solving the problem that in the prior art, NAND FLASH is frequently erased to cause bad blocks and cause NAND FLASH service time.
The embodiment of the specification adopts the following technical scheme:
a method of reducing the number of erases of a NAND flash NAND FLASH, the method comprising:
acquiring the working state of an external power supply of electronic equipment;
determining whether configuration data in a temporary storage medium of the electronic equipment is consistent with configuration data in NANDFLASH of the electronic equipment or not when the working state of the external power supply is a power-off state;
and writing the configuration data in the temporary storage medium into the NAND FLASH in the case that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH.
Optionally, acquiring the working state of the external power supply of the electronic device specifically includes:
acquiring the output voltage of an external power supply of the electronic equipment;
and determining the working state of the external power supply according to the output voltage of the external power supply.
Optionally, the writing the configuration data in the temporary storage medium into the NAND FLASH specifically includes:
writing configuration data in the temporary storage medium into the main data block of NAND FLASH; and
and writing configuration data in the temporary storage medium into the spare data blocks of NAND FLASH.
Optionally, in a case where the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH, the method further includes:
updating the write-in times of the NANDFLASH under the condition that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH;
and writing the updated writing times and configuration data in the temporary storage medium into the main data block and the standby data block of the NANDFLASH.
Optionally, the method further comprises: during the starting-up process of the electronic equipment, the main control module acquires configuration data in the main data block and the standby data block of NAND FLASH;
judging whether the configuration data in the main data block and the configuration data in the standby data block are valid or not;
comparing the number of writing in the main data block with the number of writing in the spare data block under the condition that the configuration data in the main data block and the configuration data in the spare data block are both valid;
performing starting operation according to configuration data in the main data block under the condition that the writing times in the main data block are larger than the writing times in the standby data block;
and under the condition that the writing times in the main data block are smaller than the writing times in the standby data block, starting up operation is carried out according to the configuration data in the standby data block.
Optionally, the method further comprises: under the condition that the configuration data in the main data block is invalid, starting up operation is carried out according to the configuration data in the standby data block;
and executing starting operation according to the configuration data in the main data block under the condition that the configuration data in the standby data block is invalid.
A system for reducing the number of erases of NAND flash NAND FLASH, the system comprising:
an external power source;
NAND FLASH；
the main control module is respectively connected with an external power supply and NAND FLASH and is used for acquiring the working state of the external power supply of the electronic equipment; for use in
Determining whether configuration data in a temporary storage medium of the electronic equipment is consistent with configuration data in NANDFLASH of the electronic equipment or not when the working state of the external power supply is a power-off state; for use in
And under the condition that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH, the main control module writes the configuration data in the temporary storage medium into the NAND FLASH.
Optionally, the main control module includes: a DC-DC chip, a power-off detection unit and a microcontroller;
one end of the DC-DC chip is connected with the positive electrode of the external power supply, and the other end of the DC-DC chip is respectively connected with the microcontroller and the NANDFLASH and used for providing corresponding working voltages for the microcontroller and the NANDFLASH;
one end of the power-off detection unit is connected with the positive electrode of the external power supply, and the other end of the power-off detection unit is connected with the microcontroller and is used for generating a trigger signal and sending the trigger signal to the microcontroller when the output voltage of the external power supply accords with a preset condition;
the microcontroller is connected with the NANDFLASH and is used for determining whether the configuration data in the temporary storage medium of the electronic equipment is consistent with the configuration data in the NANDFLASH of the electronic equipment or not under the condition that a trigger signal is received; for use in
And under the condition that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH, the main control module writes the configuration data in the temporary storage medium into the NAND FLASH.
Optionally, the power outage detection unit includes: the first resistor, the second resistor and the reset chip;
one end of the first resistor is connected with the positive electrode of the external power supply, the other end of the first resistor is respectively connected with one end of the reset chip and one end of the second resistor, and the other end of the second resistor is connected with the negative electrode of the external power supply;
the other end of the reset chip is connected with the microcontroller and is used for generating a trigger signal under the condition that the output voltage of the external power supply meets the preset condition.
Optionally, the voltage of the external power supply meets a preset condition, which specifically includes:
and U is>u DC
Wherein U is the voltage of the external power supply, and 1 for the reset voltage of the reset chip, R 1 A resistance value of the first resistor R 2 A resistance value of the second resistor, the u DC Is the operating voltage of the DC-DC chip.
The above-mentioned at least one technical scheme that this description embodiment adopted can reach following beneficial effect: it is possible that after the configuration data of the electronic device is modified, the modified update is not immediately updated to NAND FLASH, but the final configuration data is written into NAND FLASH when the electronic device is powered off. The method can reasonably reduce NAND FLASH erasing times, prolong the service life of the electronic equipment and improve the user experience on the basis of ensuring the writing NAND FLASH of the configuration data
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 is a flow chart of a method for reducing NAND FLASH erasure times provided in an embodiment of the present disclosure;
FIG. 2 is a flowchart of a method for detecting configuration data used when an electronic device is powered on according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a system for reducing NAND FLASH erasing times according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of another structure of a system for reducing NAND FLASH erasing times according to an embodiment of the present disclosure.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present specification more apparent, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments of the present specification and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the disclosure, are intended to be within the scope of the present application based on the embodiments described herein.
The following describes in detail the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for reducing NAND FLASH erasing times according to an embodiment of the present disclosure. As shown in fig. 1, the method comprises the steps of:
s101, acquiring the working state of an external power supply of the electronic equipment.
In some embodiments of the present application, the operating state of the external power supply of the electronic device may be obtained by:
acquiring the output voltage of an external power supply of the electronic equipment;
and determining the working state of the external power supply according to the output voltage of the external power supply.
In the power-off process of the electronic equipment, the output voltage of the external power supply can change, so that the working state of the external power supply can be judged through the output voltage of the external power supply. In general, when the output voltage of the external power supply gradually decreases, it can be determined that the external power supply of the electronic device is in a power-off process.
S102, respectively acquiring configuration data in a temporary storage medium of the electronic equipment and configuration data in NANDFLASH of the electronic equipment when the working state of the external power supply is a power-off state.
The configuration data of the electronic device may be changed according to the operation of the user during the operation, and the changed configuration data may be stored in a temporary storage medium of the electronic device, for example: a random access memory. In the case where the configuration data of the electronic device is changed again, the configuration data in the temporary storage medium may be updated to the latest configuration data.
S103, determining whether the configuration data in the temporary storage medium of the electronic device is consistent with the configuration data in NANDFLASH of the electronic device.
And comparing the configuration data in the temporary storage medium of the electronic equipment with the configuration data in NANDFLASH of the electronic equipment to confirm whether the configuration data and the configuration data are consistent.
S104, in the case where the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH, the configuration data in the temporary storage medium is written NAND FLASH.
It can be understood that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH, which means that the configuration data in the NANDFLASH is no longer the latest configuration data, and the configuration data in the NANDFLASH needs to be updated.
Because there is a limit to the number of erasures of NANDFLASH, in order to avoid writing configuration data into bad blocks of NAND FLASH, in some embodiments of the present application, configuration data in the temporary storage medium may be written into the main data block and the spare data block of NAND FLASH sequentially.
Since data cannot be written in the main data block and the spare data block of NAND FLASH simultaneously, the configuration data in the temporary storage medium may be written in the main data block of NAND FLASH before the spare data block, or the spare data block may be written in the main data block before the spare data block is written, which is not limited in the embodiment of the present specification.
Note that, the main data block and the spare data block of NAND FLASH are not substantially different, and are all NAND FLASH data blocks, and are named as main data blocks and spare data blocks only for convenience of distinction.
In some embodiments of the present application, the number of writing times of the NANDFLASH may also be updated if the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH;
and writing the updated writing times and configuration data in the temporary storage medium into the main data block and the standby data block of the NANDFLASH.
Through the scheme, the erasing times of the NANDFLASH can be conveniently known, and the uneven erasing times of each data block in the NANDFLASH are avoided.
To avoid situations where the configuration data writing is incomplete or the main data block/spare data block is inconsistent when power is off. Therefore, as shown in fig. 2, the embodiment of the present disclosure further provides a method for detecting configuration data used when the electronic device is powered on:
s201, in the starting-up process of the electronic equipment, the main control module acquires configuration data in the main data block and the standby data block of NAND FLASH.
S202, judging whether the configuration data in the main data block is valid.
And under the condition that the configuration data in the main data block is invalid, performing starting operation according to the configuration data in the standby data block.
It should be noted that whether the configuration data is valid refers to whether the configuration data of NAND FLASH can be called to complete the power-on operation when the electronic device is powered on, if the configuration data is valid, the configuration data is invalid.
Since the order in which the configuration data is written into the main data block and the spare data block is not limited, if the configuration data is written into the spare data block first, the main data block is likely to be incomplete, and the configuration data in the main data block is invalid.
S203, judging whether the configuration data in the standby data block is valid or not when the configuration data of the main data block is valid.
In the case that the configuration data in the spare data block is invalid, performing a boot operation according to the configuration data in the main data block
S204, when the configuration data in the spare data block is valid, the writing times in the main data block and the writing times in the spare data block are compared.
S205, in the case where the number of writing times in the main data block is greater than the number of writing times in the spare data block, performing a startup operation according to the configuration data in the main data block.
S206, in the case that the writing times in the main data block are smaller than the writing times in the standby data block, starting up operation is carried out according to the configuration data in the standby data block.
By the scheme, the validity of the configuration data of NAND FLASH can be detected when the electronic equipment is started, and valid and latest configuration data can be selected for starting operation.
The method for reducing NAND FLASH erasing times provided by the embodiment of the application can not update the modified configuration data to NAND FLASH immediately after the configuration data is modified, but write the final configuration data into NAND FLASH when the electronic device is powered off. On the basis of ensuring that configuration data is written into NANDFLASH, the erasing times of NAND FLASH can be reasonably reduced, the service life of the electronic equipment is prolonged, and the user experience is improved.
Based on the same thought, some embodiments of the present application further provide a system corresponding to the above method.
Fig. 3 is a system for reducing NAND FLASH erasure times provided in an embodiment of the present disclosure. As shown in fig. 3, the system includes: external power supply 310, NAND FLASH320, main control module 330 one end links to each other with external power supply 310, and main control module 330's the other end links to each other with NAND FLASH 320.
The main control module 330 is configured to obtain an operating state of the external power supply 310 of the electronic device. And is further configured to determine whether configuration data in a temporary storage medium (not shown) of the electronic device is consistent with configuration data in NAND FLASH320 of the electronic device when the operating state of the external power supply 310 is a power-off state. And for writing NAND FLASH the configuration data in the temporary storage medium to the host module 330 in case the configuration data in the temporary storage medium is inconsistent with the configuration data in NAND FLASH and 320.
In some embodiments of the present application, as shown in fig. 4, the main control module 310 may include: a DC-DC chip 410, a power-off detection unit 420, and a microcontroller 430.
As shown in fig. 4, one end of the DC-DC chip 410 is connected to the positive electrode of the external power supply 310, and the other end of the DC-DC chip 410 is connected to the microcontroller 430 and the NANDFLASH 320, respectively. One end of the power-off detection unit 420 is connected to the positive electrode of the external power source 310, and the other end is connected to the microcontroller 430. Microcontroller 430 is also coupled to NANDFLASH 420.
The DC-DC chip 410 is configured to provide corresponding operating voltages for the microcontroller 430 and the NANDFLASH 320.
The power-off detection unit 420 is configured to generate a trigger signal and send the trigger signal to the microcontroller 430 when the output voltage of the external power supply 310 meets a preset condition.
The preset condition may be a condition for determining whether the external power source 310 is in a power-off state, for example, a certain threshold is set, and if the output voltage of the external power source 310 is consistent with the preset threshold, the trigger signal may be generated.
The microcontroller 430 determines whether configuration data in a temporary storage medium of the electronic device is consistent with configuration data in the NANDFLASH 320 of the electronic device when receiving the trigger signal; for use in
In the case where the configuration data in the temporary storage medium is inconsistent with the configuration data in the NANDFLASH 320, the main control module 330 writes NAND FLASH the configuration data in the temporary storage medium.
Through the above scheme, the power-off detection unit 420 may generate the trigger signal when the operating state of the external power source 310 is the power-off state. The microcontroller 430 can determine that the operating state of the external power supply 310 is a power-off state upon receiving the trigger signal.
In some embodiments of the present application, as shown in fig. 4, the power-off detection unit 410 includes: a first resistor 411, a second resistor 412, and a reset chip 413.
One end of the first resistor 411 is connected to the positive electrode of the external power source 310, the other end is connected to one end of the reset chip 413 and one end of the second resistor 412, and the other end of the second resistor 412 is connected to the negative electrode of the external power source 310. The other end of the reset chip 412 is connected to the microcontroller 430.
The reset chip 412 is configured to generate a trigger signal when the output voltage of the external power supply 310 meets a preset condition.
Specifically, the output voltage of the external power supply 310 meets the preset condition, specifically:
and U is>u DC
Where U is the output voltage of the external power supply 310, U 1 To reset the reset voltage of chip 413, R 1 A resistance value of the first resistor 411, R 2 A resistance value of the second resistor 412, u DC Is the operating voltage of the DC-DC chip 410.
It will be appreciated that the output voltage at the external power supply 310 drops toIn the case of (a), the reset chip 413 may generate a trigger signal. At this time, the output voltage U of the external power supply 310 is required to be greater than the operating voltage of the DC-DC chip 410 to ensure the normal operation of the microcontrollers 430 and NAND FLASH 320.
Through the above scheme, the operation state of the external power source 310 can be determined.
All embodiments in the application are described in a progressive manner, and identical and similar parts of all embodiments are mutually referred, so that each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The systems and the methods provided in the embodiments of the present application are in one-to-one correspondence, so that the systems also have similar beneficial technical effects as the corresponding methods, and since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the systems are not described here again.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include non-volatile memory in a computer-readable medium, temporary storage medium (RAM) and/or non-volatile memory, etc., such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static temporary storage media (SRAM), dynamic temporary storage media (DRAM), other types of temporary storage media (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, read only optical disk read only memory (CD-ROM), digital Versatile Disks (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission media, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.

Claims (5)

1. A method of reducing the number of erases of a NAND flash NAND FLASH, the method comprising:
acquiring the working state of an external power supply of electronic equipment;
determining whether configuration data in a temporary storage medium of the electronic equipment is consistent with configuration data in NAND FLASH of the electronic equipment when the working state of the external power supply is a power-off state;
writing the configuration data in the temporary storage medium to the NAND FLASH in the event that the configuration data in the temporary storage medium is inconsistent with the configuration data in the NAND FLASH;
the writing the configuration data in the temporary storage medium into the NAND FLASH specifically includes:
writing configuration data in the temporary storage medium into the main data block of NAND FLASH; and
writing configuration data in the temporary storage medium into the spare data blocks of NAND FLASH;
in the event that the configuration data in the temporary storage medium does not correspond to the configuration data in NAND FLASH, the method further comprises:
updating the number of writes of the NAND FLASH in the event that the configuration data in the temporary storage medium does not agree with the configuration data in the NAND FLASH;
writing the updated writing times and configuration data in a temporary storage medium into the main data block and the standby data block of NAND FLASH;
the method further comprises the steps of:
during the starting-up process of the electronic equipment, the main control module acquires configuration data in the main data block and the standby data block of NAND FLASH;
judging whether the configuration data in the main data block and the configuration data in the standby data block are valid or not;
comparing the number of writing in the main data block with the number of writing in the spare data block under the condition that the configuration data in the main data block and the configuration data in the spare data block are both valid;
performing starting operation according to configuration data in the main data block under the condition that the writing times in the main data block are larger than the writing times in the standby data block;
and under the condition that the writing times in the main data block are smaller than the writing times in the standby data block, starting up operation is carried out according to the configuration data in the standby data block.
2. The method of claim 1, wherein obtaining the operating state of the external power source of the electronic device specifically comprises:
acquiring the output voltage of an external power supply of the electronic equipment;
and determining the working state of the external power supply according to the output voltage of the external power supply.
3. The method according to claim 1, wherein the method further comprises:
under the condition that the configuration data in the main data block is invalid, starting up operation is carried out according to the configuration data in the standby data block;
and executing starting operation according to the configuration data in the main data block under the condition that the configuration data in the standby data block is invalid.
4. A system for reducing the number of erases of NAND flash NAND FLASH, the system comprising:
an external power source;
NAND FLASH；
the main control module is respectively connected with an external power supply and NAND FLASH and is used for acquiring the working state of the external power supply of the electronic equipment; for use in
Determining whether configuration data in a temporary storage medium of the electronic equipment is consistent with configuration data in NAND FLASH of the electronic equipment when the working state of the external power supply is a power-off state; for use in
In the case that the configuration data in the temporary storage medium is inconsistent with the configuration data in NAND FLASH, the master control module writes the configuration data in the temporary storage medium into NAND FLASH;
the main control module comprises: a DC-DC chip, a power-off detection unit and a microcontroller;
one end of the DC-DC chip is connected with the positive electrode of the external power supply, and the other end of the DC-DC chip is respectively connected with the microcontroller and the NAND FLASH and is used for providing corresponding working voltages for the microcontroller and the NAND FLASH;
one end of the power-off detection unit is connected with the positive electrode of the external power supply, and the other end of the power-off detection unit is connected with the microcontroller and is used for generating a trigger signal and sending the trigger signal to the microcontroller when the output voltage of the external power supply accords with a preset condition;
the microcontroller is connected with the NAND FLASH and is used for determining whether the configuration data in the temporary storage medium of the electronic device is consistent with the configuration data in NAND FLASH of the electronic device or not under the condition that a trigger signal is received; for use in
In the case that the configuration data in the temporary storage medium is inconsistent with the configuration data in NAND FLASH, the master control module writes the configuration data in the temporary storage medium into NAND FLASH;
the power outage detection unit includes: the first resistor, the second resistor and the reset chip;
one end of the first resistor is connected with the positive electrode of the external power supply, the other end of the first resistor is respectively connected with one end of the reset chip and one end of the second resistor, and the other end of the second resistor is connected with the negative electrode of the external power supply;
the other end of the reset chip is connected with the microcontroller and is used for generating a trigger signal under the condition that the output voltage of the external power supply meets the preset condition.
5. The system of claim 4, wherein the voltage of the external power source meets a preset condition, specifically comprising:
and U is>u Dc
Wherein U is the voltage of the external power supply, and 1 for the reset voltage of the reset chip, R 1 A resistance value of the first resistor R 2 A resistance value of the second resistor, the u DC Is the operating voltage of the DC-DC chip.
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