CN112433959A - Method and device for realizing data storage processing, computer storage medium and terminal - Google Patents

Method and device for realizing data storage processing, computer storage medium and terminal Download PDF

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Publication number
CN112433959A
CN112433959A CN202011328864.8A CN202011328864A CN112433959A CN 112433959 A CN112433959 A CN 112433959A CN 202011328864 A CN202011328864 A CN 202011328864A CN 112433959 A CN112433959 A CN 112433959A
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page
data
storage
power failure
abnormal power
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张明
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Hefei Datang Storage Technology Co ltd
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Hefei Datang Storage Technology Co ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877Cache access modes
    • G06F12/0882Page mode
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893Caches characterised by their organisation or structure
    • G06F12/0895Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16Protection against loss of memory contents

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The embodiment of the invention takes a storage page written with data in a block written with data at the time of abnormal power failure of a NAND gate (Nand) flash memory as a reference page, and performs data storage processing on the storage page affected by the abnormal power failure after determining the storage page affected by the abnormal power failure, thereby reducing the influence of the abnormal power failure on data storage.

Description

Method and device for realizing data storage processing, computer storage medium and terminal
Technical Field
The present disclosure relates to, but not limited to, data storage technologies, and in particular, to a method, an apparatus, a computer storage medium, and a terminal for implementing data storage processing.
Background
Nand (Nand) Flash (Flash) storage is a Floating Gate (Floating Gate) -based storage technology, a Floating Gate is arranged between a Gate (control Gate) and a drain, and Nand Flash can perform erase (erase) discharge and compile (program) charging actions; data is stored in Nand Flash in the form of electric charge, and the gate and the main board are insulated by using an oxide film, so that the electric charge can be kept for a long time, and data storage can still be performed without a power supply.
When a block (block) in Nand Flash performs a write operation, if abnormal power failure occurs, the block becomes extremely unstable, and a memory page (page) written before the abnormal power failure and data compiled and written in a subsequent memory page are easy to have the problem of Error Checking and Correcting (ECC) failure (Fail) during reading, so that data loss is caused; in the related art, when ECC Fail occurs, a reread (Retry Read) operation is carried out, but ECC Fail still occurs, and the user is influenced to use Nand Flash for data storage. In order to avoid the influence of abnormal power failure on data storage, some technicians perform writing stopping operation on a block in abnormal power failure, and although data loss caused by writing data in a subsequent storage page can be avoided, the application of storage resources is influenced.
How to reduce the influence of abnormal power failure on data storage becomes a problem to be solved.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the invention provides a method and a device for realizing data storage processing, a computer storage medium and a terminal, which can reduce the influence of abnormal power failure on data storage.
The embodiment of the invention provides a method for realizing data storage processing, which comprises the following steps:
when the Nand flash memory is electrified again after abnormal power failure, determining a storage page of the last written data in a block in which data is written at the time of the abnormal power failure;
determining a storage page affected by abnormal power failure by taking the determined storage page of the last written data as a reference page;
and performing data storage processing on the determined storage page affected by the abnormal power failure.
In an exemplary instance, before determining the storage page to which the data is written last in the block to which the data is written at the time of power failure, the method further includes:
and determining a block in which the data is written at the abnormal power failure moment according to the running log information of the application loaded with the Nand flash memory.
In one illustrative example, the determining the memory pages affected by the abnormal power loss comprises:
determining the reference page and a first preset numerical value page storage page before the reference page as a first storage page which is subjected to abnormal power failure and has written data; and/or the presence of a gas in the gas,
and determining a second preset numerical value page storage page behind the reference page as a second storage page which is not written with data and is affected by abnormal power failure.
In one illustrative example, the first memory page comprises:
all memory pages in the bit line where the reference page is located.
In an exemplary instance, the performing data storage processing on the determined storage pages affected by the power failure includes:
when the storage page affected by the abnormal power failure comprises the first storage page, migrating the data in the first storage page to the storage page not affected by the power failure;
and when the memory page affected by the abnormal power failure comprises the second memory page, writing preset invalid data into the second memory page.
In an exemplary instance, when the memory page affected by the abnormal power failure includes the first memory page and the second memory page, the performing data storage processing on the determined memory page affected by the power failure includes:
caching the data in the first storage page in a preset cache region;
writing preset invalid data in the second storage page;
writing the data in the first memory page of the cache after writing the second memory page of invalid data.
On the other hand, the embodiment of the present invention further provides a computer storage medium, in which a computer program is stored, and the computer program, when executed by a processor, implements the method for implementing data storage processing.
In another aspect, an embodiment of the present invention further provides a terminal, including: a memory and a processor, the memory having a computer program stored therein; wherein the content of the first and second substances,
the processor is configured to execute the computer program in the memory;
the computer program, when executed by the processor, implements a method of implementing data storage processing as described above.
In another aspect, an embodiment of the present invention further provides an apparatus for implementing data storage processing, where the apparatus includes: a first determining unit, a second determining unit and a processing unit; wherein the content of the first and second substances,
the first determination unit is configured to: when the Nand flash memory is electrified again after abnormal power failure, determining a storage page of the last written data in a block in which data is written at the time of the abnormal power failure;
the second determination unit is configured to: determining a storage page affected by abnormal power failure by taking the determined storage page of the last written data as a reference page;
the processing unit is configured to: and performing data storage processing on the determined storage page affected by the abnormal power failure.
In an exemplary instance, the second determining unit is configured to:
determining the reference page and a first preset numerical value page storage page before the reference page as a first storage page which is subjected to abnormal power failure and has written data; and/or the presence of a gas in the gas,
and determining a second preset numerical value page storage page behind the reference page as a second storage page which is not written with data and is affected by abnormal power failure.
According to the embodiment of the invention, the storage page of the last written data in the block in which the data are written at the abnormal power failure moment of the Nand flash memory is used as the reference page, and after the storage page affected by the abnormal power failure is determined, the data storage processing is carried out on the storage page affected by the abnormal power failure, so that the influence of the abnormal power failure on the data storage is reduced.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a flow chart of a method for implementing data storage processing according to an embodiment of the present invention;
fig. 2 is a block diagram of an apparatus for implementing data storage processing according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
Fig. 1 is a flowchart of a method for implementing data storage processing according to an embodiment of the present invention, as shown in fig. 1, including:
step 101, when a Nand gate (Nand) Flash memory (Flash) is electrified again after abnormal power failure, determining a storage page of data written in a block at the time of the abnormal power failure, wherein the data is written in the block at the last time;
in an exemplary embodiment, step 101 of the present invention further includes: and determining a block in which data is written at the time of abnormal power failure according to the running log information of the application loaded with the Nand flash memory.
In an exemplary embodiment, whether a Nand flash memory is abnormally powered down or not can be determined by the running log information of an application which can load the Nand flash memory;
it should be noted that the block for obtaining the operation log information, determining the abnormal power failure according to the operation log information, and determining the data write-in at the time of the abnormal power failure from the operation log information may be implemented with reference to the related art, and is not described herein again. After the block in which the data is written at the time of abnormal power failure is determined, when power can be supplied again, the storage page in which the data is written at last is determined according to the parameters for recovering the data in the block.
Step 102, determining a storage page affected by abnormal power failure by taking the determined storage page of the last written data as a reference page;
in one illustrative example, determining a memory page affected by an abnormal power loss according to an embodiment of the present invention includes:
determining a reference page and a first preset numerical value page storage page before the reference page as a first storage page which is subjected to abnormal power failure and has written data; and/or the presence of a gas in the gas,
and determining a second preset numerical value page storage page behind the reference page as a second storage page which is not written with data and is affected by abnormal power failure.
The memory page affected by the abnormal power failure in the embodiment of the present invention may include the first memory page, the second memory page, or both the first memory page and the second memory page.
In one illustrative example, a first memory page in an embodiment of the invention includes:
all memory pages in the bit line where the reference page is located.
In an exemplary embodiment, the second predetermined value according to the embodiment of the present invention may be a value determined by experiment, which is a number greater than 36 but less than 208; for example, about 100.
And 103, performing data storage processing on the determined storage page affected by the abnormal power failure.
In one illustrative example, the data storage processing is performed on the determined storage pages affected by the power failure, and comprises the following steps:
when the storage page affected by the abnormal power failure comprises a first storage page, transferring data in the first storage page to the storage page not affected by the power failure;
and when the storage pages affected by the abnormal power failure comprise the second storage page, writing preset invalid data into the second storage page.
In one illustrative example, the invalid data may include: the marked invalid data is identified by a preset, for example, the invalid data is identified by metadata (meta-data).
In an exemplary embodiment, when the memory page affected by the abnormal power failure includes a first memory page and a second memory page, performing data storage processing on the determined memory page affected by the power failure includes:
caching data in a first storage page in a preset cache region;
writing preset invalid data in a second storage page;
after writing the second memory page of invalid data, the data in the first memory page of the cache is written.
In an exemplary embodiment, a cache region according to an embodiment of the present invention may include: a predetermined memory area in a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM).
In the block in the Nand flash memory, if data writing is already performed in the first memory page, data writing is not allowed to be performed again, and data writing is to be performed using a memory page subsequent to the second memory page, the second memory page is not allowed to be free. In order to avoid the influence of abnormal power failure on the written data and utilize the storage resources in the Nand flash memory to the maximum extent, the embodiment of the invention writes invalid data in the second storage page and embeds the data in the first storage page into the second storage page, thereby reducing the influence of abnormal power failure on data storage.
According to the embodiment of the invention, the storage page of the last written data in the block in which the data are written at the abnormal power failure moment of the Nand flash memory is used as the reference page, and after the storage page affected by the abnormal power failure is determined, the data storage processing is carried out on the storage page affected by the abnormal power failure, so that the influence of the abnormal power failure on the data storage is reduced.
The embodiment of the invention also provides a computer storage medium, wherein a computer program is stored in the computer storage medium, and when being executed by a processor, the computer program realizes the method for realizing the data storage processing.
An embodiment of the present invention further provides a terminal, including: a memory and a processor, the memory having stored therein a computer program; wherein the content of the first and second substances,
the processor is configured to execute the computer program in the memory;
the computer program, when executed by a processor, implements a method of implementing data storage processing as described above.
Fig. 2 is a block diagram of an apparatus for implementing data storage processing according to an embodiment of the present invention, as shown in fig. 2, including: a first determining unit, a second determining unit and a processing unit; wherein the content of the first and second substances,
the first determination unit is configured to: when the Nand Flash is electrified again after abnormal power failure, determining a storage page of the last written data in a block in which data is written at the time of the abnormal power failure;
the second determination unit is configured to: determining a storage page affected by abnormal power failure by taking the determined storage page of the last written data as a reference page;
the processing unit is configured to: and performing data storage processing on the determined storage page affected by the abnormal power failure.
According to the embodiment of the invention, the storage page of the last written data in the block in which the data are written at the abnormal power failure moment of the Nand flash memory is used as the reference page, and after the storage page affected by the abnormal power failure is determined, the data storage processing is carried out on the storage page affected by the abnormal power failure, so that the influence of the abnormal power failure on the data storage is reduced.
In an exemplary example, the first determining unit according to the embodiment of the present invention is further configured to:
and determining a block in which data is written at the abnormal power failure moment according to the running log information of the application loaded with the Nand Flash.
In an exemplary embodiment, the second determining unit of the embodiment of the present invention is configured to:
determining a reference page and a first preset numerical value page storage page before the reference page as a first storage page which is subjected to abnormal power failure and has written data; and/or the presence of a gas in the gas,
and determining a second preset numerical value page storage page behind the reference page as a second storage page which is not written with data and is affected by abnormal power failure.
In one illustrative example, a first memory page of an embodiment of the present invention includes:
all memory pages in the bit line where the reference page is located.
In an exemplary embodiment, the processing unit of the embodiment of the present invention is configured to:
when the storage page affected by the abnormal power failure comprises a first storage page, transferring data in the first storage page to the storage page not affected by the power failure;
and when the storage pages affected by the abnormal power failure comprise the second storage page, writing preset invalid data into the second storage page.
In an exemplary embodiment, the processing unit of the embodiment of the present invention is configured to:
caching data in a first storage page in a preset cache region;
writing preset invalid data in a second storage page;
after writing the second memory page of invalid data, the data in the first memory page of the cache is written.
The following is a brief description of the embodiments of the present invention by way of application examples, which are only used to illustrate the present invention and are not intended to limit the scope of the present invention.
Application example
The application example adds the data storage processing of the embodiment of the invention to the abnormal power failure process, and the processing after the abnormal power failure comprises the following steps:
the method comprises the following steps: when abnormal power failure occurs in the process of writing data in the Nand Flash, a Block (Block) in which data is being written is defined as Block N by loading running log information of an application of the Nand Flash;
according to the related technology, after the Nand Flash is abnormally powered down, data writing processing is continued after the Nand Flash is abnormally powered down according to the characteristics of the Nand Flash;
step two: when data is recovered during power-on again, determining the maximum storage page of the written data in Block N, namely the storage page (page) of the last written data;
step three: taking the determined storage page in which the data is written last as a reference page, reading the data of all the storage pages in a bit line (word) where the reference page is located, and writing the data into a preset cache region;
in an exemplary embodiment, the preset cache region according to the embodiment of the present invention may include: presetting storage areas in a Static Random Access Memory (SRAM) and a Dynamic Random Access Memory (DRAM);
step four: and writing invalid data in a second preset numerical value page storage page after the reference page.
Step five: and writing the data cached in the cache region into a storage page behind the storage page written with invalid data.
The application example stores the written data affected by the abnormal power failure to the area not affected by the abnormal power failure; invalid data are written in the area which is not written with data and is affected by abnormal power failure, so that the storage of the valid data in the storage page affected by the abnormal power failure is avoided, and the influence of abnormal power failure on data storage is reduced. After the data in the cache region is written into the storage page behind the storage page in which the invalid data is written, the subsequent storage page is also a storage page which is not affected by the abnormal power failure, and the data writing can be continued. The embodiment of the invention can be suitable for abnormal power failure caused by factors such as environmental temperature, abrasion times, durability (Endurance) and the like, can not lose data caused by unstable block due to abnormal power failure, and improves the working stability of the Nand flash memory. The experience that the user uses the Nand flash memory to carry out data storage is promoted.
"one of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media "as is well known to those of ordinary skill in the art.

Claims (10)

1. A method of implementing data storage processing, comprising:
when the NAND gate Nand flash memory is electrified again after abnormal power failure, determining a storage page of the last written data in a block in which data is written at the time of the abnormal power failure;
determining a storage page affected by abnormal power failure by taking the determined storage page of the last written data as a reference page;
and performing data storage processing on the determined storage page affected by the abnormal power failure.
2. The method of claim 1, wherein before determining the storage page to which the data is written last in the block to which the data is written at the time of the power failure, the method further comprises:
and determining a block in which the data is written at the abnormal power failure moment according to the running log information of the application loaded with the Nand flash memory.
3. The method of claim 2, wherein determining the memory pages affected by the abnormal power loss comprises:
determining the reference page and a first preset numerical value page storage page before the reference page as a first storage page which is subjected to abnormal power failure and has written data; and/or the presence of a gas in the gas,
and determining a second preset numerical value page storage page behind the reference page as a second storage page which is not written with data and is affected by abnormal power failure.
4. The method of claim 3, wherein the first memory page comprises:
all memory pages in the bit line where the reference page is located.
5. The method according to claim 3 or 4, wherein the performing data storage processing on the determined storage pages affected by power failure comprises:
when the storage page affected by the abnormal power failure comprises the first storage page, migrating the data in the first storage page to the storage page not affected by the power failure;
and when the memory page affected by the abnormal power failure comprises the second memory page, writing preset invalid data into the second memory page.
6. The method according to claim 3 or 4, wherein when the memory page affected by abnormal power failure includes the first memory page and the second memory page, the performing data storage processing on the determined memory page affected by power failure includes:
caching the data in the first storage page in a preset cache region;
writing preset invalid data in the second storage page;
writing the data in the first memory page of the cache after writing the second memory page of invalid data.
7. A computer storage medium having stored thereon a computer program which, when executed by a processor, implements a method of implementing data storage processing as claimed in any one of claims 1 to 6.
8. A terminal, comprising: a memory and a processor, the memory having a computer program stored therein; wherein the content of the first and second substances,
the processor is configured to execute the computer program in the memory;
the computer program, when executed by the processor, implements a method of implementing data storage processing as claimed in any one of claims 1 to 6.
9. An apparatus for implementing data storage processing, comprising: a first determining unit, a second determining unit and a processing unit; wherein the content of the first and second substances,
the first determination unit is configured to: when the Nand flash memory is electrified again after abnormal power failure, determining a storage page of the last written data in a block in which data is written at the time of the abnormal power failure;
the second determination unit is configured to: determining a storage page affected by abnormal power failure by taking the determined storage page of the last written data as a reference page;
the processing unit is configured to: and performing data storage processing on the determined storage page affected by the abnormal power failure.
10. The apparatus of claim 9, wherein the second determining unit is configured to:
determining the reference page and a first preset numerical value page storage page before the reference page as a first storage page which is subjected to abnormal power failure and has written data; and/or the presence of a gas in the gas,
and determining a second preset numerical value page storage page behind the reference page as a second storage page which is not written with data and is affected by abnormal power failure.
CN202011328864.8A 2020-11-24 2020-11-24 Method and device for realizing data storage processing, computer storage medium and terminal Pending CN112433959A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023098192A1 (en) * 2021-11-30 2023-06-08 苏州浪潮智能科技有限公司 Method and apparatus for processing abnormal power failure of solid state disk, and electronic device and medium

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060271725A1 (en) * 2005-05-24 2006-11-30 Micron Technology, Inc. Version based non-volatile memory translation layer
CN103914397A (en) * 2013-01-09 2014-07-09 深圳市江波龙电子有限公司 Flash memory device and management method thereof
CN107992431A (en) * 2017-12-21 2018-05-04 珠海亿智电子科技有限公司 A kind of power-off protection method of nand flash memory invalid data recycling
CN110580130A (en) * 2019-08-21 2019-12-17 天津大学 Method for writing data into flash memory module for preventing influence of power interruption
CN111324549A (en) * 2018-12-14 2020-06-23 北京兆易创新科技股份有限公司 Memory and control method and device thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060271725A1 (en) * 2005-05-24 2006-11-30 Micron Technology, Inc. Version based non-volatile memory translation layer
CN103914397A (en) * 2013-01-09 2014-07-09 深圳市江波龙电子有限公司 Flash memory device and management method thereof
CN107992431A (en) * 2017-12-21 2018-05-04 珠海亿智电子科技有限公司 A kind of power-off protection method of nand flash memory invalid data recycling
CN111324549A (en) * 2018-12-14 2020-06-23 北京兆易创新科技股份有限公司 Memory and control method and device thereof
CN110580130A (en) * 2019-08-21 2019-12-17 天津大学 Method for writing data into flash memory module for preventing influence of power interruption

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023098192A1 (en) * 2021-11-30 2023-06-08 苏州浪潮智能科技有限公司 Method and apparatus for processing abnormal power failure of solid state disk, and electronic device and medium

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