JP2002014947A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely hold data at no operation by a smaller circuit scale in a 1-chip microcomputer obtained by integrating a CPU and a memory for storing data. SOLUTION: In writing operation, for example, a voltage detection circuit 14 detects that power source voltage from a power source circuit 11 drops to power interruption voltage. Then, the circuit 14 varies the level of a voltage detection signal (d) to be outputted to a writing/reading control circuit 15. Then, at the timing of the break of a data bus 17, the circuit 15 stops the output of writing control signal (c) to a ferroelectric memory 21. Thus, data in the middle of being written is prevented from being written in the memory 21 as uncertain data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly, to a so-called RAM (Random Access Memory) which integrates a CPU and a data storage memory capable of writing and reading data.
emory) relates to a built-in one-chip microcomputer.

[0002]

2. Description of the Related Art Conventionally, a one-chip microcomputer with a built-in RAM has the following configuration in order to hold RAM data when not in operation.

FIG. 3 shows an SRAM (Static RA).
This is an example of a one-chip microcomputer configured to supply a dedicated power supply voltage to M).

In FIG. 3, a power supply voltage from a power supply circuit 101 is supplied to a CPU 103, a voltage detection circuit 104, a write / read control circuit 105, and other circuits 106 via a power supply wiring 102a. Has become.

In the SRAM 107, the power supply circuit 101 is provided.
A dedicated power supply voltage different from that of the power supply circuit 108 is always supplied via the power supply wiring 102b.

In such a configuration, at the time of operation, the operating voltage required for normal operation is supplied from the power supply circuit 101 to each unit except the SRAM 107. Also, SRAM
The operating voltage required for normal operation is supplied to the power supply circuit 107 from the power supply circuit 108.

In this state, it is assumed that an R / W state signal a and a write / read signal b indicating a write / read state are supplied from the CPU 103 to the write / read control circuit 105. Then, the write / read control circuit 105
SRA according to write / read control signal c from
M107 is controlled.

For example, write / read control circuit 105
The CPU 103 is supplied with an R state signal (a) and a read signal (b) indicating a read state. Then
A read control signal (c) is output from the write / read control circuit 105 to the SRAM 107. Thereby, S
Of the data held in the RAM 107, data corresponding to the read control signal (c) is
9 and the CPU 103 and other circuits 1
06.

For example, write / read control circuit 105
The CPU 103 supplies a W state signal (a) and a write signal (b) indicating a write state. Then
A write control signal (c) is output from the write / read control circuit 105 to the SRAM 107. As a result, data sent from the CPU 103 and other circuits 106 via the data bus 109 is written into the SRAM 107 in accordance with the write control signal (c).

The data in the SRAM 107 is held by the supply of power from the power supply circuit 108 during non-operation, that is, after the supply of power from the power supply circuit 101 is cut off. In this case, data can be held by supplying only a minimum voltage (minimum data holding voltage) necessary for holding data, which is lower than a normal operating voltage.

In the one-chip microcomputer having the above configuration, for example, as shown in FIG. 4, during operation, it is detected that the power supply voltage from the power supply circuit 101 has dropped to a specified value (power supply cutoff voltage). Then, the write / read control circuit 1 is
At 05, a voltage detection signal d is output.

Then, the output of the write control signal (c) from the write / read control circuit 105 to the SRAM 107 until the power supply voltage reaches the minimum value (minimum operating voltage) required for normal operation. Stopped. This allows
It is possible to prevent the power supply voltage from falling below the minimum operating voltage and writing data in the middle of writing into the SRAM 107 as indefinite data.

However, in the case of a one-chip microcomputer having such a configuration, there is a problem that two power supply circuits are required. In addition, data can be retained by supplying a minimum amount of power during non-operation, but if power supply itself is cut off,
There is a disadvantage that data cannot be held in the SRAM 107.

Further, data writing to the SRAM 107 is controlled based only on a power supply voltage change on the power supply circuit 101 side for supplying a power supply voltage to circuits other than the SRAM 107, and a power supply circuit for supplying a power supply voltage to the SRAM 107 itself. No change in the power supply voltage on the 108 side is detected. For this reason, it has been difficult to accurately avoid the possibility of writing indefinite data to the SRAM 107.

On the other hand, by integrating the two power supply circuits as described above into a single power supply circuit and preventing the power supply voltage from the integrated power supply circuit from falling below the minimum data holding voltage of the SRAM, With one power supply circuit,
A configuration that enables data to be held in the SRAM during non-operation has also been developed.

However, in the case of this configuration, the minimum data holding voltage is always supplied from the large-scale power supply circuit integrated into one system to each unit other than the SRAM during non-operation. As a result, there is a problem that power is wasted and unnecessary power consumption increases.

Next, in FIG. 5, in order to solve the problems described above, E ² P supplied minimum data holding voltage is required
ROM (Electrically Erasable)
Programmable Read Only M
2 shows an example of a one-chip microcomputer in a case where a power supply voltage is supplied to the entire system from one power supply circuit only during operation by adding an additional memory.

In FIG. 5, a power supply voltage from a power supply circuit 101 is supplied to a CPU 103, a voltage detection circuit 104, a write / read control circuit 105, other circuits 106, an SRAM 107, and E ² PRO via a power supply line 102.
M201.

In such a configuration, for example, FIG.
As shown in (1), when it is detected during operation that the power supply voltage from the power supply circuit 101 has dropped to the power supply cut-off voltage, the voltage detection circuit 104 causes the write / read control circuit 1 to operate.
At 05, a voltage detection signal d is output.

Then, the output of the write control signal (c) from the write / read control circuit 105 to the SRAM 107 is stopped. As a result, the indefinite data is stored in the SRAM 10
7 can be prevented from being written.

In addition, before the power supply voltage reaches the minimum operating voltage, the write / read control circuit 105 controls the SRA
The read control signal (c) for M107 is changed to E ² PRO
A write control signal (e) is output to M201. As a result, the data held in the SRAM 107 is read out via the data bus 109. Then, the data is written into the E ² PROM 201.

As described above, before the power supply voltage is cut off, the data held in the SRAM 107 is transferred to the E ² PR
By rewriting data in the OM 201, data can be retained during non-operation without requiring power supply.

However, in the case of the one-chip microcomputer having this configuration, the power supply voltage is reduced from the power supply cut-off voltage to the minimum operating voltage to a short time.
You need to transfer the data. In particular, the writing operation of the E ² PROM 201 takes longer time than the SRAM 107. Therefore, there is a limit to the amount of data that can be transferred, and it is necessary to set a higher power cutoff voltage, which is not suitable for lowering the power supply voltage.

Further, it is difficult to guarantee that the data written in the E ² PROM 201 is the data held in the SRAM 107.

Further, two memories for holding data are required, which is disadvantageous in terms of a circuit area, and there is a problem that a circuit scale is increased.

[0026]

As described above, conventionally, by incorporating an E ² PROM,
With the power circuit can be reduced to one system without even during non-operation wastefully consumes power, although the data can be held, and limit the amount of data that can be transferred to write to the E ² PROM is There are drawbacks such as an increase in circuit scale.

Therefore, the present invention provides a microcomputer which can securely hold data even when it is not operating and does not require a power supply voltage exclusively for RAM, and which can be easily realized with a smaller circuit scale. It is intended to provide.

[0028]

In order to achieve the above-mentioned object, a microcomputer according to the present invention comprises:
PU, a ferroelectric memory in which data writing is controlled in accordance with a writing signal from the CPU, voltage detecting means for detecting a change in power supply voltage, and the voltage detecting means, whereby the power supply voltage is higher than a specified value. Writing control means for prohibiting writing of data to the ferroelectric memory when the decrease is detected.

According to the microcomputer of the present invention, it is possible to prevent writing of indefinite data without using an E ² PROM and even when the power supply voltage is reduced or cut off. As a result, it is possible to hold only effective data without reducing the circuit scale and without limiting the amount of data that can be written.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows one embodiment of the present invention.
1 shows a configuration example of a chip microcomputer.

In FIG. 1, a power supply voltage from a power supply circuit 11 is supplied to a CPU 13, a voltage detection circuit 14, a write / read control circuit 15, and other circuits 1 via a power supply line 12.
6 and a data storage ferroelectric memory 21 respectively.

The ferroelectric memory 21 is a nonvolatile memory utilizing the property of self-polarization, and is capable of performing a high-speed write operation like an SRAM.

In such a configuration, at the time of operation, an operating voltage required for normal operation is supplied from the power supply circuit 11 to each section.

In this state, the CPU 13 sends a write / read control circuit 15 to the write / read control circuit 15 with R indicating the write / read state.
Assume that / W state signal a and write / read signal b are supplied. Then, the ferroelectric memory 21 is controlled according to the write / read control signal c from the write / read control circuit 15.

For example, the write / read control circuit 15
The R state signal (a) indicating the read state from the CPU 13
And a read signal (b). Then, a read control signal (c) is output from the write / read control circuit 15 to the ferroelectric memory 21. As a result, of the data held in the ferroelectric memory 21, data corresponding to the read control signal (c) is read via the data bus 17 and sent to the CPU 13 and other circuits 16.

On the other hand, the write / read control circuit 15
It is assumed that the W state signal (a) and the write signal (b) indicating the write state are supplied from the PU 13. Then, the write / read control circuit 15 outputs a write control signal (c) to the ferroelectric memory 21. As a result, the data sent from the CPU 13 and the other circuits 16 via the data bus 17 changes according to the write control signal (c).
The data is written in the ferroelectric memory 21 in real time.

Further, as shown in FIG. 2, for example, it is detected during operation that the power supply voltage from the power supply circuit 11 has dropped to a specified value (power supply cutoff voltage). Then, the voltage detection signal d is output (the level is changed) from the voltage detection circuit 14 to the write / read control circuit 15.

Then, at the time of the write operation, the power supply voltage is set to the minimum value (minimum operating voltage) required for normal operation.
, The output of the write control signal (c) from the write / read control circuit 15 to the ferroelectric memory 21 is stopped. In this case, the write control signal (c)
Is stopped at the timing of the break of the operation of the data bus 17 based on the W state signal (a) indicating the write state from the CPU 13. As a result, it is possible to prevent the power supply voltage from dropping below the minimum operating voltage and writing data in the middle of writing into the ferroelectric memory 21 as indefinite data.

The minimum operation voltage in FIG. 2 is equivalent to the operation guarantee voltage of each circuit. For example, in the case of the ferroelectric memory 21, a power-on signal is generated by detecting a power supply voltage. This corresponds to the detection level of the built-in detection circuit.

The power cutoff voltage as described above is determined based on the operation guarantee voltage level of such a circuit, and the output of the write control signal (c) to the ferroelectric memory 21 is stopped. Previously, the level is set to a value obtained by adding a predetermined voltage margin to the operation guarantee voltage of each circuit so that the power supply voltage does not reach the minimum operation voltage.

As described above, the data in the ferroelectric memory 21 is securely retained even when the power supply voltage is lowered and cut off, for example, when the power supply voltage is turned off, including when the power supply voltage is turned off. Available as

In particular, in the ferroelectric memory 21, a high-speed write operation can be performed in real time. Therefore, for example, it is suitable for use in the case where correction data for adjusting the fuel injection amount of an automobile is sequentially updated and recorded, or the communication content of an airplane is recorded.

As described above, it is possible to prevent writing of indefinite data without using an E ² PROM and even when the power supply voltage is lowered or cut off.

That is, as a memory for storing data,
A ferroelectric memory is built in. This makes it possible to hold data during non-operation by one memory without requiring a special power supply voltage. Therefore, as the circuit scale is reduced, valid data can be reliably held without being significantly limited in the amount of data that can be written.

In particular, when it is detected that the normal operating voltage is lower than the power cutoff voltage, the writing of data to the ferroelectric memory is prohibited, so that erroneous data is erroneously detected. It is possible to prevent writing.

In addition, the present invention is not limited to the above-described embodiment, and can be variously modified in an implementation stage without departing from the gist of the invention. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent features. For example, even if some components are deleted from all the components shown in the embodiments, at least one of the problems described in the column of the problem to be solved by the invention can be solved and the effects described in the column of the effect of the invention can be solved. In the case where at least one of the effects described above is obtained, a configuration from which this component is deleted can be extracted as an invention.

[0048]

As described in detail above, according to the present invention, data can be securely retained even when the system is not operating without requiring a power supply voltage dedicated to the RAM.
A microcomputer which can be easily realized with a smaller circuit scale can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a one-chip microcomputer according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an outline of the operation of the one-chip microcomputer having the configuration shown in FIG. 1;

FIG. 3 is a diagram illustrating a conventional technique and its problems.
FIG. 2 is a block diagram of a one-chip microcomputer showing an example of a configuration using AM.

FIG. 4 is a timing chart for explaining an outline of the operation of the one-chip microcomputer having the configuration of FIG. 3;

FIG. 5 is a diagram illustrating a conventional technique and its problems.
FIG. 2 is a block diagram of a one-chip microcomputer showing an example of a configuration using an AM and an E ² PROM.

6 is a timing chart shown for explaining an outline of the operation of the one-chip microcomputer having the configuration shown in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Power supply circuit 12 ... Power supply wiring 13 ... CPU 14 ... Voltage detection circuit 15 ... Write / read control circuit 16 ... Other circuits 17 ... Data bus 21 ... Ferroelectric memory a ... R / W state signal b ... Write / read Signal c: Write / read control signal d: Voltage detection signal

Claims (4)

[Claims] 1. A CPU, a ferroelectric memory in which writing of data is controlled in accordance with a writing signal from the CPU, voltage detecting means for detecting a change in power supply voltage, A writing control means for prohibiting writing of data to the ferroelectric memory when it is detected that the value of the ferroelectric memory drops below a specified value. 2. The writing control unit according to claim 1, wherein writing of data to said ferroelectric memory is prohibited at a timing of a bus operation break based on a writing state signal from said CPU. The microcomputer according to 1. 3. The write control unit according to claim 1, wherein the power supply voltage reaches a minimum value required for a write operation.
2. The microcomputer according to claim 1, wherein writing of data to the ferroelectric memory is prohibited. 4. The microcomputer according to claim 1, wherein the writing of the data in the ferroelectric memory is controlled in real time.