JP2006048304A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer for holding control information showing a power supply voltage and an operating status even in a stand-by time. <P>SOLUTION: This microcomputer including a voltage step-down circuit for generating an internal power supply voltage by decreasing a power supply voltage supplied from the outside and an internal logic circuit for operating when the output voltage of the step-down circuit is supplied, which can be shifted to a stand-by status, is provided with a first area 29 in which the supply of the internal power supply voltage is interrupted in the stand-by status, a second area 23 in which the supply of the internal power supply voltage is maintained in the stand-by status and a third area 28 in which the power supply voltage supplied from the outside is supplied. The first area is provided with a control circuit 19 for outputting control information related with stand-by, and the third area is provided with a storage part 66 for fetching and storing the control information when the microcomputer is shifted to the stand-by status. Thus, it is possible to prevent the control information from being lost even in the stand-by status. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a microcomputer and further to a microcomputer provided with a step-down circuit that steps down a power supply voltage supplied from the outside and supplies it to an internal circuit.

  For example, as described in Patent Document 1, a technique is known in which, in a semiconductor integrated circuit, a supply voltage supplied from the outside is stepped down by a step-down circuit and an internal circuit is driven by a power supply voltage after the step-down. In such a semiconductor device, even if a single power supply voltage (for example, 3.3 V) matched to the voltage of the input / output interface is adopted, an internal circuit (core circuit) that is likely to be an EMI generation source by adopting an internal step-down voltage. ) Can be supplied with a low voltage to reduce power consumption.

  Patent Document 2 describes a semiconductor integrated circuit device that achieves high performance and low power consumption while achieving automatic voltage adjustment of two step-down power supply circuits for active and standby while reducing the area. According to this, the fixed voltage formed by the fixed voltage generation circuit is amplified by the amplifier circuit whose voltage gain is adjusted by the resistor circuit and the switch controlled by the first trimming switch setting signal, and the first reference voltage is obtained. The first output buffer that is formed and activated by the first control signal outputs the internal step-down voltage when the internal circuit is in the active state, and the plurality of MOSFETs and the switch controlled by the second trimming switch setting signal A combination of threshold voltages of MOSFETs is adjusted to form a second reference voltage, and an internal step-down voltage when the internal circuit is in a standby state is output by a second output buffer activated by a second control signal. I have to.

  In Patent Document 3, a power supply voltage is supplied to the memory cell array and its peripheral circuits in the write / read operation mode, and a power supply voltage is supplied to the memory cell array in the data holding standby mode. A semiconductor memory device is described in which the power supply voltage to the peripheral circuit is cut off.

JP 2003-318352 A JP 2004-133800 A JP 2000-298987 A

  A semiconductor integrated circuit is divided into a logic formed by a transistor (high voltage MOS) to which a high voltage can be applied and a core logic formed by a transistor (core MOS) that has a low withstand voltage but can operate at high speed. In the microcomputer, a central processing unit (CPU) and its peripheral circuits are core logic. These core logics are operated by supplying an internal power supply voltage Vdd obtained by stepping down a power supply voltage Vcc supplied from the outside by a step-down circuit. On the other hand, in a random access memory (RAM) built in the microcomputer, the control of the power supply voltage differs between the memory unit and the control unit. For example, the power supply voltage supplied to the memory unit is not cut off in the standby state of the microcomputer. This is to avoid losing information stored in the memory unit. Although the internal power supply voltage is supplied to the power supply terminal of the control unit of the RAM, it is cut off and set to 0 V in the standby state. In addition, the supply of power to the control unit is cut off and the supply of the internal power supply voltage to the CPU, which is the main access to the RAM, is also cut off. In the standby state, the core logic other than the memory unit that needs to hold stored information is turned off. The supply is cut off. The power supply voltage control based on the operation state as described above is performed by the system controller. This system controller is provided in each of the Vdd system and the Vcc system. When the operation state including the active state and the standby state is controlled by software, the CPU sets a register for setting information indicating the operation state. This operation is closed in the internal power supply voltage Vdd system. However, since both the CPU and the Vdd system are powered off during standby, the operation state set in the register cannot be maintained, and furthermore, the power supply voltage can be controlled based on the retained operation state. Can not.

  An object of the present invention is to provide a microcomputer capable of holding information on a software standby state even in a standby state set by software.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, it includes a step-down circuit that generates an internal power supply voltage by stepping down a power supply voltage supplied from the outside, and an internal logic circuit that operates when an output voltage of the step-down circuit is supplied, and is in a normal operation state (active State), a microcomputer having a plurality of operating states including a standby state and capable of transitioning from the active state to the standby state, the first area where the supply of the internal power supply voltage is cut off in the standby state, and the microcomputer in the standby state A second area in which the supply of the internal power supply voltage is maintained, and a third area that is operable based on the power supply voltage supplied from the outside and that maintains the external power supply in the standby state, The first area is provided with a control circuit that outputs control information related to standby, and the third area transitions to the standby state. It takes in providing the retainable storage unit the control information in that. The active state is a state in which an internal power supply voltage is supplied to the first and second areas and an external power supply voltage is supplied to the third area, and any circuit is operable. It is. Furthermore, as a method for setting the operation state, there are a case where an operation mode is designated from the outside and a case where the control information including the operation mode is set by software control by the CPU.

  According to the above means, the control information is fetched from the first area where the power cut-off control is performed when the storage section of the third area where the power supply is not cut off even in the standby state when transitioning to the standby state. By holding it, the control information is not lost in the standby state. This achieves the provision of a microcomputer capable of maintaining the standby state.

As a more specific aspect, a step-down circuit that generates an internal power supply voltage by stepping down a power supply voltage supplied from outside,
A microcomputer capable of transitioning from an active state to a standby state, wherein the supply of the internal power supply voltage is cut off in a standby state. An area, a second area in which the supply of the internal power supply voltage is maintained in the standby state, and a third area in which the power supply voltage supplied from the outside is supplied and the power supply is not interrupted even in the standby state, The first area is provided with a central processing unit capable of outputting control information relating to standby and a first flip-flop circuit capable of holding control information relating to standby, and the second area includes the internal circuit in a standby state. A RAM memory cell unit capable of holding internal information by maintaining power supply is provided. The third area can be provided with a second flip-flop circuit capable of retaining captures control information held in the first flip-flop circuit when a transition to the standby state.

  At this time, the first area includes a first trimming register capable of holding trimming information for controlling the step-down circuit, and a first module selection register capable of holding information on a module to which a power supply voltage is supplied during standby. In the third area, a second trimming register capable of capturing and holding information held in the first trimming register based on an output signal of the second flip-flop circuit when transitioning to a standby state; The second module selection register that can take and hold the information held in the first module selection register on the basis of the output signal of the second flip-flop circuit when transitioning to the standby state can be provided. In order to increase the speed of transmission of the control information, when the CPU that is the main body for setting the information, the flip-flop circuit for setting the information, and the register are arranged in the same internal power supply area, and when transitioning to the standby state In order to transmit the set information at high speed, the first flip-flop circuit and the second flip-flop circuit, the first trimming register and the second trimming register, the first module selection register and the second module selection register are level shifters. It is better to connect with a dedicated line through.

  In the third area, a trimming circuit capable of trimming the power supply voltage of the circuit belonging to the second area can be provided according to the information held in the second trimming register.

  Each of the trimming circuits can be provided with a regulator capable of trimming the output voltage, and the regulator can form a power supply voltage for circuits belonging to the first area and the second area.

  A memory cell portion included in a second area to which a first power supply voltage of a first level is supplied in an active state and a second power supply voltage of a level lower than the first level is supplied in a standby state; A RAM including a control unit included in a first area capable of controlling the operation of the memory cell unit when the voltage supply is cut off and the first power supply voltage of the first level is supplied in the active state. Can do.

  In this case, the regulator can form a first main regulator capable of forming the first power supply voltage supplied to the control unit, and the first power supply voltage supplied to the memory cell unit when active. A second main regulator and a standby regulator capable of forming the second power supply voltage supplied to the memory cell unit during standby can be provided. At this time, in order to avoid a collision of voltage outputs, the output terminal of the second main regulator is controlled to a high impedance state during standby.

  The output voltage of the standby regulator can be supplied to the first trimming register and the first module selection register.

  The regulator may form a first main regulator capable of forming the first power supply voltage supplied to the control unit, and a second main regulator capable of forming the first power supply voltage supplied to the memory cell unit when active. A main regulator; a standby regulator capable of forming the second power supply voltage supplied to the memory cell unit during standby; an output terminal of the first main regulator; and an output terminal of the second main regulator short-circuited to the output terminal And a switch disposed between the standby regulator and the power supply voltage supply path to the memory cell portion.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, the microcomputer can hold control information indicating the operating state even during standby.

  FIG. 1 shows an example of the overall configuration of a microcomputer according to the present invention.

  The microcomputer 10 shown in FIG. 1 is not particularly limited, but includes a PLL (phase locked loop) 11, a trimming circuit 12, a regulator 13, a flash memory 17, a BSC (bus state controller) 18, and a CPU (central processing unit). 19, FPU (floating point unit) 20, other core logic 21, RAM 22, and system controller 25, which are formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The flash memory 17, BSC 18, CPU 19, and FPU 20 are coupled by a system bus 26 so that signals can be exchanged.

  The PLL 11 generates a system clock signal synchronized with a clock signal input from the outside via the external terminal EXTAL. The generated system clock signal is supplied to each internal circuit including the CPU. The regulator 13 generates an internal power supply voltage Vdd. The trimming circuit 12 can adjust the voltage level generated by the regulator 13 based on the trimming information. The flash memory 17 stores a program executed by the CPU 19. The BSC 18 is disposed between the system bus 26 and the peripheral bus 27, and controls signal bridging between the two buses. The CPU 19 performs a predetermined calculation process by executing a program in the flash memory 17. The FPU 20 is used to execute instructions related to non-integer numbers. The RAM 22 is not particularly limited, but includes a memory cell unit 23 and a RAM control unit 24, and is used as a work area in the arithmetic processing by the CPU 19. The memory cell unit 23 is not particularly limited, but is formed by arranging a plurality of static memory cells in an array. The RAM control unit 24 controls the operation of the memory cell unit 23. The system controller 25 includes a Vcc controller 14, a level shifter 15, and a Vdd controller 16, and is based on a mode signal MD, a hardware standby signal / HSTBY, a reset signal RST, and an external application control signal VDDVLD given from the outside. It is also possible to control the operation of each part, and further control the operation based on the operation state set by the CPU. The Vcc controller 14 controls the operation of a circuit to which a high potential side power supply Vcc (first power supply potential, for example, 3.3 V) supplied from the outside is supplied. The Vdd system controller 16 controls the operation of a circuit that operates by being supplied with a high potential side power supply Vdd (second power supply potential, for example, 1.5 V) obtained by stepping down the high potential side power supply Vcc. To do. The level shifter 15 performs level shift of signals exchanged between the Vcc controller 14 and the Vdd controller 16.

  FIG. 2 shows a detailed configuration of the power supply system in the microcomputer 10.

  The microcomputer 10 includes a circuit (referred to as a “Vcc system circuit”) 28 to which an external high potential side power supply Vcc is supplied, and a circuit (Vdd system circuit) 29 to which an internally lowered high potential side power supply Vdd is supplied. including. The Vcc system circuit 28 includes a trimming circuit 12, a Vcc system controller 14, a standby regulator 13-0, and main regulators 13-1 and 13-2. The Vdd system circuit 29 includes a Vdd system controller 16, RAM 22, flash memory 17, BSC 18, CPU 19, FPU 20, and other core logic 21.

  The Vcc controller 14 includes a mode control unit 25A, a trimming control unit 25B, a standby control unit 25C, and an external application control unit 25D, and is supplied with a high potential side power supply Vcc (power before core step-down) via an external terminal. The mode control unit 25A performs mode control according to mode control signals MD0 to MD2 supplied from the outside. The trimming control unit 25B performs voltage level trimming control based on the trimming signal transmitted from the Vdd controller 16. The standby control unit 25C performs standby control based on the hardware standby signal / HSTBY supplied from the outside or the software standby control signal transmitted from the Vdd controller 16. The external voltage application control unit 25D performs application control of the high potential side power supply Vdd based on an external application control signal supplied from the outside. The regulator 13 includes a standby regulator 13-0 and main regulators 13-1 and 13-2, each of which can adjust the output voltage. The output voltage VddRAM of the standby regulator 13-0 and the main regulator 13-1 is supplied to the memory cell unit 23. The output voltage Vdd of the main regulator 13-2 is supplied to the Vdd controller 16, RAM 22, flash memory 17, BSC 18, CPU 19, FPU 20, and other core logic 21.

  3 and 4 show the constituent blocks of the microcomputer 10 in relation to the power supply voltage.

The Vcc system circuit 28 is supplied with a high potential side power supply Vcc (eg, 3.3 V) regardless of whether the microcomputer 10 is in an active state or a standby state, whereas the Vdd system circuit 29 is in an active state. When the standby regulator 13-0 and the main regulators 13-1 and 13-2 are controlled by the Vdd controller 16 in the standby state, the supply state of the power supply voltage is switched. That is, in the active state, as shown in FIG. 3, the output voltages of the standby regulator 13-0 and the main regulators 13-1 and 13-2 are set to 1.5 V, which are supplied to each part in the Vdd system circuit 29. On the other hand, in the standby state, the output voltage of the standby regulator 13-0 is switched to a predetermined voltage VddRAM for standby (a level lower than Vdd), and the output terminal of the main regulator 13-1 is in a high impedance state (Hiz). And the output voltage of the main regulator 13-2 is 0V. As described above, the output voltage of the standby regulator 13-0 is switched to the predetermined voltage VddRAM for standby (a level lower than Vdd), and the output terminal of the main regulator 13-1 is set to the high impedance state (Hiz). The memory state of the memory cell unit 23 in the standby state is maintained, and the output voltage of the main regulator 13-2 is set to 0 V, so that the memory such as the Vdd controller 16, the RAM control unit 24, and other core logic 21 The power consumption is reduced by cutting off the power supply voltage supply to the Vdd circuit excluding the cell portion 23.

  Since the supply of the power supply voltage to the Vdd controller 16 is stopped in the standby state, the power supply voltage control by the Vdd controller 16 becomes impossible in the standby state. Therefore, in this example, control information of the Vdd controller 16 is transmitted to the Vcc controller 14 when transitioning from the active state to the standby state, and the power supply voltage control during standby is performed by the Vcc controller 14.

  FIG. 5 shows a more detailed configuration example of the main part of the microcomputer 10.

  Since the Vcc controller 14 and the Vdd system controller 16 have different operating power supply voltages, it is necessary to match the levels of signals exchanged between them. Therefore, in this example, level shifters 43 to 46 capable of shifting the signal level are interposed between the Vcc controller 14 and the Vdd controller 16, and the output signal of the Vcc controller 14 is a Vdd signal by the level shifters 43 to 46. After being shifted to the level, it is transmitted to the Vdd controller 16. Further, the output signal of the Vdd controller 16 is shifted to the Vcc signal level by the level shifters 41 to 46 and then transmitted to the Vcc controller 14.

  The Vcc controller 14 includes logic gates 67 and 73, a flip-flop circuit (FF) 66, standby control logic 68, a trimming register 69, a selector 70, and a module selection register (Vcc system) 72. The flip-flop circuit 66 is set by a signal from the Vcc controller 16 and is reset by a reset signal / reset and a hardware standby signal / HSTBY. The output signal of the flip-flop circuit 66 is transmitted to the standby control logic 68 and the trimming register 69 via the logic gate 67. The hardware standby signal / HSTBY input from the external terminal is transmitted to the standby control logic 68 and the trimming register 69 via the logic gate (OR) 67 after the logic is inverted by the logic gate (inverter) 73. The The output signal of the trimming register 69 and the signal transmitted from the Vdd controller 16 are selectively transmitted to the trimming circuit 12 by the selector 70, and the standby regulator 13-0 and the main regulator 13-1 are transmitted via the trimming circuit 12. , 13-2 are trimmed.

  The Vdd system controller 16 includes trimming registers 51 and 52, a module selection register 53, a flip-flop circuit 54, and a logic gate 55. The trimming registers 51 and 52 and the module selection register 53 are coupled to the CPU 19 via the peripheral bus 27 and can be set by the CPU 19. The flip-flop circuit 54 is set when the sleep instruction is executed by the CPU 19 and the sleep control signal SLEEP is set to the logical value “1”, and the reset signal / reset and the hardware standby signal / HSTBY are set to the logical value “0”. Will be reset. Then, the output signal of the flip-flop circuit 54 is transmitted to the logic gate 55 in the subsequent stage, where the software standby (SSTBY) bit and the AND logic are taken. The output signal of the logic gate 55 is transmitted to the trimming register 69 via the level shifter 44. The output signal of the trimming register 52 is transmitted to the selector 70 via the level shifter 45. The output signal of the module selection register 53 is transmitted to the module selection register 72 via the level shifter 46.

  In this example, the RAM 22 includes three RAMs 22-1, 22-2, and 22-3. The three RAMs 22-1, 22-2, and 22-3 can be individually supplied with a power supply voltage, so that the standby regulators 13-0, 13 are respectively connected via the corresponding switches SW1, SW2, and SW3. -1 output voltage is supplied. The switches SW1, SW2 and SW3 are controlled in operation by the output signal of the module selection register 72.

  The operation of the above configuration will be described.

  In the software standby state, the SSTBY bit 56 is set to “1”, and when the CPU 19 executes a sleep instruction, the CPU 19 makes a transition to the standby state as a trigger. In the standby state, in order to reduce power consumption, the supply of the high potential side power supply Vdd is cut off except for the memory cell units 22-1, 22-2 and 22-3. The signal determining that the software standby state is present exists in the portion where the power is cut off. Therefore, in this example, a signal that is determined to be in the software standby state is held in the Vcc circuit 28 according to the following procedure.

  The CPU 19 sets the SSTBY bit 56 to the logical value “1”, and the CPU 19 sets the trimming information at the standby time in the trimming register 51, and sets the information on the module to which the power supply voltage is supplied at the standby time in the module selection register 53. It is assumed that When a sleep command is executed by the CPU 19 in this state, the sleep control signal SLEEP is set to a logical value “1” by the CPU 19 and is set in the flip-flop circuit 54. The output signal of the flip-flop circuit 54 is transmitted to the level shifter 43 through the logic gate 55, and after being level-shifted there, is transmitted to the flip-flop circuit 66 in the Vcc controller 14 and set therein. As described above, the set information of the flip-flop circuit 54 in the Vdd controller 16 is transmitted and set to the flip-flop circuit 66 in the Vcc controller 14, so that the power supply voltage supply to the Vdd system circuit 29 is cut off by standby. Thus, even when the signal on the Vdd controller 16 side becomes logic indefinite, the information of the sleep control signal SLEEP is not lost. Further, the trimming register 69 and the module selection register 72 are written based on the output signal when the flip-flop circuit 66 in the Vcc-related controller 14 is set, and the information held in the trimming register 51 in the Vcc-related controller circuit 16 is set. The information held in the module selection register 53 is transmitted and written to the trimming register 69 and the module selection register 72 in the Vcc controller 14 via the corresponding level shifters 44 and 46, respectively.

  Next, the output signal of the trimming register 69 in the Vcc controller 14 is transmitted to the trimming circuit 12 via the selector 70 and further transmitted to the standby regulator 13-0 and the main regulators 13-1 and 13-2. . In standby, the output voltage of the standby regulator 13-0 is set to the voltage level determined by the trimming during standby, the output terminal of the main regulator 13-1 is controlled to high impedance (Hiz), and the main regulator 13- The output voltage of 2 is set to 0V. The voltage level determined by the trimming during standby is set to a value slightly lower than that when the high-potential-side power supply Vdd is 1.5V. If this value is too low, it is considered that an error occurs in the stored information in the memory cell portion of the RAM 22-1, 22-2, 22-3, so that it is set to be as low as possible in view of this. The

  When the output voltage of the main regulator 13-2 is set to 0V, the power supply voltage supply in the Vdd controller 16 is cut off, so that a signal for determining that the Vdd controller 16 is in a standby state, for example, the trimming register 51 The output logic and the output logic of the module selection register 53 are undefined. While the signal for determining that the Vdd controller 16 is in the standby state is indefinite, the output logic of the level shifter 43 is fixed to the logical value “0” by the power supply detection signal. It is prevented from flowing. Although the output voltage of the standby regulator 69 depends on the trimming data, the trimming data is also transferred to and held in a predetermined register in the Vcc controller 14 at the timing of transition to the standby state. By setting a desired standby voltage level inside, a standby voltage of a desired level can be formed during standby. Further, by setting a module for supplying power in the module selection register 53, it is possible to hold data only in a memory cell portion in a desired RAM during standby.

  Since the initial value of the trimming information set in the trimming registers 51 and 52 is stored in the flash memory 17, the initial value of the trimming information can be changed by changing the trimming information in the flash memory 17.

  FIG. 6 shows the timing of the standby transition.

  The standby signal of the Vdd controller 16 is propagated to the Vcc controller 14 via the level shifter and latched in the corresponding register. Since the change causes the Vdd trimming data to be latched in a predetermined register in the Vcc controller 14, the power supply transition starts. Therefore, by keeping this timing, the high potential side power supply Vdd immediately before being cut off can be obtained. Data can be accurately latched into a predetermined register in the Vcc controller 14.

  7 to 9 show other configuration examples of the main part of the microcomputer 10.

  7 is greatly different from that shown in FIG. 5 in that the trimming information stored in the flash memory 17 is reset via the level shifter 44 in the reset process of the microcomputer 10. It is a point that is transferred to. According to such a configuration, it is not necessary to transfer trimming information from the trimming register 51 in the Vdd-related controller 16 to the trimming register 69 in the Vcc-related controller 14 immediately before standby, so that compared to the configuration shown in FIG. Control by the Vdd controller 16 immediately before standby becomes easy. Further, since the one corresponding to the trimming register 51 in the Vdd controller 16 in FIG. 5 can be omitted, the scale of hardware can be reduced accordingly.

  8 is greatly different from that shown in FIG. 5 in that the power supply voltage VddRAM supplied to the memory cell portion in the RAMs 22-1, 22-2, and 22-3 is the trimming register 51 and the module selection. The point is that the operation power supply voltage is supplied to the register 53. The second area includes a trimming register 51 and a module selection register 53 in addition to the memory cell portion 23 of the RAM. According to such a configuration, since it is not necessary to provide the trimming register 51 and the module selection register 53 in the Vdd controller 16, the control in the Vdd controller 16 is facilitated.

  9 is greatly different from that shown in FIG. 5 in that the output terminals of the main regulators 13-1 and 13-2 are short-circuited, and the output terminals of the main regulators 13-1 and 13-2 are short-circuited. The switch SW4 is provided between the standby regulator 13-0 and the output voltage transmission path. The standby control logic 68 has a function of detecting the voltage level of the high-potential side power supply Vdd, and controls the operation of the switch SW4 based on the Vdd detection result. In standby mode, the output voltages of the main regulators 13-1 and 13-2 become 0V, and the output voltage of the standby regulator 13-0 is set to a value determined by trimming. Therefore, by turning off the switch SW4, A short circuit between the output terminals of the main regulators 13-1 and 13-2 and the output voltage transmission path of the standby regulator 13-0 is avoided. According to such a configuration, since the main regulators 13-1 and 13-2 are connected by a common power source, the regulator can be easily controlled.

  FIG. 10 shows the operation timing of the switch SW4.

  In the transition from the active state to the standby state, when the standby signal is asserted, the power supply voltage detection result becomes a low level at a certain potential from which the power supply voltage approaches 0V. If the standby signal is negated when transitioning from the standby state to the active state, the power supply voltage is raised to 1.5V. At this time, the power supply voltage detection result changes to a high level at a certain voltage. When transitioning from the active state to the standby state, it is necessary to hold the power supply voltage of the memory cell portion in the RAMs 22-1, 22-2, and 22-3, so that the standby control logic 68 before the power supply voltage is lowered. The switch SW4 is turned off. On the contrary, when the standby state is changed to the active state, the switch SW4 is turned on according to the power supply voltage detection result.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

1 is a block diagram illustrating an example of the overall configuration of a microcomputer according to the present invention. It is a block diagram of a detailed configuration example of a power supply system in the microcomputer. It is explanatory drawing of the power supply voltage supply state in the active state of the said microcomputer. It is explanatory drawing of the power supply voltage supply state in the standby state of the said microcomputer. It is a block diagram of a more detailed configuration example of the main part in the microcomputer. FIG. 6 is an operation timing chart of the main part in the configuration shown in FIG. 5. It is another example of a block diagram of the principal part in the said microcomputer. It is another example of a block diagram of the principal part in the said microcomputer. It is another example of a block diagram of the principal part in the said microcomputer. FIG. 10 is an operation timing chart of the main part in the configuration shown in FIG. 9.

Explanation of symbols

10 Microcomputer 11 PLL
12 Trimming Circuit 13 Regulator 13-0 Standby Regulator 13-1, 13-2 Main Regulator 14 Vcc Controller 15, 41-46 Level Shifter 16 Vdd Controller 17 Flash Memory 18 BSC
19 CPU
20 FPU
21 Other core logic 22 RAM
23 memory cell unit 24 RAM control unit 25 system controller

Claims (12)

A step-down circuit that generates an internal power supply voltage by stepping down a power supply voltage supplied from outside;
An internal logic circuit that operates by being supplied with the output voltage of the step-down circuit,
A microcomputer capable of transitioning from an active state to a standby state,
The internal logic circuit includes a first area in which supply of the internal power supply voltage is interrupted in a standby state;
A second area in which the supply of the internal power supply voltage is maintained in a standby state;
A third area to which the power supply voltage supplied from the outside is supplied,
The first area is provided with a control circuit that outputs control information related to the standby state.
The microcomputer in which said 3rd area is provided with the memory | storage part which can take in and hold | maintain the said control information when changing to a standby state. The microcomputer according to claim 1, wherein the third area is maintained in the standby state and the external power supply voltage supply is maintained. A step-down circuit that generates an internal power supply voltage by stepping down a power supply voltage supplied from outside;
An internal logic circuit that operates by being supplied with the output voltage of the step-down circuit,
A microcomputer capable of transitioning from an active state to a standby state,
A first area in which the supply of the internal power supply voltage is cut off in a standby state;
A second area in which the supply of the internal power supply voltage is maintained in a standby state;
A third area to which the power supply voltage supplied from the outside is supplied,
The internal logic circuit includes the first area and the second area,
The first area is provided with a central processing unit capable of outputting control information relating to standby and a first flip-flop circuit capable of holding control information relating to standby,
The microcomputer in which said 3rd area is provided with the 2nd flip-flop circuit which can take in and hold the control information stored in said 1st flip-flop circuit at the time of changing to a standby state. The first area is further provided with a first trimming register capable of holding trimming information for the step-down circuit,
The second trimming register is provided in the third area, which is capable of taking in and holding information held in the first trimming register based on an output signal of the second flip-flop circuit when transiting to a standby state. 3. The microcomputer according to 3. The first area is further provided with a first module selection register capable of holding information on a module to which the internal power supply voltage is supplied in the standby state.
The third area is provided with a second module selection register capable of capturing and holding information held in the first module selection register based on an output signal of the second flip-flop circuit when transitioning to a standby state. The microcomputer according to claim 4. The first flip-flop circuit operated by the internal power supply voltage and the second flip-flop circuit operated by the external power supply voltage are coupled to each other by a dedicated line that enables transmission of the control information. 4. The microcomputer according to claim 3. 7. The microcomputer according to claim 6, wherein the third area includes a trimming circuit capable of trimming an internal power supply voltage to be supplied to a circuit belonging to the second area according to information held in the second trimming register. Each regulator includes a regulator capable of trimming an output voltage by the trimming circuit, the regulator is operable based on a power supply voltage supplied from the outside, and the power supply voltage of the internal circuit belonging to the first area is regulated by the regulator. 8. The microcomputer according to claim 7, wherein: A memory cell portion to which a first power supply voltage of a first level is supplied in an active state and a second power supply voltage of a level lower than the first level is supplied in a standby state;
A control unit capable of controlling the operation of the memory cell unit by cutting off the power supply voltage supply in the standby state and supplying the first power supply voltage of the first level in the active state;
9. The microcomputer according to claim 8, wherein the control unit is included in a first area, and the memory cell unit is included in a second area. The regulator includes a first main regulator capable of forming the first power supply voltage supplied to the first area;
A second main regulator capable of forming the first power supply voltage supplied to the second area when active;
10. A standby regulator capable of forming the second power supply voltage supplied to the second area during standby, wherein the output terminal of the second main regulator is controlled to be in a high impedance state during standby. The microcomputer as described. 11. The microcomputer according to claim 10, wherein an output voltage of the first main regulator is supplied to the first trimming register and the first module selection register. The regulator includes a first main regulator capable of forming the first power supply voltage supplied to the first area;
A second main regulator capable of forming the first power supply voltage supplied to the second area when active;
A standby regulator capable of forming the second power supply voltage supplied to the second area during standby;
And a switch disposed between the output terminal of the first main regulator and the output terminal of the second main regulator short-circuited thereto, and a power supply voltage supply path from the standby regulator to the second area. Item 11. The microcomputer according to Item 9.

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