JP2014093585A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an off current in a standby mode.SOLUTION: A semiconductor integrated circuit includes: a CMOS logic circuit having a P channel transistor disposed between a first power line fed with a first voltage and a predetermined node, and an N channel transistor disposed between the predetermined node and a second power line fed with a second voltage lower than the first voltage; an off current measurement circuit for comparing a first off current through the P channel transistor turned off and a second off current through the N channel transistor turned off, and outputting a comparison result signal; and a control circuit for, when entering to a standby mode, according to the latest comparison result signal, turning on the P channel transistor and turning off the N channel transistor if the first off current is greater than the second off current, or turning off the P channel transistor and turning on the N channel transistor if the second off current is greater than the first off current.

Description

  The present invention relates to a semiconductor integrated circuit.

  In recent years, with the miniaturization and lowering of voltage of semiconductor integrated circuits, the channel length of transistors has become shorter and the threshold voltage has been lowered. As a result, even when the transistor is turned off, the transistor is not completely non-conductive, and an off current is generated between the drain and the source. Therefore, in order to reduce the power consumption during standby of the semiconductor integrated circuit, it is necessary to reduce the off-state current of the off-state transistor.

  For example, when a large transistor is used in a CMOS logic circuit portion of a semiconductor integrated circuit, the off-current of the transistor usually increases. Therefore, conventionally, when the semiconductor integrated circuit is on standby, the PMOS transistor and NMOS transistor constituting the CMOS inverter are turned on, and the transistor with the smaller off-current is turned off, and the transistor with the smaller off-current is turned off. A method of reducing the off-current has been taken, such as setting the state (Patent Document 1).

JP 2008-306281 A JP 2008-153415 A JP 2006-279928 A

  However, the off-current characteristics depend on the chip manufacturing process, and the off-current value varies between chips. In addition, the off-current varies depending on the temperature of the transistor, and the temperature-dependent characteristics are different for each transistor. For this reason, among the PMOS transistors and NMOS transistors constituting the CMOS inverter, the transistor having the larger off-current during standby differs depending on the chip and may change depending on the temperature at that time.

  Therefore, the above-described conventional off-current reduction method cannot cope with manufacturing variations of off-state currents and fluctuations due to temperature because transistors that are turned on and off during standby are determined in advance in the design stage.

  In view of the above, an object of the present invention is to provide a semiconductor integrated circuit that reduces off-current during standby.

The first aspect of the semiconductor integrated circuit is
A first P-channel transistor provided between a first power supply line to which a first voltage is applied and a predetermined node; a second voltage lower than the predetermined node and the first voltage; A CMOS logic circuit having a first N-channel transistor provided between a given second power supply line;
An off current that compares the first off current of the second P-channel transistor in the off state with the second off current of the second N-channel transistor in the off state and outputs a comparison result signal A measurement circuit;
When entering the standby mode, based on the latest comparison result signal, if the first off-current is larger than the second off-current, the first P-channel transistor is turned on and the first off-current is turned on. When the N-channel transistor is turned off and the second off-current is larger than the first off-current, the first P-channel transistor is turned off and the first N-channel transistor is turned on. A control circuit.

  According to the first aspect of the semiconductor integrated circuit, the off-current during standby can be reduced.

1 is a diagram illustrating a semiconductor integrated circuit according to a first embodiment. It is a figure which shows the 1st structural example of the off-current measuring circuit in 1st Embodiment. It is a figure which shows the 2nd structural example of the off-current measuring circuit in 1st Embodiment. It is a figure which shows the CMOS control circuit in 1st Embodiment. It is a figure which shows the truth table of the CMOS control circuit in 1st Embodiment. It is a figure which shows the CMOS logic circuit in 1st Embodiment. It is a figure which shows the truth table of the CMOS logic circuit in 1st Embodiment. 3 is a timing chart of the semiconductor integrated circuit according to the first embodiment. It is a figure which shows the semiconductor integrated circuit in 2nd Embodiment. It is a figure which shows the off-current measuring circuit in 2nd Embodiment. , Is a timing chart of the semiconductor integrated circuit in the second embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a diagram illustrating a semiconductor integrated circuit according to the first embodiment. In FIG. 1, a signal whose code ends with “x” indicates low active, and a signal with “z” indicates high active.

  The semiconductor integrated circuit 10 compares an off current of the PMOS transistor and the NMOS transistor and outputs a comparison result signal cmpoffz, and a standby mode that outputs an H level standby signal stbz when the semiconductor integrated circuit 10 is in a standby mode. A control circuit 12; a CMOS control circuit 13 that outputs a clamp signal clmpz, a first clamp control signal outhx, and a second clamp control signal outlz based on the comparison result signal cmpoffz and the standby signal stbz; And a CMOS logic circuit 14 having a CMOS inverter that is controlled to be turned on and off in order to reduce off current in the standby mode.

  The semiconductor integrated circuit 10 shifts from the normal operation to the standby mode in order to reduce power consumption when there is no external access for a certain period of time or when a command for actively reducing power consumption is input from the outside. . When the semiconductor integrated circuit 10 is in the standby mode, the CMOS logic circuit 14 stops operating. Then, the PMOS transistor constituting the CMOS inverter of the CMOS logic circuit 14 is turned on and the NMOS transistor is turned off, or the PMOS transistor is turned off and the NMOS transistor is turned on. As a result, the output of the CMOS inverter is fixed at the H level or the L level and is supplied to the subsequent circuit of the CMOS inverter, and current consumption stops.

  However, with the miniaturization of the semiconductor integrated circuit 10, the threshold voltage of the transistor is reduced, the channel length is shortened, and an off-current is generated in the off-state transistor. Therefore, it is necessary to reduce the off current in order to reduce the current consumption in the standby mode. Since this off-current usually has manufacturing variations, the transistor having the larger off-current among the PMOS transistor and the NMOS transistor differs depending on the chip. In addition, since the temperature dependence characteristics are different between the PMOS transistor and the NMOS transistor, the transistor on the side where the off-state current is large may differ depending on the temperature of the transistor.

  In view of this, the semiconductor integrated circuit 10 turns on the transistor having the larger off-current at the time of standby among the PMOS transistors and NMOS transistors constituting the CMOS inverter included in the CMOS logic circuit 14 at the time of standby, and the smaller of the off-current. The transistor is turned off to reduce off current.

  Specifically, as will be described later, the off-current measuring circuit 11 first compares the off-currents of the off-current measuring PMOS transistor and NMOS transistor in the standby mode. Then, based on the comparison result, the CMOS control circuit 13 controls a transistor having a large off current to be turned on and a transistor having a small off current to be turned off among the PMOS transistor and the NMOS transistor of the CMOS inverter included in the CMOS logic circuit 14. .

  FIG. 2 is a diagram illustrating a first configuration example of the off-current measurement circuit according to the first embodiment. The off-current measuring circuit 11 includes a resistor RP and a CMOS transistor C1 connected in series between a power supply voltage Vdd and a reference voltage GND, a resistor RN and a CMOS transistor C2 connected in series, a power supply voltage GND and a reference voltage GND. And a comparator CMP1 connected to. In FIG. 2, it is assumed that the resistance values of the resistors RP and RN are equal.

  The gate of the CMOS transistor C1 is connected to the connection terminal G1 between the resistor RP and the CMOS transistor C1, and the gate of the CMOS transistor C2 is connected to the reference voltage GND. As a result, the PMOS transistor P1 constituting the CMOS transistor C1 is turned off, and the NMOS transistor N1 is turned on. Further, the PMOS transistor P2 constituting the CMOS transistor C2 is turned on, and the NMOS transistor N2 is turned off. Then, the off currents Ioff_p and Ioff_n flow between the power supply voltage Vdd and the reference voltage GND by the PMOS transistor P1 and the NMOS transistor N2 which are turned off, respectively.

  The comparator CMP1 compares the voltage V1 of the resistor RP and the connection terminal G1 of the CMOS transistor C1 with the voltage V2 of the resistor RN and the connection terminal G2 of the CMOS transistor C2, and outputs a comparison result signal cmoffz. Since the off currents Ioff_p and Ioff_n flow in the resistors RP and RN, respectively, the comparator CMP1 can determine which of the off currents Ioff_p and Ioff_n is larger by comparing the voltages V1 and V2. .

  For example, when the off-current Ioff_n of the NMOS transistor N2 is larger than the off-current Ioff_p of the PMOS transistor P1, V1 becomes higher than the voltage V2, and the comparator CMP1 outputs an L-level comparison result signal cmoffz. On the other hand, when the off current Ioff_p of the PMOS transistor P1 is larger than the off current Ioff_n of the NMOS transistor N2, the voltage V1 becomes higher than V2, and the comparator CMP1 outputs an H level comparison result signal cmoffz.

  Note that the resistor RP and the CMOS transistor C1, and the resistor RN and the CMOS transistor C2 may be connected to each other in the up-down position opposite to that in FIG. In this case, the resistor RP and the CMOS transistor C1 are connected in series in the order of the CMOS transistor C1 and the resistor RP between the power supply voltage Vdd and the reference voltage GND, and the resistor RN and the CMOS transistor C2 are connected to the power supply voltage Vdd and the reference voltage GND. Are connected in series in the order of the CMOS transistor C2 and the resistor RN.

  As a result, the gate of the CMOS transistor C1 is supplied with the power supply voltage Vdd, the PMOS transistor P1 is turned off, and the NMOS transistor N1 is turned on. Further, the voltage V2 of the connection terminal G2 between the CMOS transistor C2 and the resistor RN is supplied to the gate of the CMOS transistor C2, so that the PMOS transistor P2 is turned on and the NMOS transistor N2 is turned off. As a result, an off-current flows through the PMOS transistor P1 and the NMOS transistor N2, so that the comparator CMP1 compares the voltage V1 at the connection terminal G1 and the voltage V2 at the connection terminal G2, as in FIG. The magnitudes of Ioff_p and Ioff_n can be determined.

  FIG. 3 is a diagram illustrating a second configuration example of the off-current measurement circuit according to the first embodiment. Since the off current detection circuit 11 compares the off currents of the PMOS transistor and the NMOS transistor, the PMOS transistor P1 and the NMOS transistor N2 may be connected in series to the resistors RP and RN, respectively, as shown in FIG. As a result, both the PMOS transistor P1 and the NMOS transistor N2 are turned off, and the comparator CMP1 can compare the off currents of the PMOS transistor P1 and the NMOS transistor N2 as in FIG.

  In the off-current measuring circuit 11 of FIG. 3 as well, the resistor RP, the PMOS transistor P1, the resistor RN, and the NMOS transistor N2 may be connected upside down as in FIG.

  FIG. 4 is a diagram illustrating the CMOS control circuit according to the first embodiment. FIG. 5 is a diagram showing a truth table of the CMOS control circuit according to the first embodiment.

  The CMOS control circuit 13 supplies the determination result signal cmpoffz from the off-current measurement circuit 11 and the standby signal stbz from the standby mode control circuit 12 to the input terminals A1 and A2, respectively.

  Then, the CMOS control circuit 13 outputs the first clamp control signal outhx from the output terminal A3 via the NAND gate D1 based on the determination result signal cmpoffz and the standby signal stbz. In addition, the CMOS control circuit 13 outputs the second clamp control signal outlz from the output terminal A4 via the inverters B1, B3 and the NAND gate D2 based on the determination result signal cmpoffz and the standby signal stbz. Further, the CMOS control circuit 13 outputs the clamp signal clmpz from the output terminal A5 via the inverters B2 and B4 based on the standby signal stbz.

  As a result, the standby signal stbz is output as the clamp signal clmpz. Further, during normal operation (stbz = L), the outputs of the NAND gates D1 and D2 are at H level regardless of the potential level of the comparison result signal cmoffz, so that the first clamp control signal outhx is at H level, The clamp control signal outlz is at the L level. On the other hand, in the standby mode (stbz = H), the output of the NAND gate D1 has a potential level opposite to that of the comparison result signal cmoffz, and further has a potential level opposite to that of the output of the NAND gate D2. Both the outx and the second clamp control signal outlz are at a potential level opposite to that of the comparison result signal cmoffz.

  Specifically, the output signals of the CMOS control circuit 13 when the semiconductor integrated circuit 10 is in normal operation (stbz = L) are as follows.

  When the off-current Ioff_n of the NMOS transistor N2 is larger than the off-current Ioff_p of the PMOS transistor P1 (Ioff_n> Ioff_p), the CMOS control circuit 13 has an L-level comparison result signal cmpoffz at the input terminal A1 and an L-level at the input terminal A2. Standby signal stbz is input. As a result, the first clamp control signal outhx is at the H level, the second clamp control signal outlz is at the L level, and the clamp signal clmpz is at the L level (A in FIG. 5).

  When the off-current Ioff_p of the PMOS transistor P1 is larger than the off-current Ioff_n of the NMOS transistor N2 (Ioff_p> Ioff_n), the CMOS control circuit 13 has an input terminal A1 with an H level comparison result signal cmoffz, and an input terminal A2 with an input terminal A2. An L level standby signal stbz is input. As a result, the first clamp control signal outhx is at the H level, the second clamp control signal outlz is at the L level, and the clamp signal clmpz is at the L level (B in FIG. 5).

  That is, when the semiconductor integrated circuit 10 is in normal operation (stbz = L), the first clamp control signal outhx is at the H level and the second clamp control signal outlz is at the L level regardless of the comparison result between the off currents Ioff_p and Ioff_p. , The clamp signal clmpz becomes L level.

  On the other hand, when the semiconductor integrated circuit 10 is in the standby mode (stbz = H), each output signal of the CMOS control circuit 13 is as follows.

  When the off-current Ioff_n of the NMOS transistor N2 is larger than the off-current Ioff_p of the PMOS transistor P1 (Ioff_n> Ioff_p), the CMOS control circuit 13 has an L-level comparison result signal cmpoffz at the input terminal A1 and an H-level at the input terminal A2. Standby signal stbz is input. As a result, the first clamp control signal outhx is at the H level, the second clamp control signal outlz is at the H level, and the clamp signal clmpz is at the H level (C in FIG. 5).

  Further, when the off-current Ioff_p of the PMOS transistor P1 is larger than the off-current Ioff_n of the NMOS transistor N2 (Ioff_p> Ioff_n), the CMOS control circuit 13 has an H-level comparison result signal cmoffz and an input terminal A2 at the input terminal A2. Is supplied with an H level standby signal stbz. As a result, the first clamp control signal outhx becomes L level, the second clamp control signal outlz becomes L level, and the clamp signal clmpz becomes H level (D in FIG. 5).

  That is, when the semiconductor integrated circuit 10 is in the standby mode (stbz = H), the CMOS control circuit 13 determines whether the first clamp control signal outhx of the H level or the L level is set according to the comparison result of the off currents Ioff_p and Ioff_p. The second clamp control signal outlz is output.

  The first clamp control signal outhx, the second clamp control signal outlz, and the clamp signal clmpz output from the CMOS control circuit 13 are supplied to the CMOS logic circuit 14. The CMOS logic circuit 14 performs an operation based on the first clamp control signal outhx, the second clamp control signal outlz, and the clamp signal clmpz, as will be described later.

  FIG. 6 is a diagram illustrating the CMOS logic circuit according to the first embodiment. FIG. 7 is a diagram showing a truth table of the CMOS logic circuit according to the first embodiment.

  6 (1) and 6 (2) show a configuration example of the CMOS logic circuit 14. FIG. The semiconductor integrated circuit 10 replaces the CMOS inverter used in the conventional CMOS logic circuit 14 with the inverter circuit 20 or 21 shown in FIGS. 6A and 6B to reduce the off-current in the standby mode. Then, the inverter circuits 20 and 21 receive the output signal out obtained by inverting the input signal in during normal operation, and the output signal out fixed at the H level or L level based on the comparison result of the off current in the standby mode. Output to.

  FIG. 6A shows a first example of the CMOS logic circuit 14. The inverter circuit 20 included in the CMOS logic circuit 14 of FIG. 6A includes a CMOS transistor C4 that is supplied with an input signal in from the input terminal A10 to the gate and operates as a CMOS inverter, and between the CMOS transistor C4 and the power supply voltage Vdd. It has a PMOS transistor P3, an NMOS transistor N3 between the CMOS transistor C4 and the power supply voltage Vdd, and a CMOS transistor C5 that clamps the output signal out during standby.

  The gate of the PMOS transistor P3 is supplied with the clamp signal clmpz, and the gate of the NMOS transistor N3 is supplied with the clamp signal clmpz via the inverter B10.

  The first clamp control signal outhx is supplied to the gate of the PMOS transistor P5 of the CMOS transistor C5, and the second clamp control signal outlz is supplied to the gate of the NMOS transistor N5.

  When the semiconductor integrated circuit 10 is in a normal operation (stbz = L), the clamp signal clmpz at the L level is input to the input terminal A11 and the first signal at the H level is input to the input terminal A13 regardless of the comparison result of the off currents Ioff_p and Ioff_p. And the second clamp control signal outlz at the L level is input to the input terminal A14.

  As a result, the PMOS transistor P3 and the NMOS transistor N3 are turned on, and the PMOS transistor P5 and the NMOS transistor N5 are turned off. As a result, the input signal in input to the input terminal A10 is inverted by the CMOS transistor C4 and output as the output signal out (A in FIG. 7).

  On the other hand, when the semiconductor integrated circuit 10 is in the standby mode (stbz = H), when the off-current Ioff_n of the NMOS transistor N2 is larger than the off-current Ioff_p of the PMOS transistor P1 (Ioff_n> Ioff_p), the input terminal A11 is at the H level. As for the clamp signal clmpz, the first clamp control signal outhx at the H level is input to the input terminal A13, and the second clamp control signal outlz at the H level is input to the input terminal A14.

  As a result, the PMOS transistor P3 and the NMOS transistor N3 are turned off, and the CMOS transistor C4 is disconnected from the power supply voltage Vdd and the reference voltage GND. In the CMOS transistor C4, the NMOS transistor N5 having a large off-current Ioff_n is turned on, and the PMOS transistor P5 having a small off-current Ioff_p is turned off. As a result, the output signal out of the CMOS transistor C5 is fixed at the L level (B in FIG. 7).

  When the off-current Ioff_p of the PMOS transistor P1 is larger than the off-current Ioff_n of the NMOS transistor N2 (Ioff_p> Ioff_n), the H level clamp signal clmpz is applied to the input terminal A11 and the L level first signal is input to the input terminal A13. And the second clamp control signal outlz at the L level is input to the input terminal A14.

  As a result, the PMOS transistor P3 and the NMOS transistor N3 are turned off, and the CMOS transistor C4 is disconnected from the power supply voltage Vdd and the reference voltage GND. In the CMOS transistor C4, the PMOS transistor P5 having a large off-current Ioff_p is turned on, and the NMOS transistor N5 having a small off-current Ioff_n is turned off. As a result, the output signal out of the CMOS transistor C5 is fixed to the H level (C in FIG. 7).

  As described above, the inverter circuit 20 of FIG. 6A operates as a CMOS inverter using the CMOS transistor C4 when the semiconductor integrated circuit 10 operates normally, and operates as a CMOS inverter using the CMOS transistor C5 when in the standby mode. To do. Further, when the semiconductor integrated circuit 10 is in the standby mode, the inverter circuit 20 turns on a transistor having a large off-current among the PMOS transistor P5 and the NMOS transistor N5 of the CMOS transistor C5 and turns off a transistor having a small off-current. Reduce current.

  In the CMOS logic circuit 14 of FIG. 6A, for example, if the size of the CMOS transistor C4 is increased and the size of the CMOS transistor C5 is decreased, the semiconductor integrated circuit 10 can have a larger size CMOS transistor C4 during normal operation. It can be used to operate at high speed, and the off-state current can be reduced by using the small size CMOS transistor C5 in the standby mode.

  Further, in the CMOS logic circuit 14 of FIG. 6A, a plurality of pairs of CMOS transistors C4 and C5 may share the PMOS transistor P3 and the NMOS transistor N3. Thereby, the areas of the PMOS transistor P3 and the NMOS transistor N3 are not increased more than necessary, and the off-currents of the PMOS transistor P3 and the NMOS transistor N3 can be reduced.

  FIG. 6B shows a second example of the CMOS logic circuit 14. An inverter circuit 21 included in the CMOS logic circuit 14 of FIG. 6B includes an inverter B11 and switches S10 and S11 of the selector 22, and a CMOS transistor C6 that operates as a CMOS inverter by inputting the outputs of the switches S10 and S11 to the gate. Have

  The clamp signal clmpz input to the input terminal A16 is supplied to the gates of the switches S10 and S11 of the selector 22. However, the clamp signal clmpz is supplied to the PMOS gate of the switch S10 and the NMOS gate of the switch S11 via the inverter B11.

  The first clamp control signal outhx input to the input terminal A17 and the input signal in input to the input terminal A18 are supplied to the gate of the CMOS transistor C6 via the switches S10 and S11, respectively.

  When the semiconductor integrated circuit 10 is in a normal operation (stbz = L), the L level clamp signal clmpz is applied to the input terminal A16 and the L level second signal is applied to the input terminal A17 regardless of the comparison result between the off currents Ioff_p and Ioff_p. The clamp control signal outlz is input.

  As a result, the switch S10 is turned off and the switch S11 is turned on. As a result, the input signal in input to the input terminal A18 is inverted by the CMOS transistor C6 and output as the output signal out (A in FIG. 7).

  On the other hand, when the semiconductor integrated circuit 10 is in the standby mode (stbz = H), if the off-current Ioff_n of the NMOS transistor N2 is larger than the off-current Ioff_p of the PMOS transistor P1 (Ioff_n> Ioff_p), the input terminal A16 has an H level. The clamp signal clmpz is input to the input terminal A17, and the second clamp control signal outlz of H level is input to the input terminal A17.

  As a result, the switch S10 is turned on and the switch S11 is turned off. Further, the second clamp control signal outlz at the H level is supplied to the gate of the CMOS transistor C6, the NMOS transistor N6 having a large off current Ioff_n is turned on, and the PMOS transistor P6 having a small off current Ioff_p is turned off. As a result, the output signal out of the CMOS transistor C6 is fixed to the L level (B in FIG. 7).

  Further, when the off-current Ioff_p of the PMOS transistor P1 is larger than the off-current Ioff_n of the NMOS transistor N2 (Ioff_p> Ioff_n), the clamp signal clmpz at the H level is input to the input terminal A16 and the second signal at the L level is input to the input terminal A17. The clamp control signal outlz is input.

  As a result, the switch S10 is turned on and the switch S11 is turned off. Further, the L-level second clamp control signal outlz is supplied to the gate of the CMOS transistor C6, the PMOS transistor P6 having a large off-current Ioff_p is turned on, and the NMOS transistor N6 having a small off-current Ioff_n is turned off. The output signal out of the CMOS transistor C6 is fixed at the H level (C in FIG. 7).

  As described above, in the inverter circuit 21 in FIG. 6B, in the standby mode, the CMOS transistor C4 itself that operates as a CMOS inverter when the semiconductor integrated circuit 10 operates normally turns on a transistor having a large off-current, thereby turning off the off-current. Is turned off to reduce the off-state current.

  In the CMOS logic circuit 14 of FIG. 6B, a plurality of pairs of the switches S10 and S11 and the CMOS transistor C6 may share the inverter B11. Thereby, the circuit area of the CMOS logic circuit 14 does not need to be increased more than necessary.

  FIG. 8 is a timing chart of the semiconductor integrated circuit according to the first embodiment. FIG. 8 shows an output waveform of each signal when the semiconductor integrated circuit 10 is a pseudo SRAM which is a DRAM having an interface compatible with the SRAM as an application example. The pseudo SRAM is a memory that does not receive a refresh command from the outside, and periodically executes a refresh operation inside itself to hold data written in the memory cell.

  The pseudo SRAM semiconductor integrated circuit 10 is activated or deactivated by a chip enable signal / CE supplied from the outside such as a CPU. In FIG. 8, the semiconductor integrated circuit 10 is activated when the chip enable signal / CE is at L level and deactivated when the chip enable signal / CE is at H level. When activated, the pseudo-SRAM semiconductor integrated circuit 10 performs a read operation, a write operation, and the like based on an address (and write data at the time of writing) supplied thereafter.

  The pseudo-SRAM semiconductor integrated circuit 10 internally generates a refresh signal refz periodically (for example, every several μsec) to perform a refresh operation. In FIG. 8, when the refresh signal refz rises to H level, the semiconductor integrated circuit 10 of the pseudo SRAM performs a self-refresh operation.

  During normal operation of the pseudo-SRAM semiconductor integrated circuit 10, the chip enable signal / CE may frequently repeat L level (activation) and H level (deactivation) within a short time (for example, 100 nsec or less). Since the standby control circuit and the CMOS control circuit in the semiconductor integrated circuit 10 consume a current during the switching operation from the normal operation to the standby mode, the pseudo-SRAM semiconductor integrated circuit 10 is generated each time the chip enable signal / CE rises. When switching from the normal operation to the standby mode, the current consumption generated during the switching operation goes against power saving.

  Therefore, in FIG. 8, when the chip enable signal / CE rises from the L level (activation) to the H level (deactivation) and then continues for a predetermined time and remains at the H level, the pseudo-SRAM semiconductor integrated circuit 10 is turned on. The normal operation is switched to the standby mode. Specifically, if the chip enable signal / CE is maintained at the H level between the rise of the chip enable signal / CE and the time after the refresh signal refz rises twice, the semiconductor integrated circuit 10 is in the standby mode. Switch to

  On the other hand, when the chip enable signal / CE changes from H level (deactivation) to L level (activation), an operation command or the like is supplied from the outside immediately after that, so that the semiconductor integrated circuit 10 of the pseudo SRAM is The standby mode is switched to the normal operation in response to the fall of the chip enable signal / CE.

  In FIG. 8, as described above, the standby mode control signal 12 is supplied from the chip enable signal / CE until the refresh signal refz rises twice after the rise (inactivation) of the chip enable signal / CE at time T0. In response to the CE maintaining the H level, the time T1de standby signal stbz is raised to the H level (standby mode).

  When the off-current Ioff_n of the NMOS transistor N2 is larger than the off-current Ioff_p of the PMOS transistor P1 (Ioff_n> Ioff_p), the off-current measurement circuit 11 outputs an L-level comparison result signal cmoffz. Therefore, the clamp signal clmpz and the second clamp control signal outlz output from the CMOS control circuit 13 rise from the L level to the H level in response to the rise of the standby signal stbz at time T1.

  As a result, the CMOS logic circuit 14 is supplied with the clamp signal clmpz at the H level, the first clamp control signal outhx at the H level, and the second clamp control signal outlz at the H level. Then, as described in FIG. 6, the NMOS transistors N5 and N6 having a large off current Ioff_n are turned on, and the PMOS transistors P5 and P6 having a small off current Ioff_p are turned off, thereby reducing the off current.

  When the chip enable signal / CE falls from the H level (deactivation) to the L level (activation) at time T2, the standby mode control signal 12 responds by setting the standby signal stbz to the H level (at time T3). The standby mode is lowered to the L level (normal operation).

  The clamp signal clmpz and the second clamp control signal outlz change from the H level to the L level in response to the standby signal stbz at time T3.

  As a result, an L level clamp signal clmpz, an H level first clamp control signal outhx, and an L level second clamp control signal outlz are supplied to the CMOS logic circuit 14. Then, as described in FIGS. 6A and 6B, the CMOS logic circuit 14 outputs the output signal out obtained by inverting the input signal in.

  On the other hand, when the off-current Ioff_n of the NMOS transistor N2 is larger than the off-current Ioff_p of the PMOS transistor P1 (Ioff_n> Ioff_p), the off-current measurement circuit 11 outputs an H-level comparison result signal cmoffz. Therefore, the clamp signal clmpz and the first clamp control signal outhx output from the CMOS control circuit 13 are respectively changed from L level to H level and from H level to L level in response to the rising of the standby signal stbz at time T1. Become.

  As a result, the CMOS logic circuit 14 is supplied with the clamp signal clmpz at the H level, the first clamp control signal outhx at the L level, and the second clamp control signal outlz at the L level. Then, as described in FIGS. 6A and 6B, the PMOS transistors P5 and P6 having a large off-current Ioff_p are turned on, the NMOS transistors N5 and N6 having a small off-current Ioff_n are turned off, and the off-current is reduced. .

  When the standby mode control signal 12 drops the standby signal stbz from the H level (standby mode) to the L level (normal operation) at time T3, the clamp signal clmpz and the clamp control signal outhx are respectively set to the H level. Changes from L level to L level and from L level to H level.

  As a result, an L level clamp signal clmpz, an H level first clamp control signal outhx, and an L level second clamp control signal outlz are supplied to the CMOS logic circuit 14. Then, as described in FIGS. 6A and 6B, the CMOS logic circuit 14 outputs the output signal out obtained by inverting the input signal in.

  When the semiconductor integrated circuit 10 is an SDRAM, a self-refresh command for instructing a refresh operation is supplied from the outside. This self-refresh command is a command in which the memory controller actively sets the SDRAM to the standby mode. Therefore, in the SDRAM semiconductor integrated circuit 10, it is preferable that the standby mode control circuit 12 sets the standby signal to the H level (standby mode) in response to the self-refresh command. Thereby, the off-current measuring circuit 11, the CMOS control circuit 13, and the CMOS logic circuit 14 of the semiconductor integrated circuit 10 can operate in the same manner as in FIG.

[Second Embodiment]
In the first embodiment, the off-current measuring circuit 11 performs an off-current comparison operation not only in the standby mode of the semiconductor integrated circuit 10 but also in the normal operation, so that an extra current is consumed even in the normal operation. Is done. Therefore, in the second embodiment, the off-current measurement circuit 31 performs the off-current comparison operation only when entering the standby mode in order to reduce the current consumption due to the off-current comparison operation during the normal operation.

  FIG. 9 is a diagram illustrating a semiconductor integrated circuit according to the second embodiment. In addition, about the circuit which overlaps with FIG. 1, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  The semiconductor integrated circuit 30 shown in FIG. 9 is in an operating state in response to the comparison execution signal measz, the standby mode control circuit 12 that outputs the comparison execution signal measz, the latch execution signal latz, and the standby signal stbz, and outputs the comparison result signal cmoffz. The off-current measuring circuit 31 to output, the latch circuit 32 that latches the comparison result signal cmpoffz in response to the latch execution signal latz and outputs the comparison result latch signal cmplatz, and the clamp based on the comparison result latch signal cmplatz and the standby signal stbz A CMOS control circuit 13 that outputs a signal clmpz, a first clamp control signal outhx, and a second clamp control signal outlz, and a CMOS logic circuit 14 are provided.

  In the second embodiment, the standby mode control circuit 12 outputs the comparison execution signal measz to the off-current measuring circuit 31 for a predetermined time ΔT when the semiconductor integrated circuit 20 enters the standby mode. The off-current measuring circuit 31 compares the off-currents of the PMOS transistor and the NMOS transistor in response to the rising edge of the comparison execution signal measz, and outputs the comparison result signal cmpoffz while the comparison execution signal measz is supplied. .

  The standby mode control circuit 12 outputs the latch execution signal latz to the latch circuit 32 after outputting the comparison execution signal measz. The latch circuit 32 latches the comparison result signal cmpoffz output from the off-current measurement circuit 31 in response to the rising of the latch signal latz, and outputs the comparison result latch signal cmplatz to the CMOS control circuit 13.

  The CMOS control circuit 13 has the same configuration as that in FIG. In the second embodiment, the CMOS control circuit 13 is supplied with the comparison result latch signal cmplatz instead of the comparison result signal cmpoffz to the input terminal A1, and based on the comparison result latch signal cmplatz and the standby signal stbz, the clamp signal clmpz. The first clamp control signal outhx and the second clamp control signal outlz are output.

  As in the first embodiment, the CMOS logic circuit 14 performs a normal operation or a standby mode operation based on the clamp signal clmpz, the first clamp control signal outhx, and the second clamp control signal outlz. .

  FIG. 10 is a diagram illustrating an off-current measurement circuit according to the second embodiment. The off-current measuring circuit 31 in FIG. 10 is different from the off-current measuring circuit 11 in FIG. 2 in that the NMOS transistor NS1 (current source transistor) is turned on in response to the comparison execution signal measz between the comparator CMP1 and the reference voltage GND. ) And an NMOS transistor NS2 that is turned on in response to the comparison execution signal measz between the CMOS transistors C1 and C2 and the reference voltage GND. In addition, the same code | symbol is attached | subjected about the location which overlaps with FIG.

  The comparison execution signal measz is supplied to the gates of the NMOS transistors NS1 and NS2. During normal operation, the standby mode control circuit 12 outputs an L level comparison execution signal measz, and the NMOS transistors NS1 and NS2 are turned off. As a result, the comparator CMP1 is disconnected from the reference voltage GND, and no current is supplied to the comparator CMP1. Also, the CMOS transistors C1 and C2 are disconnected from the reference voltage GND. For this reason, the comparison operation of the comparator CMP1 is not performed, and the current consumption during the normal operation is reduced.

  On the other hand, in the standby mode, the standby mode control circuit 12 outputs the H level comparison execution signal measz for a predetermined time ΔT, and the NMOS transistors NS1 and NS2 are turned on. As a result, the off-current is compared for a predetermined time ΔT, and the comparison result signal cmpoffz is output to the latch circuit 32.

  FIG. 11 is a timing chart of the semiconductor integrated circuit according to the second embodiment. FIG. 11 shows the output waveform of each signal when the semiconductor integrated circuit 10 is a pseudo SRAM, as in FIG.

  At time T0, the chip enable signal / CE rises from the L level (activation) to the H level (inactivation). The standby mode control signal 12 changes the comparison execution signal measz from the L level to the H level at time T1 in response to the refresh signal refz rising twice and the chip enable signal / CE maintaining the H level. To do.

  Since the off-current measuring circuit 11 is supplied with the L-level comparison execution signal measz until time T1 and does not compare the off-current, the comparison result signal cmpoffz is indefinite (shaded portion). Then, the off-current measuring circuit 11 compares the off-current in response to the rise of the comparison execution signal measz at time T1, and when the off-current of the NMOS transistor N2 is larger than the off-current of the PMOS transistor P1 (Ioff_n > Ioff_p) is an L level comparison result signal cmpoffz (solid line). When the off current of the PMOS transistor P1 is larger than the off current of the NMOS transistor N2 (Ioff_p> Ioff_n), the H level comparison result signal cmpoffz (dashed line) ) Is output.

  Next, the standby mode control signal 12 raises the latch execution signal latz from the L level to the H level at time T2. The latch circuit 32 latches the comparison result signal cmpoffz in response to the rise of the latch execution signal latz, and outputs the comparison result latch signal cmplatz at the L level (Ioff_n> Ioff_p, solid line) or the H level (Ioff_p> Ioff_n, broken line). Output.

  The standby mode control signal 12 causes the comparison execution signal measz and the latch execution signal latz to fall from the H level to the L level at a time T3 when a predetermined time ΔT has elapsed from the time T2. The off-current measuring circuit 11 ends the off-current comparison at the falling edge of the comparison execution signal measz. As a result, the comparison result signal cmpoffz becomes indefinite (hatched) again.

  Then, the standby mode control signal 12 raises the standby signal stbz from L level (normal operation) to H level (standby mode) at time T4. Based on the H level standby signal stbz and the H level or L level comparison result latch signal cmplatz, the CMOS control circuit 13 performs the clamp signal clmpz, the first clamp control signal, and the second clamp signal as in FIG. A control signal outlz is output.

  That is, when the off current of the NMOS transistor N2 is larger than the off current of the PMOS transistor P1 (Ioff_n> Ioff_p), the H level clamp signal clmpz, the H level first clamp control signal, and the H level second clamp signal A clamp control signal outlz is output. As a result, in the CMOS logic circuit 14, the NMOS transistors N5 and N6 having a large off current are turned on, and the PMOS transistors P5 and P6 having a small off current are turned off, thereby reducing the off current in the standby mode.

  On the other hand, when the off current of the PMOS transistor P1 is larger than the off current of the NMOS transistor N2 (Ioff_p> Ioff_n), the clamp signal clmpz at the H level, the first clamp control signal at the L level, and the second clamp at the H level. A control signal outlz is output. As a result, in the CMOS logic circuit 14, the PMOS transistors P5 and P6 having a large off current are turned on, the NMOS transistors N5 and N6 having a small off current are turned off, and the off current in the standby mode is reduced.

  When the chip enable signal / CE falls from H level (deactivation) to L level (activation) at time T5, the standby mode control signal 12 responds to this without waiting for the generation of the refresh signal refz at time T6. The standby signal stbz is lowered from the H level (standby mode) to the L level (normal operation). The CMOS control circuit 13 responds to the falling edge of the standby signal stbz in the same manner as in FIG. 8, and receives the L level clamp signal clmpz, the H level first clamp control signal, and the L level second clamp control signal outlz. Output. As a result, the CMOS logic circuit 14 performs a normal operation by the CMOS inverter of the CMOS transistors C4 and C6.

  As described above, in the second embodiment, the off-current measurement circuit 31 compares the off-currents of the PMOS transistor and the NMOS transistor at that time and outputs the comparison result signal cmoffs in a short time when entering the standby mode. . Then, in the standby mode, the CMOS control circuit 13 uses the latched comparison result signal (comparison result latch signal cmplatz) and the H level standby signal stbz, and the PMOS transistors P5 and P6 and the NMOS transistor N5 of the CMOS logic circuit 14. , N6 are controlled on and off. During the normal operation, the off-current measuring circuit 31 is not operated. Thereby, the off current of the CMOS logic circuit 14 in the standby mode can be reduced, and the current consumption by the off current comparison operation in the normal operation can be reduced.

  The above embodiment is summarized as follows.

(Appendix 1)
A first P-channel transistor provided between a first power supply line to which a first voltage is applied and a predetermined node; a second voltage lower than the predetermined node and the first voltage; A CMOS logic circuit having a first N-channel transistor provided between a given second power supply line;
An off current that compares the first off current of the second P-channel transistor in the off state with the second off current of the second N-channel transistor in the off state and outputs a comparison result signal A measurement circuit;
When entering the standby mode, based on the latest comparison result signal, if the first off-current is larger than the second off-current, the first P-channel transistor is turned on and the first off-current is turned on. When the N-channel transistor is turned off and the second off-current is larger than the first off-current, the first P-channel transistor is turned off and the first N-channel transistor is turned on. A semiconductor integrated circuit.

(Appendix 2)
In Appendix 1,
The off-current measuring circuit includes a first resistor and the second P-channel transistor connected in series, a second resistor and the second N-channel transistor connected in series, and the first resistor. And the second connection voltage between the second P-channel transistor and the second connection voltage between the second resistor and the second N-channel transistor. A semiconductor integrated circuit having a comparator for outputting a signal.

(Appendix 3)
In Appendix 1,
The off-current measurement circuit is activated by being supplied with a comparison execution signal when entering the standby mode, and outputs the comparison result signal for a predetermined period of time.
The control circuit latches the comparison result signal when entering the standby mode, and when the first off-current is larger than the second off-current based on the latched comparison result signal, the control circuit When one P-channel transistor is turned on and the first N-channel transistor is turned off, and the second off-current is larger than the first off-current, the first P-channel transistor is turned on. A semiconductor integrated circuit which is turned off to turn on the first N-channel transistor.

(Appendix 4)
In Appendix 3,
The off-current measuring circuit includes a first resistor and the second P-channel transistor connected in series, a second resistor and the second N-channel transistor connected in series, and the first resistor. And the second connection voltage between the second P-channel transistor and the second connection voltage between the second resistor and the second N-channel transistor. A comparator that outputs a signal; and a current source transistor that supplies current to the comparator,
The current source transistor is a semiconductor integrated circuit which is turned on when the comparison execution signal is supplied to the gate for the predetermined period.

(Appendix 5)
In Appendix 1,
Further, the CMOS logic circuit has a CMOS inverter that inverts an input signal and outputs an output signal to the predetermined node between the first power supply line and the second power supply line,
In the normal operation, the control circuit turns off the first P-channel transistor and the first N-channel transistor, and connects the CMOS inverter to the first power supply line and the second power supply line. In the standby mode, the semiconductor integrated circuit disconnects the connection between the first power supply line and the second power supply line and the CMOS inverter.

(Appendix 6)
In Appendix 1,
The CMOS logic circuit includes a CMOS inverter having the first P-channel transistor and the first N-channel transistor, and a selector that selects either an input signal or a control signal and outputs the selected signal to the CMOS inverter. And
The control circuit causes the selector to select the input signal in a normal operation, outputs the control signal based on the comparison result signal in the standby mode, causes the selector to select the control signal, and When the first off-current is larger than the second off-current, the first P-channel transistor is turned on, the first N-channel transistor is turned off, and the second off-current is A semiconductor integrated circuit in which the first P-channel transistor is turned off and the first N-channel transistor is turned on when larger than the first off-state current.

(Appendix 7)
In Appendix 1,
In the standby mode, the control circuit outputs a control signal corresponding to the comparison result signal to the CMOS logic circuit, and among the first P-channel transistor and the first N-channel transistor, the off-current A semiconductor integrated circuit which turns on a transistor having a larger current and turns off a transistor having a smaller off current.

(Appendix 8)
In Appendix 1,
A semiconductor integrated circuit in which off currents of the P-channel transistor and the N-channel transistor have manufacturing variations.

(Appendix 9)
In Appendix 1,
A semiconductor integrated circuit in which off currents of the P-channel transistor and the N-channel transistor vary depending on the temperatures of the P-channel transistor and the N-channel transistor, respectively.

cmpoffz: comparison result signal cmplatz: comparison result latch signal clmpz: clamp signal latz: latch signal measz: comparison execution signal outhx: first clamp control signal outlz: second clamp control signal stbz: standby signal GND: reference voltage Vdd: Power supply voltages Ioff_p, Ioff_n: OFF currents B1 to B4, B10, B11: Inverters C1 to C6: CMOS transistors CMP1: Comparators D1, D2: NAND gates N1 to N6, NS1, NS2: NMOS transistors P1 to P6: PMOS transistors RP , RN: resistors S10, S11: switches

Claims (6)

A first P-channel transistor provided between a first power supply line to which a first voltage is applied and a predetermined node; a second voltage lower than the predetermined node and the first voltage; A CMOS logic circuit having a first N-channel transistor provided between a given second power supply line;
An off current that compares the first off current of the second P-channel transistor in the off state with the second off current of the second N-channel transistor in the off state and outputs a comparison result signal A measurement circuit;
When entering the standby mode, based on the latest comparison result signal, if the first off-current is larger than the second off-current, the first P-channel transistor is turned on and the first off-current is turned on. When the N-channel transistor is turned off and the second off-current is larger than the first off-current, the first P-channel transistor is turned off and the first N-channel transistor is turned on. A semiconductor integrated circuit. In claim 1,
The off-current measuring circuit includes a first resistor and the second P-channel transistor connected in series, a second resistor and the second N-channel transistor connected in series, and the first resistor. And the second connection voltage between the second P-channel transistor and the second connection voltage between the second resistor and the second N-channel transistor. A semiconductor integrated circuit having a comparator for outputting a signal. In claim 1,
The off-current measurement circuit is activated by being supplied with a comparison execution signal when entering the standby mode, and outputs the comparison result signal for a predetermined period of time.
The control circuit latches the comparison result signal when entering the standby mode, and when the first off-current is larger than the second off-current based on the latched comparison result signal, the control circuit When one P-channel transistor is turned on and the first N-channel transistor is turned off, and the second off-current is larger than the first off-current, the first P-channel transistor is turned on. A semiconductor integrated circuit which is turned off to turn on the first N-channel transistor. In claim 3,
The off-current measuring circuit includes a first resistor and the second P-channel transistor connected in series, a second resistor and the second N-channel transistor connected in series, and the first resistor. And the second connection voltage between the second P-channel transistor and the second connection voltage between the second resistor and the second N-channel transistor. A comparator that outputs a signal; and a current source transistor that supplies current to the comparator,
The current source transistor is a semiconductor integrated circuit which is turned on when the comparison execution signal is supplied to the gate for the predetermined period. In claim 1,
Further, the CMOS logic circuit has a CMOS inverter that inverts an input signal and outputs an output signal to the predetermined node between the first power supply line and the second power supply line,
In the normal operation, the control circuit turns off the first P-channel transistor and the first N-channel transistor, and connects the CMOS inverter to the first power supply line and the second power supply line. In the standby mode, the semiconductor integrated circuit disconnects the connection between the first power supply line and the second power supply line and the CMOS inverter. In claim 1,
The CMOS logic circuit includes a CMOS inverter having the first P-channel transistor and the first N-channel transistor, and a selector that selects either an input signal or a control signal and outputs the selected signal to the CMOS inverter. And
The control circuit causes the selector to select the input signal in a normal operation, outputs the control signal based on the comparison result signal in the standby mode, causes the selector to select the control signal, and When the first off-current is larger than the second off-current, the first P-channel transistor is turned on, the first N-channel transistor is turned off, and the second off-current is A semiconductor integrated circuit in which the first P-channel transistor is turned off and the first N-channel transistor is turned on when larger than the first off-state current.

Images