JP2001147746A - Power supply circuit for microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a power supply circuit for a microcomputer, capable of reducing current consumption of a microcomputer built in a VDC circuit. SOLUTION: The current consumption of a peripheral circuit which is not required to be driven, can be suppressed by suppressing the current consumption due to the leakage of a current from a VDC circuit of a power supply circuit, corresponding to the peripheral circuit which does not require supply of dropped power supply voltage by switching circuits 11, 12, and also the current consumption of the microcomputer can be suppressed further by removing current leakage from the VDC circuit, corresponding to the peripheral circuit not required to be driven.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power supply circuit of a microcomputer, and more particularly to a power supply circuit of a microcomputer having a power supply voltage dropping circuit.

[0002]

2. Description of the Related Art With the miniaturization of the process rules of microcomputers, the on-breakdown voltage of transistors used in microcomputer internal circuits cannot be ensured by the conventional 5V system. Power supply voltage drop circuit (Volta
Ge Down Converter: hereinafter referred to as a VDC circuit) and an external 5 V system incorporating a level shift circuit.
Internal 3V systems are widespread.

According to this, the voltage applied to each terminal from the outside is a 5 V system as before, but the VDC circuit reduces the power supply voltage of 5 V applied from the outside, and the level shift circuit converts the level of the input signal. Therefore, the internal operation is based on a 3V power supply voltage.

FIG. 9 is a circuit diagram showing a configuration of a VDC circuit 100 used in a power supply circuit of such a conventional microcomputer (hereinafter referred to as a microcomputer). In the figure, reference numeral 1 denotes a VREF operational amplifier block which performs comparison for generating a reference voltage and generating a lowered 3V power supply voltage, 2 denotes a 5V power supply voltage (hereinafter referred to as an external VDD) inputted from outside the microcomputer, and 3 Is a P-channel transistor (hereinafter, referred to as PchTr) for stepping down the external system VDD2 and supplying a 3V system power supply voltage, and 4 is a group of resistors for stepping down the voltage, and applying a feedback to the VREF operational amplifier block 1 to perform fine voltage control. It is intended to be implemented. Reference numeral 5 denotes a power supply line for outputting a 3V power supply voltage (hereinafter referred to as a drop power supply voltage VD) supplied to the microcomputer internal circuit, and 7 denotes a ground.

Next, the operation will be described. VDC circuit 1
00, the external system VDD2 applied from the outside is
3 and the resistor group 4 to drop the power supply voltage V
D is output to the power supply line 5. Further, a feedback signal for stably obtaining the drop power supply voltage VD is connected to the VREF operational amplifier block 1 from the resistor group 4.

By incorporating such a VDC circuit 100, blocks mainly using an external power supply voltage, such as a port driver, and a block mainly using a reduced power supply voltage VD can be used.
A power supply voltage is separately supplied to a block of an internal circuit such as a PU. In this case, since the power supply voltage supplied from the VDC circuit 100 to the inside of the microcomputer is generally one type, the power supply voltage is supplied to all the blocks inside the microcomputer even during standby or the like.

[0007]

Since the power supply circuit of the conventional microcomputer is configured as described above,
Since the VDC circuit 100 supplies the power supply voltage to all the blocks inside the microcomputer even during standby, there is a problem that static characteristics of the microcomputer, particularly current consumption during standby, cannot be reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a microcomputer power supply circuit capable of reducing current consumption in a microcomputer having a built-in VDC circuit.

[0009]

A power supply circuit of a microcomputer according to the present invention is provided for each internal peripheral circuit, and steps down an external power supply voltage to generate a step-down power supply voltage to be supplied to a corresponding internal peripheral circuit. VDC circuit, a leakage current reduction circuit provided for each VDC circuit for reducing the leakage current of the VDC circuit, and the power supply from the VDC circuit to a corresponding internal peripheral circuit provided for each VDC circuit. Corresponds to a switch circuit for supplying and stopping a voltage, and an internal peripheral circuit in which the supply and the supply of the lowered power supply voltage generated by the VDC circuit are stopped and the supply of the reduced power supply voltage is stopped. Control means for controlling the reduction of leakage current by the leakage current reduction circuit. A.

A power supply circuit for a microcomputer according to the present invention supplies a reduced power supply voltage generated by a VDC circuit,
A VDC control register for outputting a control signal corresponding to the VDC circuit for controlling supply stop and reduction of leakage current of a VDC circuit corresponding to an internal peripheral circuit to which supply of the drop power supply voltage is stopped. It was made.

The power supply circuit of the microcomputer according to the present invention is configured to stop the supply of the reduced power supply voltage generated by the VDC circuit during standby and to supply the VDC circuit corresponding to the internal peripheral circuit where the supply of the reduced power supply voltage is stopped. In order to reduce the leakage current, a priority circuit is provided which outputs a control signal which has priority over a control signal output from the VDC control register.

According to another aspect of the present invention, there is provided a power supply circuit for a microcomputer, comprising: a plurality of internal peripheral circuits to which a common power supply voltage is supplied; Based on a control signal output from a VDC control register corresponding to a VDC circuit that supplies the lowered power supply voltage to a plurality of internal peripheral circuits, supply and stop of the supply of the lowered power supply voltage generated by the VDC circuit are performed. Power supply control means for controlling each of the plurality of internal peripheral circuits.

A power supply circuit for a microcomputer according to the present invention is provided with a bit for supplying and stopping supply of a reduced power supply voltage during execution of a standby instruction to each port latch circuit block to which a common reduced power supply voltage is supplied as an internal peripheral circuit. A block selection register in which data is set, the bit data set in the block selection register, and a VDC control register corresponding to a VDC circuit that supplies a drop power supply voltage to an internal peripheral circuit that is the port latch circuit block. A power supply control signal generation circuit for generating a port latch power supply control signal based on the output control signal; and supplying and stopping supply of the lowered power supply voltage generated by the VDC circuit to each of the port latch circuit blocks. Each port latch circuit block is controlled based on the port latch power control signal. Performed for each click, the is obtained so as to include a switch circuit provided corresponding to each port latch circuit block.

According to the power supply circuit of the microcomputer according to the present invention, a reset signal output at the time of resetting, setting data for supply and stop of the supply of the reduced power supply voltage at the time of the reset for each of the internal peripheral circuits, A reset power supply control circuit for controlling supply of a reduced power supply voltage to a desired internal peripheral circuit at the time of resetting based on a signal defining a predetermined mode to be executed, and supply stop. is there.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 shows a power supply voltage drop circuit (hereinafter referred to as VD
FIG. 2 is a circuit diagram showing a power supply circuit of the microcomputer according to the first embodiment (hereinafter, referred to as a microcomputer) including a C circuit. In the figure, 1 is the generation of a reference voltage,
A VREF operational amplifier block for performing a comparison for generating a 3V system power supply voltage.
V system power supply voltage (hereinafter referred to as external system VDD), 3 is external system V
A P-channel transistor (hereinafter, referred to as PchTr) 4 that steps down DD2 and supplies a 3V power supply voltage (hereinafter, referred to as dropped power supply voltage VD), 4 is a group of resistors for stepping down the voltage, and feeds back to the VREF operational amplifier block 1 To perform fine voltage control. Reference numeral 5 denotes a power supply line for outputting a drop power supply voltage VD supplied to each peripheral circuit (not shown) inside the microcomputer, and 7 denotes a ground.

6a, 6b and 6c are switch circuits,
This is for turning on / off the supply of the power supply voltage to each peripheral circuit inside the microcomputer. The supply of the drop power supply voltage VD to each peripheral circuit inside the microcomputer and the stop of the supply are control signals OFF0, OFF1,. Controlled by OFFn.

Reference numeral 8a denotes a drop power supply voltage line of a peripheral circuit of the microcomputer whose supply and stop of the supply of the drop power supply voltage VD are controlled by the switch circuit 6a, and 8b denotes a switch circuit 6b
The supply and stop of the supply of the reduced power supply voltage VD1 are controlled by the reduced supply voltage line of another peripheral circuit of the microcomputer;
Reference numeral 8c denotes a falling power supply voltage line of still another peripheral circuit whose supply and stop of the supply of the falling power supply voltage VDn are controlled by the switch circuit 6c.

In the switch circuits 6a, 6b and 6c, the drop power supply voltages VD0 and VD0 to the peripheral circuits inside the microcomputer are provided.
D1,... VDn are supplied by control signals OFF0, Of.
.. 8c are connected to the side of the power supply line 5, respectively. Further, the falling power supply voltages VD0, VD1,. The supply of VDn is stopped by activating the control signals OFF0, Off1,..., Offn so that the power supply voltage lines 8a, 8b,.
8c is connected to the ground 7 side.

Next, the operation will be described. The voltage of the external system VDD2 applied from the outside is reduced by the PchTr 3 and the resistor group 4, and the lowered power supply voltage VD is output to the power supply line 5. Further, a feedback signal for stably obtaining the drop power supply voltage VD is returned from the resistor group 4 to the VREF operational amplifier block 1. The power supply line 5 from which the drop power supply voltage VD is output from the VREF operational amplifier block 1
Power supply voltage VD0, VD is supplied to each peripheral circuit inside the microcomputer.
.. 8c for supplying VDn, each of which is switched by switch circuits 6a, 6b,. ..Connected or disconnected with 8c.

For this reason, at the time of standby, for example, the internal circuit to which the power supply voltage VD0 is supplied as a power supply is operated, and other internal circuits are not operated without supplying the power supply voltage, thereby suppressing current consumption at the time of standby. In this case, the control signal OFF0 remains inactive during standby, and the control signals Off1,... Offn are activated to switch the drop power supply voltages VD1 to VDn to the ground level. It is possible not to supply the voltage itself.

As described above, according to the first embodiment, switch circuits 6a, 6b,... 6c are controlled by control signals Off0, Off1,. By doing so, it is possible to cut off the power supply to the internal circuit that does not require power supply, and thus it is possible to obtain a power supply circuit of a microcomputer that can reduce static characteristics of the microcomputer, particularly, current consumption during standby.

Embodiment 2 FIG. FIG. 2 is a circuit diagram showing a configuration of a power supply circuit of a microcomputer according to the second embodiment including a VDC circuit. 2, the same or corresponding parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In the figure, reference numeral 9a denotes a first power supply circuit for supplying a reduced power supply voltage VD0 to peripheral circuits inside the microcomputer, and 9b similarly designates a reduced power supply voltage VD1 to another peripheral circuit inside the microcomputer.
The second power supply circuit 9c is an n-th power supply circuit that similarly supplies the reduced power supply voltage VDn to another peripheral circuit inside the microcomputer. 6 is VD of the first power supply circuit 9a.
This is a switch circuit for controlling whether or not the falling power supply voltage VD generated by the C circuit is supplied to the falling power supply voltage line 8a by a control signal OFF0. Note that other power supply circuits (second power supply circuit,..., Nth power supply circuit) are provided with switch circuits having the same configuration. Also, Off0,
Offn are control signals for controlling each switch circuit 6 for an internal circuit that does not require power supply during standby, as in the first embodiment.

As described above, in the second embodiment, the power supply circuit composed of the switch circuit and the VDC circuit that can control the supply and stop of the supply of the reduced power supply voltage is individually provided for each peripheral circuit inside the microcomputer. Is provided.

Next, the operation will be described. In the power supply circuit of the microcomputer according to the second embodiment, the power supply circuits 9a, 9b, and 9c each including a VDC circuit provided for each peripheral circuit inside the microcomputer and the switch circuit 6 provide the peripheral circuit with respect to each peripheral circuit. The drop power supply voltage VD0,
VD1,... VDn supply and supply stop are individually controlled. Power supply voltage drop for each peripheral circuit inside microcomputer
Stopping the supply of D0, VD1,..., VDn can be performed independently by activating the control signals OFF0 to OFFn as in the first embodiment.

As described above, since the VDC circuit is provided for each peripheral circuit, each of the power supply circuits 9a, 9b,.
9c is responsible for only the corresponding peripheral circuit as a load, so that the control load of each power supply circuit is reduced as compared with the power supply circuit of the microcomputer of the first embodiment, and the control load for controlling the falling power supply voltage is reduced. An improvement in accuracy can be expected.

As described above, according to the second embodiment, a power supply circuit is provided for each peripheral circuit, and the drop power supply voltage VD0, VD0 to the peripheral circuit corresponding to each power supply circuit is provided.
Since VD1,... VDn supply and supply stop can be controlled for each power supply circuit by the switch circuit 6 of each power supply circuit, power to an internal circuit that does not require power supply can be cut off. In addition to reducing the static characteristics of the microcomputer, particularly the current consumption during standby, the control load of each VDC circuit can be reduced, and the power supply circuit of the microcomputer that can improve the accuracy in controlling the power supply voltage drop can be obtained.

Embodiment 3 FIG. 3 shows the third embodiment.
1 is a circuit diagram showing a configuration of a power supply circuit of a microcomputer according to the present invention. 3, the same or corresponding parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 3, reference numeral 10a denotes a first power supply circuit for supplying a reduced power supply voltage VD0 to peripheral circuits inside the microcomputer, and 10b similarly denotes a second power supply circuit for supplying a reduced power supply voltage VD1 to another peripheral circuit inside the microcomputer. Similarly, it is an n-th power supply circuit for supplying the reduced power supply voltage VDn to another peripheral circuit inside the microcomputer.

Reference numeral 11 denotes a switch circuit (leakage current reducing circuit) arranged in a feedback circuit between the resistor group 4 and the VREF operational amplifier block 1 in the VDC circuit of the first power supply circuit 10a. A portion for extracting the feedback signal of the resistor group 4 is connected to the VREF operational amplifier block 1 so that the compressed feedback signal is supplied to the VREF operational amplifier block 1. When the control signal OFF0 becomes active, the feedback circuit is activated. The input side of the VREF operational amplifier block 1 to which the feedback signal is supplied is connected to the external system VDD2.

Reference numeral 12 denotes a switch circuit (leakage current reducing circuit) disposed between the output terminal of the VREF operational amplifier block 1 of the first power supply circuit 10a and the gate of the PchTr3.
Normally, the output of the VREF operational amplifier block 1 is supplied to the gate of the PchTr 3 so that the PchTr
3 and the output terminal of the VREF operational amplifier block 1, and when the control signal OFF0 becomes active, the connection between the gate of the PchTr3 and the output terminal of the VREF operational amplifier block 1 is cut off,
The third gate is connected to the external system VDD2 to eliminate the occurrence of a leak current from the external system VDD2 to the ground 7 via the PchTr3 and the resistor group 4.

The VDC circuits other than the first power supply circuit 10a are provided with switch circuits 11 and 12 having the same configuration.

Next, the operation will be described. When, for example, only the drop power supply voltage VD0 is supplied to the peripheral circuit of the corresponding microcomputer during standby, the control signal OFF0 is made inactive, and the other control signals OFF1,.
n is activated, the output of the VREF operational amplifier block 1 is supplied to the gate of the PchTr 3 by the switch circuit 12 of the VDC circuit of the first power supply circuit 10a, and the feedback circuit between the resistor group 4 and the VREF operational amplifier block 1 provides feedback. Signal to VRE
It is supplied to the F operational amplifier block 1.

At this time, another control signal OFF1.
.. OFFn is active and the second power supply circuit 10b
... In the nth power supply circuit 10c, the gate of the PchTr3 is connected to the external system VDD2 by the switch circuit 12 of each VDC circuit.
And VREF by the switch circuit 11.
The input side of the feedback signal of the operational amplifier block 1 is connected to the external system VDD2.

As a result, in the other power supply circuits except the first power supply circuit 10a, the PchTr3 is turned off, the output side of the VREF operational amplifier block 1 to the gate of the PchTr3 is opened, and the VREF operational amplifier block 1 is opened. The input side of the feedback signal of
The state is pulled up to DD2, and the falling power supply voltage V
In a power supply circuit that supplies D1.
3 and the external system VDD2 to the ground 7 through the resistor group 4.
Since the current leaking to the microcomputer and the current leaking in the VREF operational amplifier block 1 are suppressed, the current consumption can be further reduced as compared with the power supply circuit of the microcomputer of the second embodiment.

As described above, according to the third embodiment, the switching circuits 11 and 12 further suppress the current consumption due to the leakage in the VDC circuit of the power supply circuit corresponding to the peripheral circuit that does not need to supply the drop power supply voltage. Therefore, there is an effect that a power supply circuit of a microcomputer which can further reduce current consumption can be obtained.

Embodiment 4 FIG. FIG. 4 is a block diagram showing a circuit configuration around a VDC control register for generating the control signals OFF0, OFF1,... OFFn used in the first, second, and third embodiments. It is. In the figure, reference numeral 29 denotes a central processing unit (hereinafter referred to as a CPU) as control means, 20 an address decoder, 21 a VDC in which bits corresponding to each peripheral circuit are stored.
The VDC control register 21 is a readable / writable bit.
After reset release, all become "0" (inactive).

Reference numeral 22 denotes an address bus in the microcomputer, reference numeral 23 denotes a data bus in the microcomputer, and reference numeral 24 denotes a signal line for outputting an STP command signal from the CPU 29. 25 is a control signal OF
A signal line from which Fn is output, and 26 is a control signal OFFn-1
Is a signal line from which the control signal OFF0 is output. Reference numeral 27 denotes a two-input OR gate (priority circuit) that outputs a control signal OFFn-1,..., A control signal OFF0 based on the bit output set in the VDC control register 21 and the STP command signal. In addition,
In the fourth embodiment, the control signal OFFn is V
The bit set in the DC control register 21 is output as it is as a control signal.

Next, the operation will be described. According to the circuit configuration around the VDC control register 21, the control signals OFF0 to OFFn for controlling the supply and the stop of the supply of the drop power supply voltages VD0 to VDn to the respective peripheral circuits described in the first to third embodiments are provided. Generate. For example, a control signal OFFn to be supplied to a power supply circuit corresponding to a peripheral circuit which is known not to be used after reset release is activated so as not to supply the lowered power supply voltage. In this case, the following operation is performed. Become.

That is, the CPU 29 outputs the address of the VDC control register 21 to the address bus 22, and the address decoder 20 decodes the address output to the address bus 22 and outputs a write signal to the VDC control register 21. . Further, the CPU 29 outputs data to the data bus 23 in which only the bit n corresponding to the peripheral circuit that is known not to be used after the reset is released is “1”. As a result, "1" is set at the position of bit n of the register 21 in synchronization with the write signal from the address decoder 10.
However, '0' is written in other bit positions.

As a result, the level of the corresponding control signal OFFn becomes "1" (active), and the switch circuit 6c in the first embodiment corresponding to the peripheral circuit which is known not to be used, and the second embodiment corresponds to the second embodiment. In the third embodiment, the switch circuit 6 of the power supply circuit 9c is used.
The switch circuits 6, 11, and 12 of 0c are switched as described in the first embodiment to the third embodiment, and the supply of the drop power supply voltage VDn to the peripheral circuit is stopped.

Further, when a standby instruction for stopping the operation of the peripheral circuit, for example, an STP instruction or the like is executed, a peripheral circuit necessary for recovery (in this case, a peripheral circuit which is provided by the power supply circuit to which the control signal OFFn is supplied) is provided. Except for all, the supply of the drop power supply voltage can be stopped. This is realized by the two-input OR circuit 27 shown in FIG. 4. In this case, when the STP instruction is executed, the STP instruction signal is output from the CPU 29 to the signal line 24. Then, a two-input OR gate 27 to which a control signal (“0” and non-active) for supplying a drop power supply voltage is supplied to one input terminal.
, The control signal OFFn-1... The control signal OFF0.
To “1”, that is, active, and the control signal OFFn
-1... Forcibly stop the supply of the falling power supply voltage to each peripheral circuit that is provided by the power supply circuit to which the control signal OFF0 is supplied. In this case, the two-input OR gate 27 is not provided on the signal line 25 from which the control signal OFFn for supplying the lowered power supply voltage to the peripheral circuit necessary for the return is provided, and the control signal OFFn remains inactive. .

As described above, according to the fourth embodiment, the control signals OFF0, OFF1,..., OFFn are generated by using the circuit configuration around the VDC control register, so that they are not used after reset release. A power supply circuit of a microcomputer that can suppress a current consumption value in a known peripheral circuit, a leakage current value in a VDC circuit corresponding to the peripheral circuit, and reduce a current consumption value as a static characteristic of a microcomputer during execution of a standby instruction. There is an effect that can be obtained.

Embodiment 5 FIG. FIG. 5 shows the fifth embodiment.
FIG. 2 is a block diagram showing a configuration around a port latch circuit which is a part of a power supply circuit of the microcomputer of FIG. In the figure, reference numeral 38 denotes a switch circuit for supplying and stopping the supply of a drop power supply voltage to an adjacent port latch circuit block 39 based on a port latch power supply control signal; 39, the port latch circuit block (internal peripheral circuit); Is the power supply voltage drop line 8c shown in FIG. 1 of the first embodiment, FIG. 2 of the second embodiment, or FIG. 3 of the third embodiment.
Is a power supply line to which a reduced power supply voltage for the port latch circuit block 39 is supplied. Reference numeral 41 denotes a signal line from which the port latch power control signal for controlling the supply of the drop power supply voltage from the power supply line 40 to each port latch circuit block 39 is output. This port latch power control signal is output to each switch circuit 38.

FIG. 6 shows the port latch power control signal *
A port latch power supply control signal generation circuit that generates OFF0 to * OFFn based on, for example, the control signal OFFn illustrated in FIG. 4 described in the fourth embodiment and the bit data set in the block selection register 32. In the figure, 31 is an address decoder, 32 is a block selection register (power control means), and 33, 34 and 35 are two-input ANDs.
It is a gate (power control means, power control signal generation circuit).

Next, the operation will be described. By arranging the respective port latch circuit blocks 39 as one block inside the microcomputer, the power supply line 40 for supplying the lowered power supply voltage to the port latch circuit block 39 is configured as shown in FIG.
You can lay out like this. Therefore, the switch circuit 3 is provided between each port latch circuit block 39.
8 as port switch power control signals * OFF0 to * OFF as switch switching signals of the switch circuit 38.
n is used.

Then, the port latch power supply control signal * OF
Unlike the fourth embodiment, F0 to * OFFn are codes obtained by combining the port latch power control signals * OFF0 to * OFFn as bits for the supply of the drop power supply voltage from the power supply line 40 to each port latch circuit block 39. (In this case, each switch circuit 38 requires a decoder for decoding the code.) Or, each port latch power control signal * OFF0 *
It is configured to be controllable by OFFn.

In the following description, the latter case is described as an example, and the port latch power control signals * OFF0 to * OFF
When OFFn is “1”, the switch circuit 38 to which the port latch power control signal is input is connected to the power supply line 40.
Block the supply of the drop power supply voltage to the corresponding port latch circuit block 39.

The CPU 29 shown in FIG. 4 outputs the address of the block selection register 32 shown in FIG. 6 to the address bus 22, and the address decoder 31
The address output to the block selector 32 is decoded, and a write signal is output to the block selection register 32. Also, the CPU 29
Outputs data to the data bus 23 in which only the bit corresponding to the port latch circuit block 39 that does not supply the falling power supply voltage during execution of the standby instruction is “1”. As a result, in synchronization with the write signal from the address decoder 31, "1" is set at a bit position of the block selection register 32 corresponding to the port latch circuit block 39 that does not supply the falling power supply voltage during execution of the standby instruction, '0' is written in other bit positions.

The bit data written into the block selection register 32 is a two-input AND gate 33, 34,.
... AND operation with the control signal OFFn is performed at 35.

The control signal OFFn in this case is a signal applied to the power supply circuit 9c of the second embodiment shown in FIG. 2 or the power supply circuit 10c of the third embodiment shown in FIG. 3, and is shown in FIG. '1' is set in the corresponding bit position of the VDC control register 21. In the fifth embodiment, it is assumed that the power supply circuit 9c or the power supply circuit 10c is configured to handle the drop power supply voltage supplied to each port latch circuit block 39.

As a result, the port latch power supply control signal corresponding to the port latch circuit block 39 which does not supply the falling power supply voltage during execution of the standby instruction is “1”, and the port corresponding to the port latch circuit block 39 supplying the falling power supply voltage is “1”. The latch power control signal becomes "0", and these port latch power control signals * OFF0 to * OFFn are output to the signal line 41 shown in FIG.

As a result, the switch circuit 38 to which the port latch power control signal of “1” has been inputted cuts off the supply of the drop power supply voltage to the corresponding port latch circuit block 39 and the port circuit of “0” The switch circuit 38 to which the latch power supply control signal has been input is connected to the port latch circuit block 39 corresponding to the drop power supply voltage from the power supply line 40.
Supply to

Accordingly, by changing the bit data set in the block selection register 32 every time the standby instruction is executed, it becomes possible to supply power only to the desired port latch circuit block 39 every time the standby instruction is executed.

In the normal operation, the block selection register 32 is reset to zero by the initial reset, so that the lowered power supply voltage can be constantly supplied to each port latch circuit block 39.

As described above, according to the fifth embodiment, since the falling power supply voltage can be supplied only to the desired port latch circuit block, for example, the light emission analysis (executing the standby command, which is a kind of microcomputer failure analysis method) is performed. Then, the switch circuit 38 adjacent to the port latch circuit block 39 is switched every time a standby command is performed without performing the method of converting the current flowing at that time into light energy to specify light energy and specifying a leak point. In the case of investigating a leak location due to destruction, it is possible to easily determine in which port latch circuit block 39 a leak is occurring by a test using an LSI tester.

Embodiment 6 FIG. FIG. 7 shows a case where a reduced power supply voltage is supplied to peripheral circuits such as a ROM and a port latch circuit block which require power supply at the time of reset, and the reduced power supply voltage is supplied to other peripheral circuits which do not need power supply at the time of reset. FIG. 3 is a circuit diagram illustrating a power supply control signal generation circuit that stops supply. In the figure, reference numeral 41 denotes a reset terminal (reset power supply control circuit) to which a low-level reset signal is input, 42 denotes an arbitrary external terminal (reset power supply control circuit), and 43, 62, 64, and 66 denote AND gates (reset). The power supply control circuit 44 is a two-input OR gate to which one input is supplied with the output of the AND gate 62 and the other input is supplied with the control signal OFFn shown in FIG. Reference numeral 45 denotes one input to which the output of the AND gate 64 is supplied, and the other input to the control signal O shown in FIG.
FF1 is a two-input OR gate supplied.

46 is an AND gate 66 connected to one input.
And the other input is a two-input OR gate to which the control signal OFF0 shown in FIG. 4 is supplied. 45, 46 output power control signals ** OFFn to ** OFF0.
Reference numeral 61 denotes an external terminal (reset power supply control circuit) for setting whether or not to supply a drop power supply voltage at the time of reset to a peripheral circuit which is controlled by the control signal OFFn and is served by the power supply circuit 10a of FIG. When supplying the falling power supply voltage to the circuit at reset, ground side,
If not supplied, connect to Vcc side. Similarly, reference numeral 63 denotes the power supply circuit 10 of FIG.
b is an external terminal (power supply control circuit at reset) for setting whether or not to supply a lowered power supply voltage at the time of reset to the peripheral circuit assigned to b.
And Similarly, reference numeral 65 denotes an external terminal (reset power control circuit) for setting whether or not to supply a drop power supply voltage at the time of reset to a peripheral circuit which is controlled by the control signal OFF0 and is served by the power supply circuit 10a of FIG. The peripheral circuit in this case is a port latch circuit.

FIG. 8 is a circuit diagram showing a circuit configuration for power supply around the ROM and the port latch circuit. In the figure, 47 is the power control signal ** O
FF0 to ** OFFn are output signal lines. 48
Is a switch circuit for controlling the supply and stop of the supply of the reduced power supply voltage to the ROM (internal peripheral circuit) 49. The power supply control signal supplies the lowered power supply voltage to the ROM 49 when the power supply control signal is at the Low level. At the High level, the supply of the drop power supply voltage to the ROM 49 is stopped. 49 is a ROM, 50 is a port latch circuit (internal peripheral circuit) 51
This is a switch circuit that controls the supply and stop of the supply of the falling power supply voltage to the power supply, and operates in the same manner as the switch circuit 48.
Reference numeral 52 denotes a power supply line for outputting a lowered power supply voltage to be supplied to the ROM. In the sixth embodiment, the power supply line branches off from the lowered power supply voltage line 8b of the power supply circuit 10b shown in FIG. Reference numeral 53 denotes a power supply line for outputting a lowered power supply voltage supplied to the port latch circuit 51, and similarly branches off from the lowered power supply voltage line 8a of the power supply circuit 10a shown in FIG.

Next, the operation will be described. In the sixth embodiment, even when various operations performed during the reset period of the microcomputer, such as execution of write / read access to the ROM and a special mode for analysis, are performed, peripheral circuits that do not need to supply the drop power supply voltage are provided. Stop supplying the falling power supply voltage. For this reason, an AND operation is performed between the input of an arbitrary external terminal 42 and the reset terminal 41 or the enable signal of the special mode by the AND gate 43 in advance. For a peripheral circuit for supplying a drop power supply voltage at the time of reset, for example, the ROM 49, a corresponding external terminal 6 is connected.
3 is connected to the ground side, and similarly, for a port latch circuit 51 that supplies a falling power supply voltage at the time of reset,
The corresponding external terminal 65 is connected to the ground side. Also,
For other peripheral circuits that do not supply the falling power supply voltage at reset, the corresponding external terminals are connected to the Vcc side.

At the time of reset, an arbitrary level (in this case, High level) is applied to the external terminal 42,
Also, when a low-level reset signal is input to the external terminal 41, the output of the AND gate 43 goes high. At this time, since the external terminals 63 and 65 are connected to the ground side, the outputs of the AND gates 64 and 66 are at the low level.
A low level is output as OFF0, ** OFF1, and a drop power supply voltage VD0 from the power supply line 52 and a ROM 4
9 is supplied with a drop power supply voltage VD1 from a power supply line 53 by a switch circuit 48. Further, the power supply control signals except for the power supply control signals ** OFF0 and ** OFF1 become High level to other peripheral circuits, so that the reduced power supply voltage is not supplied.

As described above, by connecting the external terminals corresponding to the respective peripheral circuits to the ground side or the Vcc side, the peripheral circuits which do not need to supply the reduced power supply voltage at the time of reset through the two-input OR gates 44, 45, 46 The power supply control signal to be output to each switch circuit is set to "1", and the power supply control signal to be output to each switch circuit of a peripheral circuit which needs to supply the drop power supply voltage at reset is set to "0". And the port power supply voltage is supplied to only the port latch circuit 51 at the time of reset.

As described above, according to the sixth embodiment, the supply of the reduced power supply voltage to the peripheral circuits which do not need to be operated at the time of resetting can be stopped. There is an effect that a power supply circuit of a microcomputer that can be reduced can be obtained.

[0062]

As described above, according to the present invention, VD
A leak current reducing circuit provided for each VDC circuit for reducing a leak current of the C circuit, and supply and supply of the lowered power supply voltage from the VDC circuit to a corresponding internal peripheral circuit provided for each VDC circuit A switch circuit for stopping, and supply of the lowered power supply voltage generated by each of the VDC circuits to the corresponding internal peripheral circuit by the switch circuit;
Since the supply is stopped and the VDC circuit corresponding to the internal peripheral circuit to which the supply of the drop power supply voltage is stopped is provided with control means for controlling the leakage current reduction by the leakage current reduction circuit. The control unit can eliminate the current consumption of the internal peripheral circuit that does not need to be operated supplied from the VDC circuit, and can also reduce the leakage current in the VDC circuit corresponding to the internal peripheral circuit that does not need to operate. Therefore V
There is an effect that current consumption in a microcomputer with a built-in DC circuit can be more effectively reduced.

According to the present invention, the supply of the lowered power supply voltage generated by the VDC circuit is stopped, the supply of the supply voltage is stopped, and the V CC corresponding to the internal peripheral circuit to which the supply of the lowered power supply voltage is stopped is provided.
The VDC control register for controlling the reduction of the leakage current of the DC circuit and outputting a control signal corresponding to the VDC circuit is provided. Therefore, the VDC control register corresponds to an internal peripheral circuit that does not need to be operated. VD
Designating the C circuit not only eliminates the current consumption of internal peripheral circuits that do not need to be operated and that is supplied from the VDC circuit, but also reduces the leakage current in the VDC circuit. This has the effect of reducing the current consumption of the microcomputer more effectively.

According to the present invention, the supply of the reduced power supply voltage generated by the VDC circuit during standby and the reduction of the leakage current of the VDC circuit corresponding to the internal peripheral circuit to which the supply of the reduced power supply voltage is stopped are described. , V
Since a priority circuit that outputs a control signal that is higher than a control signal that is output from the DC control register is provided, the current consumption of the internal peripheral circuits that need not be operated and supplied from the VDC circuit in the standby mode can be reduced. Irrespective of the contents specified by the VDC control register, not only the priority circuit can eliminate the leakage current, but also the leakage current in the VDC circuit corresponding to the internal peripheral circuit that does not need to operate can be reduced.
There is an effect that current consumption in a microcomputer with a built-in C circuit can be reduced more effectively.

According to the present invention, the setting data for the supply and stop of the supply of the drop power supply voltage to each of the internal peripheral circuits to which the common drop power supply voltage is supplied, and the drop power supply voltage to the plurality of internal peripheral circuits Supply and stop of the drop power supply voltage generated by the VDC circuit based on a control signal output from a VDC control register corresponding to the VDC circuit that supplies the internal power supply to each of the plurality of internal peripheral circuits. Since the power supply control means is provided for each of the peripheral circuits, not only the internal peripheral circuits that do not need to be operated according to the setting data can be changed to freely eliminate the current consumption, but also the plurality of peripheral circuits can be used. Since the leakage current of a VDC circuit corresponding to an internal peripheral circuit that does not need to be operated other than the internal peripheral circuit can be reduced, VD
There is an effect that current consumption in a microcomputer with a built-in C circuit can be reduced more effectively.

According to the present invention, the supply of the lowered power supply voltage and the stop of the supply during the execution of the standby instruction to each of the port latch circuit blocks to which the common lowered power supply voltage as the internal peripheral circuit is supplied are set in the block selection register. Bit data and a V that supplies a drop power supply voltage to the internal peripheral circuit that is the port latch circuit block.
A power supply control signal generation circuit for generating a port latch power supply control signal based on a control signal output from a VDC control register corresponding to a DC circuit; and each of the port latches of a drop power supply voltage generated by the VDC circuit There is provided a switch circuit provided corresponding to each of the port latch circuit blocks, wherein the switch circuit is provided for each of the port latch circuit blocks, based on the port latch power supply control signal, for supplying and stopping supply to the circuit blocks. Therefore, not only the port latch circuit block which does not need to be operated according to the bit data set in the block selection register can be changed to eliminate the current consumption freely, but also to reduce the current consumption. The leak current of the VDC circuit corresponding to the internal peripheral circuits that do not need to operate is also reduced. Because there is more effectively reduced can effect the consumption current in the VDC circuit built-in microcomputer.

According to the present invention, the reset signal output at the time of resetting, the setting data regarding the supply and stop of the supply of the reduced power supply voltage at the time of resetting for each internal peripheral circuit, and the predetermined mode executed at the time of resetting The power supply circuit includes a reset power supply control circuit that controls supply of a reduced power supply voltage to a desired internal peripheral circuit at the time of resetting and supply stop based on a signal defining the above. The unnecessary power consumption of the internal peripheral circuits can be eliminated by the reset power supply control circuit, and the leak current in the VDC circuit corresponding to the internal peripheral circuits that do not need to be operated can be reduced. The current consumption of the microcomputer can be reduced more effectively. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a power supply circuit of a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a power supply circuit of a microcomputer according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a power supply circuit of a microcomputer according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a circuit configuration around a VDC control register of a power supply circuit of a microcomputer according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration around a port latch circuit which is a part of a power supply circuit of a microcomputer according to a fifth embodiment of the present invention;

FIG. 6 is a block diagram showing a port latch power supply control signal generation circuit of a power supply circuit of a microcomputer according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram showing a power supply control signal generation circuit of a power supply circuit of a microcomputer according to Embodiment 6 of the present invention.

FIG. 8 is a circuit diagram showing a circuit configuration for supplying power to peripherals such as a ROM and a port latch circuit of a power supply circuit of a microcomputer according to a sixth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of a VDC circuit used in a power supply circuit of a conventional microcomputer.

[Explanation of symbols]

6,38 switch circuit, 11,12 switch circuit (leakage current reduction circuit), 21 VDC control register,
27 2-input OR gate (priority circuit), 29 CPU
(Control means), 32 block selection register (power control means), 33, 34, 352 2-input AND gate (power control means, power control signal generation circuit), 39-port latch circuit block (internal peripheral circuit), 41 reset terminal (Power supply control circuit at reset), 42, 61, 63, 65
External terminals (reset power control circuit), 43, 62,
64, 66 AND gate (reset power control circuit), 49 ROM (internal peripheral circuit), 51 port latch circuit (internal peripheral circuit).

Claims (6)

[Claims] A power supply circuit of a microcomputer for generating a reduced power supply voltage to be supplied to an internal peripheral circuit by reducing an external power supply voltage, wherein the power supply circuit is provided for each internal peripheral circuit and reduces the external power supply voltage. A VDC circuit for generating a step-down power supply voltage to be supplied to an internal peripheral circuit; a leak current reducing circuit provided for each VDC circuit for reducing a leak current of the VDC circuit; and a VDC circuit provided for each VDC circuit. And a switch circuit for supplying and stopping the supply of the reduced power supply voltage to the corresponding internal peripheral circuit, and supplying the supply of the reduced power supply voltage generated by the VDC circuit by the switch circuit, stopping the supply, and controlling the supply of the reduced power supply voltage. V corresponding to the internal peripheral circuit whose supply is stopped
A power supply circuit for a microcomputer, comprising: a DC circuit; and control means for controlling a reduction in leakage current by the leakage current reduction circuit. 2. The control means includes the steps of: supplying a supply voltage drop generated by the VDC circuit;
And a VDC control register that outputs a control signal corresponding to the VDC circuit and controls a reduction in leakage current of a VDC circuit corresponding to an internal peripheral circuit to which the supply of the power supply voltage is stopped. A power supply circuit for a microcomputer according to claim 1, wherein: 3. The control means is configured to stop supply of the reduced power supply voltage generated by the VDC circuit during standby and to reduce leakage current of the VDC circuit corresponding to an internal peripheral circuit in which the supply of the reduced power supply voltage is stopped. 3. A power supply circuit for a microcomputer according to claim 2, further comprising a priority circuit for outputting a control signal having priority over a control signal output from the VDC control register. 4. A setting data on supply and stop of the supply of the lowered power supply voltage in each of a plurality of internal peripheral circuits to which a common power supply voltage is supplied, and a supply of the lowered power supply to the plurality of internal peripheral circuits. Based on a control signal output from a VDC control register corresponding to a VDC circuit that supplies a voltage, supply and stop of the supply of the lowered power supply voltage generated by the VDC circuit are performed by the plurality of internal peripheral circuits. 4. The power supply circuit for a microcomputer according to claim 3, further comprising power supply control means for controlling each of the internal peripheral circuits. 5. The power supply control means sets bit data for supplying and stopping supply of a reduced power supply voltage during execution of a standby instruction to each port latch circuit block to which a common reduced power supply voltage as an internal peripheral circuit is supplied. A block select register, and the bit data set in the block select register and a VDC circuit corresponding to a VDC circuit for supplying a drop power supply voltage to an internal peripheral circuit which is the port latch circuit block.
A power supply control signal generation circuit that generates a port latch power supply control signal based on a control signal output from a C control register; and a supply of the lowered power supply voltage generated by the VDC circuit to each of the port latch circuit blocks. A switch circuit provided corresponding to each of the port latch circuit blocks, for stopping supply of the respective port latch circuit blocks based on the port latch power supply control signal. The power supply circuit of a microcomputer according to claim 4, wherein 6. A reset signal output at the time of resetting, setting data about supply and stop of supply of a reduced power supply voltage at the time of resetting for each internal peripheral circuit, and a signal defining a predetermined mode to be executed at the time of resetting 4. The microcomputer according to claim 3, further comprising: a reset-time power supply control circuit that controls supply of a reduced power supply voltage to a desired internal peripheral circuit at the time of said reset and control of supply stop. Power circuit.