JP2005078197A - Power-saving controller - Google Patents

Power-saving controller Download PDF

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JP2005078197A
JP2005078197A JP2003305136A JP2003305136A JP2005078197A JP 2005078197 A JP2005078197 A JP 2005078197A JP 2003305136 A JP2003305136 A JP 2003305136A JP 2003305136 A JP2003305136 A JP 2003305136A JP 2005078197 A JP2005078197 A JP 2005078197A
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power
saving mode
program
speed memory
power saving
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Naohiko Miyoshi
尚彦 三好
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Ricoh Co Ltd
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Ricoh Co Ltd
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<P>PROBLEM TO BE SOLVED: To provide a power-saving controller which saves on power during power-saving time and reduces the time to return from a power-saving mode, using an inexpensive constitution in either case. <P>SOLUTION: The power-saving controller downloads a program stored in a slow memory 4 into a volatile fast memory 6 to execute the program. In the power-saving mode, the power of a CPU 1 is turned off and the fast memory 6 has its power backed up to retain the program downloaded; the potential of backup voltage is detected and a method of recovery from the power-saving mode is changed according to power-saving mode information stored in a nonvolatile RAM 5. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、低速メモリあるいはネットワークからプログラムを揮発性の高速メモリにダウンロードして実行する省電力制御装置に関するものである。   The present invention relates to a power saving control apparatus that downloads a program from a low-speed memory or a network to a volatile high-speed memory and executes the program.

低速メモリあるいはネットワークからプログラムを揮発性の高速メモリにダウンロードして実行する省電力制御装置に関連して以下の技術が公知である。
特開１１−０５３２７１号公報 特開０８−０３３２１７号公報 特開０５−３０３５５３号公報 The following techniques are known in relation to a power-saving control device that downloads a program from a low-speed memory or a network to a volatile high-speed memory and executes the program.
JP 11-053271 A JP 08-033217 A JP 05-303553 A

従来、性能向上のためにプログラムを低速メモリ（ＨＤＤやＲＯＭ）から高速メモリ（一般的には揮発性のＤＲＡＭを指す）にロードして実行する装置において、省電力時、省電力化のために高速メモリまでも電源をオフすると、省電力モードからの復帰に時間がかかり、逆に、復帰時間を速くするために高速メモリに電源を供給すると省電力化ができないといった課題があった。
本発明は、省電力時の省電力化と省電力モードからの復帰時間の短縮を安価な構成で達成することができる省電力制御装置を提供することを目的としている。 Conventionally, in order to improve performance, in a device that loads and executes a program from a low-speed memory (HDD or ROM) to a high-speed memory (generally indicating a volatile DRAM), in order to save power and power When even the high-speed memory is turned off, it takes time to recover from the power saving mode. Conversely, if power is supplied to the high-speed memory in order to speed up the recovery time, there is a problem that power saving cannot be achieved.
An object of the present invention is to provide a power saving control device that can achieve power saving at the time of power saving and shortening of a return time from a power saving mode with an inexpensive configuration.

上記目的を達成するために、請求項１記載の発明は、低速メモリに格納されたプログラムを揮発性の高速メモリにダウンロードして実行する省電力制御装置において、省電力モード時、ＣＰＵの電源をオフし高速メモリに対して電源バックアップしダウンロードしたプログラムを保持すると共に、バックアップ電圧の電位検出を行ない、不揮発性ＲＡＭに格納した省電力モード情報に基いて省電力モードからの復帰方法を変更する省電力制御装置を最も主要な特徴とする。
請求項２記載の発明は、ネットワークからプログラムを揮発性の高速メモリにダウンロードして実行する省電力制御装置において、省電力モード時、ＣＰＵの電源をオフし高速メモリに対して電源バックアップしてダウンロードしたプログラムを保持すると共に、バックアップ電圧の電位検出を行ないと不揮発性ＲＡＭに格納した省電力モード情報から省電力モードからの復帰方法を変更する省電力制御装置を最も主要な特徴とする。
請求項３記載の発明は、請求項１、２記載の省電力制御装置において、高速メモリのバックアップ電源がコンデンサである省電力制御装置を主要な特徴とする。
請求項４記載の発明は、請求項１、２記載の省電力制御装置において、揮発性の高速メモリデバイスが複数個実装され、該デバイスの一部分のみをバックアップする省電力制御装置を主要な特徴とする。 In order to achieve the above object, according to a first aspect of the present invention, there is provided a power saving control device that downloads a program stored in a low speed memory to a volatile high speed memory and executes the program. Turn off the power supply to the high-speed memory, hold the downloaded program, detect the potential of the backup voltage, and change the return method from the power saving mode based on the power saving mode information stored in the nonvolatile RAM The most important feature is the power control device.
According to the second aspect of the present invention, in a power saving control device that downloads a program from a network to a volatile high speed memory and executes the program, the power of the CPU is turned off and the high speed memory is backed up and downloaded in the power saving mode. The power saving control device that holds the program and changes the return method from the power saving mode based on the power saving mode information stored in the nonvolatile RAM unless the potential of the backup voltage is detected is the main feature.
According to a third aspect of the present invention, in the power saving control device according to the first or second aspect, the main feature is the power saving control device in which the backup power source of the high-speed memory is a capacitor.
According to a fourth aspect of the present invention, there is provided the power saving control apparatus according to any one of the first and second aspects, wherein the power saving control apparatus includes a plurality of volatile high-speed memory devices and backs up only a part of the device. To do.

請求項１、２の装置においては、省電力モード時システムの大部分の電源を遮断可能でかつそのモードにおいても高速メモリ上にデータを保持可能であるため、省電力化と高速復帰の両立が可能となる。また、電源オンと省電力モードからの復帰の区別がつくので初期化ルーチンによりプログラム格納メモリの初期化を防ぐことができる。あるいは、省電力モードからの復帰であってもバックアップ電圧が閾値に満たない場合は初期化が必要であり、その判断も可能となる。また、プログラムのロードやメモリ初期化のスキップなど復帰時間の高速化も図ることが可能となる。
請求項３の装置では、揮発性の高速メモリのバックアップをコンデンサで行なうことで非常に安価な構成でバックアップできる。本発明ではバックアップ電圧の電位を検出することで揮発性メモリの内容が保証できない場合は再ロード可能な構成としているため、コンデンサのような安価な部品での構成を可能としている。但し、バックアップ時間とコストがトレードオフの関係となる。
請求項４の装置では、一般的に揮発性の高速メモリは増設可能な仕様になっているものが多いが電源バックアップの領域を該メモリの最小構成部分のみにすることでバックアップ時間を長くすることが可能となる。 In the apparatus according to claims 1 and 2, since most of the power supply of the system can be shut off in the power saving mode and data can be held in the high speed memory even in that mode, both power saving and high speed recovery can be achieved. It becomes possible. Further, since it is possible to distinguish between power-on and return from the power saving mode, initialization of the program storage memory can be prevented by the initialization routine. Alternatively, even when returning from the power saving mode, if the backup voltage is less than the threshold value, initialization is necessary, and the determination can be made. Also, it is possible to speed up the recovery time such as program loading and memory initialization skip.
According to the third aspect of the present invention, a volatile high-speed memory can be backed up with a capacitor at a very low cost by performing a backup with a capacitor. In the present invention, when the contents of the volatile memory cannot be guaranteed by detecting the potential of the backup voltage, the configuration can be reloaded, so that a configuration with an inexpensive component such as a capacitor is possible. However, there is a trade-off between backup time and cost.
In the apparatus according to claim 4, in general, there are many volatile high-speed memories that can be expanded, but the backup time can be extended by making the power backup area only the minimum component of the memory. Is possible.

以下、図面により本発明の実施の形態を詳細に説明する。
図１は本発明の実施の形態に係る省電力制御装置の全体ブロック図である。本省電力制御装置は、ＣＰＵ１、ＭＣＨ(Memory Controller Hub)２、ＩＣＨ(IO Controller Hub)３のチップセットから構成されている。
ＭＣＨ２は主にメモリの制御を行なっており、プログラムが格納されている比較的低速のＲＯＭ４と不揮発性メモリであるＮＶＲＡＭ５、そして高速大容量の揮発性メモリＲＡＭ６が接続されている。ＮＶＲＡＭ５は電源オフ時もデータ保持する不揮発性メモリであり、省電力モードかどうかの状態を表す情報等システムコンフィギュレーションが格納される。
ＩＣＨ３は、省エネのための電源制御を行なうI／O制御チップである。省電力モード時、ホストからＩ／Ｏ部７を介してデータを受信すると復帰のための信号（Ｒｅｔｕｒｎ）をアサートし外部ＰＯＷＥＲがオンされる。
電源制御部は、外部ＰＯＷＥＲを供給する電源部８、バックアップ電源９、供給電源切替部１０、ＲＡＭ供給電圧電位検出部(電位検出部)１１からなる。供給電源切替部１０では、ＲＡＭ６への供給電圧を外部ＰＯＷＥＲとバックアップ電源９の間で切り替えている。
すなわち電源オフ時は（オフ時はメインスイッチオフ時と省電力モード移行時が考えられる）バックアップ電源９から、電源オン時は外部ＰＯＷＥＲから供給を行なう。ＲＡＭ供給電圧電位検出部１１ではＲＡＭ６への供給電圧の電位を検出し、閾値よりも低い場合には、ＩＣＨ３に対して通知を行なう。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is an overall block diagram of a power saving control apparatus according to an embodiment of the present invention. This power saving control device is composed of a chip set of a CPU 1, an MCH (Memory Controller Hub) 2, and an ICH (IO Controller Hub) 3.
The MCH 2 mainly controls the memory, and is connected to a relatively low-speed ROM 4 storing a program, an NVRAM 5 which is a nonvolatile memory, and a high-speed and large-capacity volatile memory RAM 6. The NVRAM 5 is a non-volatile memory that retains data even when the power is turned off, and stores a system configuration such as information indicating the state of whether or not it is in the power saving mode.
The ICH3 is an I / O control chip that performs power supply control for energy saving. In the power saving mode, when data is received from the host via the I / O unit 7, a return signal (Return) is asserted and the external POWER is turned on.
The power supply control unit includes a power supply unit 8 that supplies an external POWER, a backup power supply 9, a supply power supply switching unit 10, and a RAM supply voltage potential detection unit (potential detection unit) 11. The power supply switching unit 10 switches the supply voltage to the RAM 6 between the external POWER and the backup power supply 9.
That is, the power is supplied from the backup power supply 9 when the power is off (when the main switch is off and when the power saving mode is shifted), and from the external POWER when the power is on. The RAM supply voltage potential detection unit 11 detects the potential of the supply voltage to the RAM 6 and notifies the ICH 3 when it is lower than the threshold value.

図２は本発明の省電力制御装置における制御動作を示すフローチャート、図３は各状態における処理内容を示す図表である。図２のフローに沿って本発明の詳細を説明する。
ＰＯＷＥＲオンあるいは、省電力モードから復帰すると電源が供給され、まず最低限のハードの初期化が行なわれる。その後の処理は「省電力モード復帰？」で、バックアップ時の電源の電位とＮＶＲＡＭ５に格納された電源オン直前のモードを読み出し、図３の例に従って処理が変わる。
図３は、フローチャート上の、「省電力モード復帰？」で行なわれる判定の一例である。この例では、ＲＡＭ供給電圧の電位がＬｏｗかつ省電力モードからの復帰時のみ、他の状態と異なりプログラムのＲＡＭダウンロードを行なわない。初期化は省電力復帰に最適化して実施などの高速化のための処理が行なわれている。
省電力モードからの復帰では、フローチャートのとおり高速にレディとなる。その他のケースでは通常のシステム起動時間をかけてレディとなる。レディの期間が一定時間以上経つと省電力モードの突入し、その際、ＮＶＲＡＭ５に省電力モード移行情報を格納し、電源をオフする。一部ホスト装置からの受信検知に必要な電源は供給され、受信を検知すると、電源復帰の信号「Ｒｅｔｕｒｎ」をアサートし、ＰＯＷＥＲオンのシーケンスに戻る。
図１において、バックアップ電源９がコンデンサであっても、本発明ではバックアップ電源９が放電し低電位になることを前提としているため有効である。但し、コストとバックアップ時間はトレードオフの関係である。
図１の増設ＲＡＭ部６−２はバックアップされていないことを示す。一般的に主なプログラム（ＯＳ他）のダウンロードは常駐のＲＡＭ部６−１にダウンロードされるため、システムを起動する際に増設ＲＡＭ部６−２のバックアップは不要である。本システムでは、低コストで長時間のバックアップを可能とする。 FIG. 2 is a flowchart showing a control operation in the power saving control apparatus of the present invention, and FIG. 3 is a chart showing processing contents in each state. The details of the present invention will be described along the flow of FIG.
When the power is turned on or the power saving mode is restored, the power is supplied, and first, the minimum hardware initialization is performed. The subsequent processing is “return to power saving mode?”, The power supply potential at the time of backup and the mode immediately before power-on stored in the NVRAM 5 are read, and the processing changes according to the example of FIG.
FIG. 3 is an example of the determination performed by “return to power saving mode?” On the flowchart. In this example, the RAM download of the program is not performed unlike the other states only when the potential of the RAM supply voltage is Low and the mode returns from the power saving mode. Initialization is optimized for returning to power saving and processing for speeding up is performed.
When returning from the power saving mode, the system is ready at high speed as shown in the flowchart. In other cases, it becomes ready over normal system startup time. When the ready period exceeds a certain time, the power saving mode is entered. At this time, the power saving mode transition information is stored in the NVRAM 5 and the power is turned off. Power necessary for detection of reception from some host devices is supplied. When reception is detected, a power recovery signal “Return” is asserted and the sequence returns to the POWER on sequence.
In FIG. 1, even if the backup power supply 9 is a capacitor, the present invention is effective because it is premised on that the backup power supply 9 is discharged and has a low potential. However, cost and backup time are in a trade-off relationship.
The additional RAM section 6-2 in FIG. 1 indicates that it has not been backed up. Generally, since the main program (such as OS) is downloaded to the resident RAM unit 6-1, backup of the additional RAM unit 6-2 is not required when starting the system. This system enables long-term backup at low cost.

本発明の実施の形態に係る省電力制御装置の全体ブロック図である。1 is an overall block diagram of a power saving control device according to an embodiment of the present invention. 本発明の省電力制御装置における制御動作を示すフローチャートである。It is a flowchart which shows the control action in the power saving control apparatus of this invention. 各状態における処理内容を示す図である。It is a figure which shows the processing content in each state.

符号の説明Explanation of symbols

１ ＣＰＵ
４ ＲＯＭ(低速メモリ)
５ ＮＶＲＡＭ
６ ＲＡＭ(高速メモリ) 1 CPU
4 ROM (low speed memory)
5 NVRAM
6 RAM (high-speed memory)

Claims (4)

低速メモリに格納されたプログラムを揮発性の高速メモリにダウンロードして実行する省電力制御装置において、省電力モード時、ＣＰＵの電源をオフし前記高速メモリに対して電源バックアップしダウンロードしたプログラムを保持すると共に、バックアップ電圧の電位検出を行ない、不揮発性ＲＡＭに格納した省電力モード情報に基いて省電力モードからの復帰方法を変更することを特徴とする省電力制御装置。   In a power-saving control device that downloads and executes a program stored in a low-speed memory to a volatile high-speed memory, in the power-saving mode, the CPU is turned off and the downloaded high-speed memory is backed up to retain the downloaded program And a power-saving control device that detects the potential of the backup voltage and changes the return method from the power-saving mode based on the power-saving mode information stored in the nonvolatile RAM. ネットワークからプログラムを揮発性の高速メモリにダウンロードして実行する省電力制御装置において、省電力モード時、ＣＰＵの電源をオフし前記高速メモリに対して電源バックアップしてダウンロードしたプログラムを保持すると共に、バックアップ電圧の電位検出を行ない不揮発性ＲＡＭに格納した省電力モード情報から省電力モードからの復帰方法を変更することを特徴とする省電力制御装置。   In the power saving control device that downloads and executes the program from the network to the volatile high-speed memory, in the power saving mode, the CPU is turned off and the downloaded program is backed up to the high-speed memory to store the downloaded program. A power-saving control device that detects a potential of a backup voltage and changes a return method from a power-saving mode based on power-saving mode information stored in a nonvolatile RAM. 請求項１、２記載の省電力制御装置において、前記高速メモリのバックアップ電源がコンデンサであることを特徴とする省電力制御装置。   3. The power saving control device according to claim 1, wherein a backup power source of the high speed memory is a capacitor. 請求項１、２記載の省電力制御装置において、揮発性の高速メモリデバイスが複数個実装され、該デバイスの一部分のみをバックアップすることを特徴とする省電力制御装置。   3. The power saving control device according to claim 1, wherein a plurality of volatile high-speed memory devices are mounted, and only a part of the device is backed up.
JP2003305136A 2003-08-28 2003-08-28 Power-saving controller Pending JP2005078197A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102244709A (en) * 2010-05-12 2011-11-16 佳能株式会社 Image forming apparatus and control method
JP2012103796A (en) * 2010-11-08 2012-05-31 Ricoh Co Ltd Image processing apparatus
CN102708876A (en) * 2011-03-28 2012-10-03 西部数据技术公司 Disk drive booting from volatile semiconductor memory when exiting power save mode
KR101236393B1 (en) 2005-09-24 2013-02-22 삼성전자주식회사 Electric device and control method thereof
US8806241B2 (en) 2008-02-19 2014-08-12 Canon Kabushiki Kaisha Apparatus and method for shortening the time returning from a power-saving mode to normal power mode and reducing power consumption in the power-saving mode

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101236393B1 (en) 2005-09-24 2013-02-22 삼성전자주식회사 Electric device and control method thereof
US8806241B2 (en) 2008-02-19 2014-08-12 Canon Kabushiki Kaisha Apparatus and method for shortening the time returning from a power-saving mode to normal power mode and reducing power consumption in the power-saving mode
CN102244709A (en) * 2010-05-12 2011-11-16 佳能株式会社 Image forming apparatus and control method
US8914655B2 (en) 2010-05-12 2014-12-16 Canon Kabushiki Kaisha Image forming apparatus and control method
JP2012103796A (en) * 2010-11-08 2012-05-31 Ricoh Co Ltd Image processing apparatus
CN102708876A (en) * 2011-03-28 2012-10-03 西部数据技术公司 Disk drive booting from volatile semiconductor memory when exiting power save mode
CN102708876B (en) * 2011-03-28 2015-09-30 西部数据技术公司 When exiting energy-saving mode from the disc driver that volatile semiconductor memory starts

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