JP2900551B2 - Portable semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a portable semiconductor memory device equipped with a semiconductor memory device.

[Conventional technology]

FIG. 2 is a circuit block diagram showing a conventional portable semiconductor memory device. In the figure, (1) is a power supply switching circuit,
(2) is a power supply detection circuit, (3a) is an external power supply voltage, (3b)
Is the internal power supply voltage, (4) is a capacitor between the power supply and ground, (5) is a diode for preventing reverse current, (6) is a resistor,
(7) is an internal power supply battery, (8) is an address decode circuit, and (9) and (10) are SRAMs and semiconductor memories.
(11) is an address bus. (12) is a write enable signal, (13) is a card enable signal, and (14) is an output enable signal, and these are control signals. (15) is a data bus, (16) is an address bus 1, (17a) is a memory selector signal 1, (17b) is a memory select signal 2, (18) is an external power detection signal, (19),
(20) and (21) are pull-up resistors, (22) is an external power supply, and (25) is an internal power supply line.

Next, the operation will be described. SRMA (9) and (10)
The case of reading data from is as follows. The power supply voltage is applied from the outside to the external power supply (22) and is higher than the voltage of the internal power supply battery (7), and the SRAMs (9) and (10)
When the voltage reaches a voltage at which a write or read operation is possible, the power supply switching circuit (1) operates and the internal power supply voltage (3b)
Is connected to the internal power supply line (25), the voltage of which is substantially the same as the external power supply voltage (3a). At this time, the external power supply detection signal (18) is "L" in logic level but becomes "H", and becomes active in CS of the address decode circuit (8) and CE of the SRAMs (9) and (10). Send "H" as a signal. Next, the card enable signal (13) and the output enable signal (14) are set to “L”, and the write enable signal (12)
Is set to "H", the lower address signal is applied to the address bus (11), the upper address signal is applied to the address bus 1 (16), and one of the memory select signals (17a) or (17b) is selected. Then, if the SRAM (9) or (10) is selected, the data held in the memory at the address appears on the data bus (15).

Next, writing data to the SRAMs (9) and (10) is as follows. Card enable signal (1
3) “L”, output enable signal (14) “H”, write enable signal (12) “L”, lower address signal on address bus (11), upper address signal on address bus (16) Then, if one of the SRAMs (9) or (10) or the like is selected and data for writing is applied to the data bus (15), writing is performed on the selected SRAM (9) or (10). The pull-up resistors (18), (20) and (21) are for preventing erroneous writing when a power supply voltage is applied to the external power supply (22).

Next, a case where the power supply voltage applied to the external power supply (22) is cut off and the external power supply (22) is opened will be described. When the power supply detection circuit (2) determines that the voltage of the external power supply (22) has fallen below a certain value, the circuit of the power supply switching circuit (1) includes an external power supply (22) and an internal power supply line (25).
And the value of the internal power supply voltage (3b) is switched to the voltage supplied from the internal power supply battery (7), and power is supplied to the address decode circuit (8) and the SRAMs (9) and (10). And retain the memory data. At this time, the external power supply detection signal (18) changes from "H" to "L", and the address decode circuit (8) and the SRAMs (9) and (10)
Is made inactive, and writing to the SRAM and reading from the SRAM are stopped.

As described above, in the conventional portable semiconductor memory device, power is supplied to the address decoding circuit (8) by either the voltage applied to the external power supply (22) or the voltage from the internal power supply battery (7). SRAMs (9) and (10) are configured, and a data bus (15), an address bus (11) and control signals (12), (13), (1)
4) has a circuit configuration directly connected to the SRAMs (9) and (10) or the address decode circuit (8) from the outside.

[Problems to be solved by the invention]

Since the conventional portable semiconductor memory device is configured as described above, when the device is carried in a memory backup state by the internal power supply battery (7), the address bus (11) and the data bus line (15) are used. ) And the control signals (12), (13) and (14) are charged for some reason, and depending on the change in the potential of these terminals, the internal power supply battery (7) is consumed and the memory data is destroyed. There was a case. In addition, when the device is attached to or detached from a computer terminal for reading memory data of the device or for rewriting the memory data, when the device is attached or detached, for example, when the device should not be inserted and detached by being inserted obliquely. Depending on the contact state of the contacts, unpredictable current may flow from the internal power supply line (25) to the ground line through the internal circuit of each block circuit, or may be incorrect, due to the irregular voltage change caused by the attachment / detachment of the unit. In some cases, a signal is generated and the memory data is destroyed in the same manner as described above.
Also, if you increase the number of SRAMs and increase the memory capacity,
The address bus and the data bus of the SRAM are connected in parallel, and when these terminals are viewed, there is a problem that a bus having a large load capacity needs to be driven.

The present invention has been made to solve the above problems, and in order to prevent the destruction of memory data as much as possible,
The control buffer, the address buffer and the data bus buffer are inserted. The address bus buffer and the data bus buffer are supplied with power from an external power supply. Further, a diode for preventing reverse current is inserted in the power supply circuit of the address bus buffer and the data bus buffer. Accordingly, it is an object of the present invention to obtain a portable semiconductor memory device in which the retention of memory data is improved and the load capacity is reduced.

[Means for Solving the Problems] A portable semiconductor memory device according to the present invention includes a plurality of semiconductor memories, an address decode circuit of the semiconductor memory,
An internal power supply; and a power supply switching circuit for switching between the internal power supply and the external power supply. In a backup state in which the external power supply is not supplied, power is supplied from the internal power supply to the semiconductor memory and the address decode circuit. In a portable semiconductor memory circuit that retains memory data and switches the power supply to the external power supply when receiving the external power supply to enable reading or writing of memory data, a control buffer, an address bus buffer, In the case of a backup state in which the data bus buffer is not supplied with the external power supply, power is supplied from the internal power supply to the semiconductor memory, the address decode circuit, and the control buffer to hold memory data, When receiving power supply, increase the power supply. Switching to an external power source, and reads out the memory data by supplying power from the external power source through a reverse current preventing diode to the address bus buffer and said data bus buffer is obtained by allowing to write or retention.

[Operation] A portable semiconductor memory device according to the present invention includes a control buffer, an address bus buffer, and a data bus buffer. In a backup state in which the external power supply is not supplied, the semiconductor memory and the address are transferred from the internal power supply. Power is supplied to the decoding circuit and the control buffer to hold the memory data. When the external power is supplied, the power supply is switched to the external power, and the address bus buffer and the data bus buffer receive the power. Power is supplied from an external power supply to enable reading, writing, or holding of memory data.

In a memory backup state in which external power is not supplied, the address bus buffer and the data bus buffer are in a power supply stopped state, so that the internal circuits are in an inactive state, the SRAM is cut off from an external input / output signal terminal, The malfunction of the memory circuit can be reduced by noise caused by a potential change based on the electric charges charged on the address bus and the data bus. In addition, in the computer terminal, when the device is attached or detached, for example, a malfunction caused by an irregular voltage change caused by inserting the device obliquely and attaching or detaching it when it should not be attached or detached may cause a malfunction of the memory circuit. To prevent as much as possible, power is supplied to the power supply circuits of the address buffer and data bus buffer via diodes to prevent the current generated by the irregular signal from sneaking into the internal power supply line and stabilize the operation of the SRAM. And destruction of memory data can be reduced. In addition, even if the number of semiconductor memories to be mounted increases, the capacitance seen from the outside of the card does not change.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, (30) is an address bus buffer, (31)
And (34) are diodes to prevent power sneak
(32) is an internal data bus, (33) is a data bus buffer, and (35) is a control buffer.

 Next, the operation and operation will be described.

The power supply to the address bus buffer (30) and the data bus buffer (33) is supplied from an external power supply (22) to a diode (3).
Supplied via 1) and (34).

In the data backup state in which the device is not supplied with power from the outside, since no power is supplied, the address bus buffer (30) and the data bus buffer (33) are not supplied.
Is in an electrically inactive state. As a result, since the noise voltage superimposed on the address bus (11) and the data bus (15) is blocked by these buffers, the destruction and malfunction of the memory data of the SRAMs (9) and (10) are reduced. .

Here, the diodes (31) and (34) are inserted to further prevent the destruction of the memory data. If these diodes are not inserted, a signal generated by an irregular voltage change caused by attaching / detaching the device to / from the computer terminal when the device should be attached / detached, for example, when it should not be attached / detached at an angle, should be inserted. Due to the short time,
An external power supply (2) is connected to the address bus (11) and data bus (15).
An unspecified signal may appear before the power is supplied to 2), and the unspecified signal passes through the input protection circuit of the address bus buffer (30) and the data bus buffer (33). ) Flows into the power supply circuit via the protection circuit, and reaches the external power supply (22), so that the power supply detection circuit (2)
Is operated to generate an external power supply detection signal (18), and a state may be obtained in which writing or reading to the memory is performed. In particular, when data writing to the memory is performed, memory data is destroyed. To prevent this, insert diodes (31) and (34) and connect the external power supply (2
2) Prevent malfunction by preventing the current from flowing into.

The memory control signals such as the write enable signal (12), the card enable signal (13), and the output enable signal (14) are connected to the input terminal of the SRAM via the control buffer (35) to prevent malfunction due to noise. Has been inserted for.

In the above embodiment, the number of SRAMs is two, but the number is not limited. In the above diagram, the upper address is decoded. However, the decoding may be performed with the lower address. In the above embodiment, only the SRAM has been considered. However, even in other semiconductor memory devices, providing a buffer has a similar effect.

[Effects of the Invention] As described above, according to the present invention, an address bus buffer is inserted into an address bus and a data bus buffer is inserted into a data bus, and the power is supplied from an external power supply. The control buffer and SRAM inserted in the memory control signal line are separated so that the circuits necessary for holding the memory data are supplied with power by the internal power supply battery. And the data bus buffer is in an inactive state due to a power supply stop state, the SRAM is cut off from an external input / output signal terminal, and a memory is generated by noise due to a potential change based on charges charged on an address bus and a data bus. It can reduce the malfunction of the circuit, Flow increase can be reduced.

At the computer terminal, when attaching / detaching this device,
For example, in order to prevent malfunction of the memory circuit as much as possible by a signal generated by an irregular voltage change caused by mounting and dismounting when it should not be mounted and demounted when it should not be mounted and demounted, the address bus buffer and the data bus buffer should be connected. Since the required power is supplied via the diode, by preventing the current generated by the irregular signal from sneaking into the internal power supply line,
The circuit operation of the SRAM can be stabilized, and the memory data can be protected. In addition, there is an effect that a portable semiconductor memory device can be obtained in which the capacitance seen from the outside of the card does not change even if the number of semiconductor memories to be mounted increases.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a portable semiconductor memory device according to one embodiment of the present invention. FIG. 2 is a circuit block diagram of a conventional device. In the figure, (1) is a power supply switching circuit, (2) is a power supply detection circuit, (3a) is an external power supply voltage, (3b) is an internal power supply voltage,
(5) is a diode for preventing reverse current, (7) is a battery for internal power supply, (8) is an address decode circuit, (9) and (10).
Is an SRAM and a semiconductor memory. (11) is the address bus,
(15) is the data bus, (16) is the address bus 1, (17)
a) is a memory select signal 1, (17b) is a memory select signal 2, (18) is an external power supply detection signal, (22) is an external power supply, (25) is an internal power supply line, (30) is an address bus buffer, 31) is a diode, (33) is a data bus buffer, (34) is a diode, and (35) is a control buffer. In the drawings, the same reference numerals indicate the same or corresponding parts.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 12/16 G06F 1/26 G06K 19/073 G11C 5/00 301-303

Claims (1)

(57) [Claims] A plurality of semiconductor memories; an address decode circuit for the semiconductor memory; an internal power supply; and a power supply switching circuit for switching between the internal power supply and an external power supply. When power is supplied from the internal power supply to the semiconductor memory and the address decode circuit to hold memory data, and when the external power supply is received, the power supply is switched to the external power supply to read the memory data. Or, in a portable semiconductor memory circuit capable of writing, a control buffer, an address bus buffer and a data bus buffer are provided, and in the case of a backup state where supply of the external power is not received, the semiconductor memory and the Power is supplied to the address decode circuit and the control buffer. In the case where the external power supply is supplied while the memory data is held, the power supply is switched to the external power supply, and the external power is supplied to the address bus buffer and the data bus buffer via a reverse current prevention diode. A portable semiconductor memory circuit, wherein power is supplied from a power supply to enable reading, writing, or holding of memory data.