JPH08228005A - Semiconductor device, thin film transistor, complementary thin film transistor, liquid crystal display device and manufacture of them - Google Patents

Abstract

PURPOSE: To make it possible to activate impurity ions, which are implanted using an ion implantation device, at a low temperature and to make it possible to prevent the ions from being implanted in the channel part of a thin film transistor without making thick the gate electrode of the thin film transistor by a method wherein an impurity ion implantation in a polycrystaline silicon film is made on a specified condition and the like. CONSTITUTION: A polycrystalline silicon film 7 is formed on an insulating substrate 5 and an insulating film 8 is formed on the film 7. Then, ions 14, which are produced from Kr-base gas containing less than 20% impurity, are implanted in the film 7 via the film 8 while the substrate 5 is heated at 200 deg.C or higher. After that, the substrate 5 is heated to 200 deg.C or higher to activate the impurity gas. For example, all ions 14, which are produced from Kr-base gas containing 0.01-5%pH3 gas, are implanted in source and drain regions 10 at an energy of 80kV using an ion implantation device which does not use a mass spectrometry.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for activating impurities contained in a polycrystalline silicon thin film. Further, the present invention relates to a semiconductor device, a thin film transistor, a complementary thin film transistor, a liquid crystal display device, and a manufacturing method thereof, each having a polycrystalline silicon thin film in which impurities are activated.

[0002]

2. Description of the Related Art An ion implantation technique without mass spectrometry has been developed for the purpose of forming a source region and a drain region of a thin film transistor used in a liquid crystal display device. FIG. 2 is a sectional view of an example of an ion implantation apparatus that does not use mass separation. Impurity ions 2 are extracted from the plasma source 1 by the extraction electrode 3, the impurity ions 2 are accelerated by the acceleration electrode 4 to have a predetermined energy, and the thin film transistor formed on the glass substrate 5 is implanted to form a source region and a drain region. To do. The energy given to the impurity ions 2 is determined by the sum of the voltage of the extraction electrode 3 and the voltage of the acceleration electrode 4. For plasma generation, there is an arc discharge method using a filament or the like in addition to the method of generating using high frequency of 13.56 MHz as in this example. When an ion implantation apparatus that does not use such mass separation is used and impurity ions are included in a doping gas and a mixed gas diluted with hydrogen is used to inject the impurity ions, the injected impurities have a temperature of about 300 ° C. Activated by heat treatment, M. Matsuo et al .:
Jpn. J. Appl. Phys. 31 (1992) 4567 and JP-A-4-37.
0937. Further, as a method for activating a trace amount of impurities contained in the source region and the drain region at a low temperature of less than 600 ° C., a specific amount of hydrogen is additionally implanted only into the source / drain regions of the thin film transistor after the implantation of the impurities. Method is M. Matsuo et al.: Ext
end Abstract of the Conference on Solid State Devi
ces and Materials, Makuhari, 1993 pp.437-439. Both methods have the disadvantage that hydrogen ions ionized from the diluent gas are injected into the silicon film of the channel portion at the same time as the impurity source / drain regions are injected, and the characteristics of the thin film transistor are changed. In order to solve this, a method of using helium as a diluent gas of a mixed gas used in an ion implantation apparatus that does not use mass separation has been proposed in JP-A-2-202028. Further, Japanese Patent Laid-Open No. 4-39967 proposes a method of making the protective film thicker than the projected range of hydrogen. However, such a conventional method causes a new problem that the step difference of the thin film transistor is increased, and wiring breaks and liquid crystal alignment defects occur.

[0003]

The problem to be solved by the present invention is that impurities implanted by using the above-mentioned ion implantation apparatus which does not use mass spectrometry can be activated at a low temperature, and the gate electrode of a thin film transistor is thickened. It is to provide a method capable of preventing the implantation of ions into the channel portion without doing so and stably form a thin film transistor on an inexpensive glass substrate.

[0004]

DISCLOSURE OF THE INVENTION The present invention is to solve the above-mentioned problems, and a polycrystalline silicon film formed on an insulating substrate and an insulating film deposited on the polycrystalline silicon film. The film contains a gas serving as a donor or an acceptor by using an ion implanter without mass separation,
All the ions generated from the mixed gas, the balance of which is Kr, are implanted into the polycrystalline silicon film through the insulating film while heating the insulating substrate, and then ion implantation is performed without using the mass separation. Using the apparatus, hydrogen ions generated from pure hydrogen gas are implanted into the polycrystalline silicon film through the insulating film, and then the insulating substrate is heated and implanted into the polycrystalline silicon film. It is characterized by activating the impurities.

That is, the method of manufacturing a semiconductor device according to the present invention comprises: (1) a step of forming a polycrystalline silicon film on an insulating substrate; and (2) forming an insulating film on the polycrystalline silicon film. Insulating film forming step for forming, and (3) ions generated from a mixed gas containing impurities of more than 0% and 20% or less and the balance of Kr at 200 ° C. for the insulating substrate.
Impurity ion implantation step of implanting into the polycrystalline silicon film via the insulating film while heating as described above, (4)
After the step of implanting the impurity ions, the insulating substrate 200 is formed.
It is characterized in that it has an impurity activation step of heating to a temperature of not less than ° C.

Further, in such a method of manufacturing a semiconductor device, hydrogen ions generated from hydrogen gas are made to pass through the insulating film and the polycrystal is formed between the impurity ion implantation step and the impurity activation step. It is characterized by having a hydrogen ion implantation step of implanting into a silicon film.

Further, when the n-type semiconductor device is manufactured, the impurity is PH ₃ , and when the p-type semiconductor device is manufactured, the impurity is B ₂ H _6. Characterize.

The semiconductor device of the present invention is manufactured by the method of manufacturing a semiconductor device according to any one of claims 1 to 4.

The semiconductor device of the present invention has an insulating substrate, a polycrystalline silicon thin film formed on the insulating substrate, and an insulating film formed on the polycrystalline silicon thin film. It is characterized in that the silicon and the insulating film contain Kr.

The method of manufacturing a thin film transistor of the present invention is
(1) a polycrystalline silicon film forming step of forming a polycrystalline silicon film on an insulating substrate; (2) an insulating film forming step of forming an insulating film on the polycrystalline silicon film; and (3) an insulating film. A gate electrode forming step of forming a gate electrode on
(4) Impurities exceeding 0% and 20% or less and the balance Kr
Ions generated from a mixed gas consisting of are implanted into the polycrystalline silicon film through the insulating film using the gate electrode as a mask while heating the insulating substrate to 200 ° C. or higher, and the source of the thin film transistor is self-aligned. Impurity ion implantation step for forming a region and a drain region,
(5) An impurity activation step of activating the impurities by heating the insulating substrate to 200 ° C. or higher after the impurity ion implantation step.

Further, in such a method of manufacturing a thin film transistor, hydrogen ions generated from hydrogen gas are passed through the insulating film and the polycrystalline silicon between the impurity ion implantation step and the impurity activation step. It is characterized by having a step of implanting hydrogen ions into the film.

Further, in manufacturing an n-type semiconductor device, the impurity is PH ₃ , and in manufacturing a p-type semiconductor device, the impurity is B ₂ H _6. Characterize.

The thin film transistor of the present invention has the following features.
It is manufactured by the method for manufacturing a thin film transistor according to claim 10.

The thin film transistor of the present invention is a planar type top gate thin film transistor formed on an insulating substrate. In the gate insulating film, a region in contact with the source region or the drain region, the source region and the drain region contain Kr. It is characterized by becoming.

When the thin film transistor is n-type, phosphorus is contained as an impurity in the source region and the drain region. When the thin film transistor is p-type, the source region and the drain region are formed. It is characterized in that the drain region contains boron as an impurity.

The method of manufacturing a complementary thin film transistor according to the present invention comprises (1) a step of forming a polycrystalline silicon film on an insulating substrate, and (2) forming an insulating film on the polycrystalline silicon film. And (3) a gate electrode forming step of forming a gate electrode on the insulating film, and (4) a first impurity of n-type exceeding 0% to 20%.
Ions generated from a mixed gas containing the following, the balance being a diluent gas, are implanted into the polycrystalline silicon film through the insulating film while heating the insulating substrate to 200 ° C. or higher, and self-aligned to n-type. N-type impurity ion implantation step of forming the source region and the drain region of (5), and (5) the second impurity of p-type is produced from a mixed gas containing more than 0% and 20% or less and the balance being a diluent gas. Ions are implanted into the polycrystalline silicon film through the insulating film while heating the insulating substrate to 200 ° C. or higher, and p-type impurity ion implantation is performed to form p-type source and drain regions in a self-aligned manner. Step (6) 200 of the insulating substrate
And an impurity activation step of activating the n-type impurities and the p-type impurities by heating at a temperature equal to or higher than ° C.

In the method of manufacturing such a complementary thin film transistor, hydrogen gas may be used after the n-type impurity ion implantation step and the p-type impurity ion implantation step and before the impurity activation step. And a hydrogen ion implantation step of implanting hydrogen ions generated from the above into the source region and the drain region of the thin film transistor through the insulating film.

Further, in the method of manufacturing such a complementary thin film transistor, the first impurity is PH ₃ and the second impurity is B ₂ H ₆ .

The complementary thin film transistor of the present invention is characterized by being manufactured by such a method of manufacturing a complementary thin film transistor.

The complementary thin film transistor of the invention is a complementary (CMOS) thin film transistor comprising an n-type thin film transistor and a p-type thin film transistor,
At least one of the n-type thin film transistor and the p-type thin film transistor is the above-described thin film transistor.

A method of manufacturing a liquid crystal display device of the present invention is characterized by having the above-described method of manufacturing a thin film transistor.

Further, the liquid crystal display device of the present invention comprises: a first substrate on which the above-mentioned thin film transistor is formed, a second substrate on which a transparent common electrode is formed, the first substrate and the second substrate. It has a liquid crystal layer sandwiched between.

[0023]

EXAMPLES Example 1 FIG. 1 shows a case where PH ₃ exceeds 0% by using the ion implantation apparatus without mass separation shown in FIG.
All ions generated from a mixed gas containing 0% or less, preferably more than 0.01% and 5% or less, and the balance being Kr, are 5 × in terms of P ⁺ ions at an energy of 80 kV.
It is a figure which shows distribution of phosphorus, Kr, and hydrogen when it implants in a silicon single crystal substrate so that it may become 10 ¹⁵ pieces / cm ² .
In FIG. 1, the projected range of Kr is about half that of phosphorus. Since hydrogen is a decomposition product when PH ₃ ions are implanted, the projection range is short. FIG. 3 shows a method of adjusting the ion beam current of the insulating substrate to the polycrystalline silicon film formed on the insulating substrate and the polycrystalline silicon film to adjust the irradiation heat amount in a timely manner, and a heat source such as a heater. By using a method such as heating using 200 ° C or higher, preferably 200 ° C or higher and 350 ° C or lower, more preferably 2 ° C or higher.
Using the ion implantation apparatus without mass separation shown in FIG.
₃ more than 20% over 0%, preferably comprises 5% or less than 0.01% for all ions generated from a mixed gas and the balance of Kr, at an energy of 80 kV P ⁺
Ion conversion 1 × 10 ¹³ pieces / cm ² to 5 × 10 ¹⁵ pieces / cm ²
So that it is injected at 600 ° C, preferably above 200 ° C.
In one embodiment, the sheet resistance value with respect to the P ⁺ ion implantation amount is shown when the heat treatment is performed at a temperature of ≦ ° C., more preferably 300 ° C. or higher and 450 ° C. or lower, and particularly preferably 300 ° C. or higher and 350 ° C. or lower. is there. FIG. 4 shows a method of adjusting the ion beam current of the above-mentioned insulating substrate to the polycrystalline silicon film formed on the insulating substrate and the above-mentioned polycrystalline silicon film to adjust the irradiation heat amount at a proper time, and a heat source such as a heater. 2 is used while heating to 200 ° C. or higher, preferably 200 ° C. or higher and 350 ° C. or lower, and more preferably 200 ° C. or higher and 300 ° C. or lower, using the mass separation shown in FIG. PH ₃ is more than 0% and 20% or less, preferably 0.
All ions generated from the mixed gas containing more than 01% and 5% or less and the balance of Kr are 1 × 10 ¹³ ions / cm ² to 5 × 10 ^{15 in} terms of P ⁺ ions at an energy of 80 kV.
Injected in such a way that pieces / cm ^2, then using an ion implantation apparatus that does not use the mass separation shown in Figure 2, is injected all ions generated from a 100% hydrogen gas at 20 kV, preferably 200 Shows a sheet resistance value with respect to the H ⁺ ion implantation amount when a heat treatment is performed at a temperature of 600 ° C or higher and 600 ° C or lower, more preferably 300 ° C or higher and 450 ° C or lower, and particularly preferably 300 ° C or higher and 350 ° C or lower. This is an example. If the activation temperature decreases, the number of glass substrates that can be used increases, and a cheaper substrate can be used. In addition, the expansion and contraction of the substrate are reduced, and there is an advantage that an alignment error in manufacturing a thin film transistor can be reduced. Further, the reason for heating the substrate is to reduce defects in the polycrystalline silicon film generated during ion implantation and maintain the crystallinity of the polycrystalline silicon film. In FIGS. 3 and 4, the polycrystalline silicon film has a crystallization rate of 75% or more, preferably 90% or more. The method for producing the polycrystalline silicon film in the first half is not particularly limited, but a method by laser irradiation, a low pressure chemical vapor deposition method (LPCVD method), a plasma chemical vapor deposition method (P
CVD method) or the like can be used. In this embodiment, hydrogen ions generated from 100% hydrogen gas are continuously implanted with an energy of 20 kV by using the ion implantation apparatus shown in FIG. 2 which does not use mass separation. The energy can be adjusted in a timely manner by the thickness and type of the gate insulating film and the implanted ion species, like the ion implantation apparatus generally used for manufacturing semiconductor devices, and is limited to this embodiment. Not the one. For example, in the case of using the ion implantation apparatus that does not use mass separation shown in FIG. 2, most of the ions ionized from 100% hydrogen gas are H ₂ ⁺ , and in order to carry out hydrogenation efficiently, The implantation energy of 20 kV is set so that the maximum concentration of ₂ ^{+ in} the depth direction comes to the interface between the polycrystalline silicon film and the SiO ₂ film of the previous period. However, in the case where H ⁺ is generated as the main ion, the same effect can be obtained by setting the energy at the time of implantation to about 10 kV. When the thickness of the SiO ₂ film is 800 Å, PH ₃ is set to more than 0% and 20% or less, preferably 0.01% by using the ion implantation apparatus which does not use mass separation. Includes less than 5% and balance is Kr
Ions produced from a mixed gas consisting of 1 x 10 ¹³ ions / cm ² to 5 x in terms of P ⁺ ions at an energy of 50 kV
The polycrystal silicon film is implanted through the SiO ₂ film having a thickness of 800 Å deposited on the polycrystal silicon film so as to obtain 10 ¹⁵ pieces / cm ^2, and the mass separation of FIG. 2 is continuously performed. 100% using an ion implanter not used
Hydrogen ions generated from hydrogen gas may be implanted with an energy of 12 kV. In the present embodiment, when the impurity ions and hydrogen ions are implanted, the implantation energy is set so that the peak concentration of the implanted ions becomes the maximum concentration, but the maximum concentration is not necessarily implanted. It does not have to match the peak concentration determined. Since the distribution of the implanted ions shows a normal distribution, for example, the implantation energy can be set so that the peak concentration of the implanted ions in the SiO ₂ film comes and the tail of the broadened distribution can be used. Is a method that can be easily analogized. That is, it is clear that the present invention does not limit the implantation energy. As can be seen from the present embodiment, the impurity-implanted polycrystalline silicon film has an implanted H ⁺ ion amount of 1 × 1.
0 × ¹⁴ pieces / cm ² or more and 1 × 10 ¹⁶ pieces / cm ² or less, more preferably 1 × 10 ¹⁵ pieces / cm ² or more, 5 × 1
When the implantation amount is 0 ¹⁵ pieces / cm ² or less, that is, the maximum concentration in the polycrystalline silicon film is 6 × 10 ¹⁸ pieces / cm ³ or more and 1 × 10 ²¹ pieces / cm ³ or less, more preferably Is 6 × 1
When it is in the range of 0 ¹⁹ pieces / cm ³ or more and 3 × 10 ²⁰ pieces / cm ³ or less, the resistance is lowered. This is because the effect of terminating asymmetric bonds in the polycrystalline silicon film by the implanted hydrogen ions and the defect caused by the implanted hydrogen ions. It is also possible to use a hydrogen plasma method in the hydrogen injection step. Further, the reason for implanting the impurity ions while heating the insulating substrate is to maintain the crystallinity of the polycrystalline silicon film. If there is no problem with the material of the insulating substrate, the higher temperature of the insulating substrate is preferable. .

Example 2 FIG. 5 is a sectional view of an example of a thin film transistor manufactured by using the present invention.
SiO ₂ for preventing diffusion of heavy metals from the glass substrate 5
Film 6, film thickness 500 to be a channel portion of a thin film transistor
A polycrystalline silicon film 7 having a thickness of about Å, a SiO ₂ film having a film thickness of 1200 Å formed as a gate insulating film 8, a gate electrode 9 made of Ta, Al, or Cr, an n-type source / drain region 10 of a thin film transistor, and SiO 2. ₂ , the interlayer insulating film 11 formed of ₂ , the source electrode 12 formed of Al,
A drain electrode 13 made of Al or ITO is shown. The embodiment of FIG. 5 will be described with reference to the process chart of FIG.
First, as shown in FIG. 6A, a SiO ₂ film 6 as an insulating film is deposited on the glass substrate 5 to a thickness of 2000 Å. The SiO ₂ film 6 is made of a heavy metal contained in the substrate,
The purpose is to prevent diffusion to the element part during heat treatment,
The substrate need not be sufficiently high in purity. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned. A film having a crystallization rate of the polycrystalline silicon of 75% or more, preferably 90% or more is used.
Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, a low resistance metal such as Al, Cr or Ta is deposited by a sputtering method to a thickness of about 3500 Å and patterned to form the gate electrode 9. Next, as shown in FIG. 6B, the temperature of the insulating substrate is 20
As shown in FIG.
P using the ion implantation apparatus shown in FIG.
All the ions 14 generated from the doping gas containing H ₃ in a concentration of more than 0% and 20% or less, preferably more than 0.01% and 5% or less and the balance of Kr are P ⁺ ion implantation amount. The source / drain region 10 is implanted with energy of 80 kV so that the range is 5 × 10 ¹⁴ pieces / cm ² or more and 5 × 10 ¹⁵ pieces / cm ² or less. Further, Kr simultaneously implanted at this time remains in the gate insulating film and the gate electrode, and does not affect the electrical characteristics of the thin film transistor. Next, as shown in FIG. 6C, impurities in the source / drain region are activated by heat treatment at 300 ° C. for 1 hour, and an SiO ₂ film is deposited as an interlayer insulating film 11 to a thickness of 5000 Å or more. Then, a contact hole is formed in the source / drain region 10,
The electrode 16 is formed of Al, ITO or the like in the drain region. According to the present invention, a thin film transistor having a thin gate electrode and a flat structure can be stably manufactured at a low temperature of about 300 ° C.

Example 3 Another method of manufacturing the thin film transistor of FIG. 5 will be described with reference to the process chart of FIG. First, as shown in FIG. 7A, a SiO ₂ film 6 as an insulating film is deposited on the glass substrate 5 to a thickness of 2000 Å. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during the heat treatment, and it is not necessary if the purity of the substrate is sufficiently high. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned. A film having a crystallization rate of the polycrystalline silicon of 75% or more, preferably 90% or more is used. Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, a low resistance metal such as Al, Cr or Ta is deposited by a sputtering method to a thickness of about 3500 Å and patterned to form the gate electrode 9. Next, as shown in FIG. 7B, the temperature of the insulating substrate is 200
While adjusting the beam current so as to be not lower than ℃, using an ion implantation apparatus without mass spectrometry shown in FIG.
₃ 20% or less than 0%, preferably at a concentration of 5% or less than 0.01% for all ions 14 generated from a doping gas balance being Kr, applying amount P ⁺ ions 1 × 10 ¹³ pieces / cm ² or more 5 × 10 ¹⁵ pieces / c
Implantation is performed on the source / drain region 10 with an energy of 80 kV so as to be in the range of m ² or less. Further, Kr simultaneously implanted at this time remains in the gate insulating film and the gate electrode, and does not affect the electrical characteristics of the thin film transistor. Next, as shown in FIG.
Using the ion implantation apparatus without mass spectrometry shown in FIG.
All ions 15 generated by using 00% H ₂ as a doping gas are 1 × 10 ¹⁴ ions / cm ² at an energy of 20 kV.
Thus, the n-type source / drain region 10 is implanted in the range of 1 × 10 ¹⁶ pieces / cm ² or less, and more preferably in the range of 1 × 10 ¹⁵ pieces / cm ² or more and 5 × 10 ¹⁵ pieces / cm ² or less. . The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment.
According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG. 7 (d), impurities in the source / drain region are heated to 300 ° C.
After heat treatment for a long time to activate, an SiO ₂ film is deposited as the interlayer insulating film 11 to a thickness of 5000 Å or more, and
A contact hole is formed in the source / drain region 10, and an electrode 16 is formed in the source / drain region with Al or ITO. According to the present invention, a thin film transistor having a thin gate electrode and a flat structure can be formed at a low temperature of about 300 ° C.
It is possible to manufacture stably.

Example 4 FIG. 8 is a sectional view of another example of a thin film transistor manufactured by using the present invention. Si for preventing diffusion of heavy metals from the glass substrate 5
O ₂ film 6, polycrystalline silicon film 1 having a film thickness of about 1000 Å which becomes a part of n-type source / drain of a thin film transistor
7. The thickness of the thin film transistor channel is 500Å
Polycrystalline silicon film 7 and SiO ₂ film 8 having a film thickness of 1200Å formed as a gate insulating film, Ta and A
1, a gate electrode 9 made of Cr, n of a thin film transistor
Type source / drain region 10, interlayer insulating film 11 made of SiO ₂ , source electrode 12 made of Al, A
1 shows the drain electrode 13 made of ITO. The embodiment of FIG. 8 will be described with reference to the process chart of FIG.
First, as shown in FIG. 9A, a SiO ₂ film 6 as an insulating film is deposited to a thickness of 2000 Å on a glass substrate 5, and then a polycrystalline silicon film 17 is deposited to a thickness of 1000 Å and then patterned. To do. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during the heat treatment, and it is not necessary if the purity of the substrate is sufficiently high. Next, the polycrystalline silicon film 7 containing no impurities is formed into 50
Deposit and pattern with a thickness of 0Å. The polycrystalline silicon films 7 and 17 have a crystallization ratio of 75% or more, preferably 90% or more. Next, the SiO ₂ film 1
The gate insulating film 8 is formed by depositing it with a thickness of about 200Å. Next, a low resistance metal such as Al, Cr or Ta is deposited by a sputtering method to a thickness of about 3500 Å and patterned to form the gate electrode 9. Next, as shown in FIG. 9B, while adjusting the beam current so that the temperature of the insulating substrate becomes 200 ° C. or higher, the ion implantation apparatus without mass spectrometry shown in FIG. 2 is used. , PH ₃ is contained in a concentration of more than 0% and less than 20%, preferably more than 0.01% and less than 5%, and the balance of all ions 14 generated from the doping gas consisting of Kr is the implantation amount of P ⁺ ions. Is 1
× 10 ¹³ / cm ² or more at 5 × 10 ¹⁵ pieces / cm ² Energy of 80kV to be equal to or less than the range, implanted into the source and drain regions 10. Further, Kr simultaneously implanted at this time remains in the gate insulating film and the gate electrode, and does not affect the electrical characteristics of the thin film transistor. Next, as shown in FIG. 9C, the impurities in the source / drain regions are heat-treated in a nitrogen atmosphere at 300 ° C. for 1 hour to be activated, and Si is used as an interlayer insulating film 11.
An O ₂ film is deposited to a thickness of 5000 Å or more, a contact hole is formed in the source / drain region 10, and an electrode 16 is formed in the source / drain region with Al or ITO.
In this embodiment, the polycrystalline silicon film in the source / drain region of the thin film transistor is thick, and therefore the resistance value of the source / drain region can be reduced.
Further, when the contact hole is formed by the dry etching method, it is possible to perform sufficient over-etching, and there is an advantage that the process stability is improved.

(Embodiment 5) Using the process diagram of FIG.
Another manufacturing method of FIG. 8 will be described. First, as shown in FIG. 10A, a SiO ₂ film 6 as an insulating film is formed on the glass substrate 5.
Is deposited to a thickness of 2000Å, then polycrystalline silicon film 1
7 is deposited to a thickness of 1000Å and patterned. The SiO ₂ film 6 is made of a heavy metal contained in the substrate,
The purpose is to prevent diffusion to the element part during heat treatment,
The substrate need not be sufficiently high in purity. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned. The polycrystalline silicon films 7 and 17 have a crystallization ratio of 75% or more, preferably 90% or more. Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, use a low resistance metal such as Al, Cr or Ta for 3500Å by the sputtering method.
The gate electrode 9 is formed by depositing with a certain thickness and patterning. Next, as shown in FIG. 10 (b), while adjusting the beam current so that the temperature of the insulating substrate becomes 200 ° C. or higher, the ion implantation apparatus without mass spectrometry shown in FIG. 2 is used. , PH ₃ in a concentration of more than 0% and less than 20%, preferably more than 0.01% and less than 5%, and the balance K.
All ions produced from a doping gas consisting of r 1
4, as applying amount P ⁺ ions is 5 × 10 ¹⁵ / cm ² or less in the range 1 × 10 ¹³ / cm ² or more 80kV
The source / drain region 10 is implanted with the energy of. Further, Kr simultaneously implanted at this time remains in the gate insulating film and the gate electrode, and does not affect the electrical characteristics of the thin film transistor. Next in FIG.
As shown in FIG. 0 (c), by using the ion implantation apparatus of FIG. 2 which does not use mass spectrometry, all the ions 15 generated as pure hydrogen as a doping gas are 1 × 10 ¹⁴ / energy at an energy of about 20 keV. cm ² or more and 1 × 10 ¹⁶ pieces / cm ² or less, more preferably 1 × 10 ¹⁵ pieces / cm ² or more and 5 × 1
It is implanted into the n-type source / drain region 10 within a range of 0 ¹⁵ pieces / cm ² or less. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG. 10D, the impurities in the source / drain regions are activated by performing heat treatment at 300 ° C. for 1 hour in a nitrogen atmosphere, and SiO 2 is used as the interlayer insulating film 11.
_Two films are deposited to a thickness of 5000 Å or more, a contact hole is formed in the source / drain region 10, and an electrode 16 is formed in the source / drain region with Al or ITO. In this embodiment, the polycrystalline silicon film in the source / drain region of the thin film transistor is thick, and therefore the resistance value of the source / drain region can be reduced. Further, when the contact hole is formed by the dry etching method, it is possible to perform sufficient over-etching, and there is an advantage that the process stability is improved.

(Example 6) FIG. 11 shows a case where B ₂ H ₆ is more than 0% and 20% or less, preferably 0.01% by using the ion implantation apparatus without mass separation shown in FIG. 2. To a silicon single crystal substrate so that all ions generated from a mixed gas containing more than 5% and less than 5% and the balance being Kr become 5 × 10 ¹⁵ ions / cm ^{2 in} terms of B ⁺ ions at an energy of 80 kV. It is a figure which shows distribution of boron, Kr, and hydrogen when it implants. In FIG. 11, the projected range of Kr is
It is about one-third of boron. Hydrogen is B ₂ H ₆
It is a decomposed product when ions are implanted and has a short projection range. FIG. 12 shows a method of adjusting the ion beam current of the above-mentioned insulating substrate to the polycrystalline silicon film formed on the insulating substrate and the above-mentioned polycrystalline silicon film to adjust the irradiation heat amount at a time, and a heat source such as a heater. Is heated to 200 ° C. or higher, preferably 200 ° C. or higher for 35
Using an ion implanter without mass separation shown in FIG. 2 while heating to 0 ° C. or lower, more preferably 200 ° C. or higher and 300 ° C. or lower, B ₂ H ₆ exceeds 0% and 20% or less. , Preferably more than 0.01% and 5% or less, with all the ions generated from the mixed gas of which the balance is Kr,
1 × 10 ¹³ pieces in energy B ⁺ ions in terms of 80kV from / cm ² 5 × 10 ¹⁵ atoms / cm ² and injected as made, preferably 600 ° C. at 300 ° C. or higher or less, more preferably 300 ° C. or higher 450 ° C or lower, more preferably 3
6 is an example showing a sheet resistance value with respect to a B ⁺ ion implantation amount when a heat treatment is performed at a temperature of 00 ° C. or higher and 350 ° C. or lower for one hour. FIG. 13 shows a method of adjusting the ion beam current to the polycrystalline silicon film formed on the insulating substrate and the polycrystalline silicon film to adjust the irradiation heat amount in a timely manner, and a heat source such as a heater. By using a method such as heating at 200 ° C or higher, preferably 200 ° C or higher and 350 ° C or lower, and more preferably 200 ° C or higher and 30
While heating to 0 ° C. or lower, using an ion implantation apparatus without mass separation shown in FIG. 2, B ₂ H ₆ exceeds 0% and 20% or less, preferably 0.01% and 5%. All of the ions that are included below and that are generated from the mixed gas of which the balance is Kr are 1 × in terms of B ⁺ ions at an energy of 80 kV.
Implantation is performed at 10 ¹³ ions / cm ² to 5 × 10 ¹⁵ ions / cm ^2, and then all ions generated from 100% hydrogen gas are injected at 20 kV, preferably at 200 ° C. or higher and 600 ° C.
Or less, more preferably 300 ° C or higher and 450 ° C or lower,
More preferably, it is an example showing the sheet resistance value with respect to the H ⁺ ion implantation amount when the heat treatment is performed at 300 ° C. or higher and 350 ° C. or lower for one hour. If the activation temperature decreases, the number of glass substrates that can be used increases, and a cheaper substrate can be used. In addition, the expansion and contraction of the substrate are reduced, and there is an advantage that an alignment error in manufacturing a thin film transistor can be reduced.
Further, the reason for heating the substrate is to reduce defects in the polycrystalline silicon film generated during ion implantation and maintain the crystallinity of the polycrystalline silicon film. 12 and 13, the polycrystalline silicon film has a crystallization rate of 75% or more, preferably 90% or more. The method for producing the polycrystalline silicon film in the first half is not particularly limited, but a method by laser irradiation or a low pressure chemical vapor deposition method (LPCVD
Method), a plasma chemical vapor deposition method (PCVD method), or the like. In this embodiment, the ion implantation apparatus without mass separation shown in FIG.
Hydrogen ions generated from 00% hydrogen gas are implanted at an energy of 20 kV. The energy at the time of implantation is the same as that of an ion implantation apparatus generally used for manufacturing a semiconductor device, which is the thickness of the gate insulating film. Size and type,
It is possible to make timely adjustments depending on the implanted ion species, and the present invention is not limited to this example. For example, in the case of using the ion implanter without mass separation shown in FIG. 2, most of the ions ionized from 100% hydrogen gas are H ₂ ⁺ , and in order to carry out hydrogenation efficiently,
The implantation energy of 20 kV is set so that the maximum concentration of H ₂ ^{+ in} the depth direction comes to the interface between the polycrystalline silicon film and the SiO ₂ film of the previous period. However, in the case where H ⁺ is generated as the main ion, the same effect can be obtained by setting the energy at the time of implantation to about 10 kV.
Similarly, in the case of using the ion implantation apparatus of FIG. 2 which does not use mass separation, B ₂ H ₆ is contained in an amount of more than 0% and 20% or less, preferably more than 0.01% and 5% or less and the balance Kr. ions generated from a mixed gas of the energy of 80kV for B ₂ H _x ⁺ ions is the primary, and devote myself. However, when B ⁺ ions are mainly produced, 4
Energy of 0 kV is sufficient. When the SiO ₂ film has a thickness of 800 Å, B ₂ H ₆ is more than 0% and not more than 20%, preferably 0.01% or less by using the ion implantation apparatus without mass separation shown in FIG. % And 5% or less, with the balance being 50 kV of ions generated from a mixed gas containing Kr.
800 Å deposited on the polycrystalline silicon film on the polycrystalline silicon film so as to be 1 × 10 ¹³ pieces / cm ² to 5 × 10 ¹⁵ pieces / cm ^{2 in} terms of B ⁺ ions at the energy of
By implanting through a SiO ₂ film having the thickness of
Hydrogen ions generated from 00% hydrogen gas may be implanted with an energy of 12 kV. In the present embodiment, when the impurity ions and hydrogen ions are implanted, the implantation energy is set so that the peak concentration of the implanted ions becomes the maximum concentration, but the maximum concentration is not necessarily implanted. It does not have to match the peak concentration determined. Since the distribution of the implanted ions shows a normal distribution, for example, the implantation energy can be set so that the peak concentration of the implanted ions in the SiO ₂ film comes and the tail of the broadened distribution can be used. And
This is an easy analogy. That is, it is clear that the present invention does not limit the implantation energy. As can be seen from the present embodiment, the impurity-implanted polycrystalline silicon film has an implanted H ⁺ ion amount of 1 ×.
When the implantation amount is 10 ¹⁴ pieces / cm ² or more and 1 × 10 ¹⁶ pieces / cm ² or less, more preferably 1 × 10 ¹⁵ pieces / cm ² or more and 5 ×
When the implantation amount is 10 ¹⁵ pieces / cm ² or less, that is, the maximum concentration in the polycrystalline silicon film is 6 × 10 ¹⁸ pieces / cm ³ or more and 1 × 10 ²¹ pieces / cm ³ or less, more preferably Is 6 ×
When it is in the range of 10 ¹⁹ pieces / cm ³ or more and 3 × 10 ²⁰ pieces / cm ³ or less, the resistance is lowered. This is due to the effect of termination of asymmetric bonds in the polycrystalline silicon film by the implanted hydrogen ions and competition with the defects caused by the implanted hydrogen ions. It is also possible to use a hydrogen plasma method in the hydrogen injection step. Further, the reason for implanting the impurity ions while heating the insulating substrate is to maintain the crystallinity of the polycrystalline silicon film. If there is no problem with the material of the insulating substrate, the higher temperature of the insulating substrate is preferable. .

Example 7 FIG. 14 is a sectional view of an example of a thin film transistor manufactured by using the present invention. Si for preventing diffusion of heavy metals from the glass substrate 5
O ₂ film 6, film thickness 5 to be the channel part of the thin film transistor
Polycrystalline silicon film 7 of about 00Å, SiO ₂ film having a film thickness of 1200Å formed as the gate insulating film 8, T
a, a gate electrode 9 made of Al, Cr, a p-type source / drain region 18 of a thin film transistor, an interlayer insulating film 11 made of SiO ₂ , a source electrode 1 made of Al
2. Drain electrode 13 made of Al or ITO
Indicates. The embodiment of FIG. 14 will be described with reference to the process chart of FIG. First, as shown in FIG. 15A, the glass substrate 5
A SiO ₂ film 6 as an insulating film is deposited thereon with a thickness of 2000 Å. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during the heat treatment, and it is not necessary if the purity of the substrate is sufficiently high. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned. A film having a crystallization rate of the polycrystalline silicon of 75% or more, preferably 90% or more is used. Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, Al, Cr and Ta
A low resistance metal such as is deposited by sputtering to a thickness of about 3500 Å and patterned to form the gate electrode 9. Next, as shown in FIG. 15B, while adjusting the beam current so that the temperature of the insulating substrate becomes 200 ° C. or higher, the ion implantation apparatus without mass spectrometry shown in FIG. 2 is used. , B ₂ H ₆ in a concentration of more than 0% and less than 20%, preferably more than 0.01% and less than 5% and the balance being Kr, all ions generated from the doping gas 19
Is implanted into the source / drain region 18 with an energy of 80 kV so that the implantation amount of B ⁺ ions is in the range of 5 × 10 ¹⁴ / cm ² or more and 5 × 10 ¹⁵ / cm ² or less.
Further, Kr simultaneously implanted at this time remains in the gate insulating film and the gate electrode, and does not affect the electrical characteristics of the thin film transistor. Next, FIG.
As shown in (C), impurities in the source / drain region are activated by heat treatment at 300 ° C. for 1 hour, and an SiO ₂ film is deposited as the interlayer insulating film 11 to a thickness of 5000 Å or more. A contact hole is formed in the source / drain region 18, and an electrode 16 is formed in the source / drain region with Al or ITO. According to the present invention, a thin film transistor having a thin gate electrode and a flat structure is provided at 300 ° C.
It is possible to stably manufacture at a low temperature.

(Embodiment 8) Using the process chart of FIG.
Another method of manufacturing the thin film transistor of FIG. 14 will be described.
First, as shown in FIG. 16A, a SiO ₂ film 6 as an insulating film is deposited on the glass substrate 5 to a thickness of 2000 Å.
The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during the heat treatment, and it is not necessary if the purity of the substrate is sufficiently high. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned. A film having a crystallization rate of the polycrystalline silicon of 75% or more, preferably 90% or more is used. Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, a low resistance metal such as Al, Cr or Ta is deposited by a sputtering method to a thickness of about 3500 Å and patterned to form the gate electrode 9.
Next, as shown in FIG. 16 (b), while adjusting the beam current so that the temperature of the insulating substrate becomes 200 [deg.] C. or higher, an ion implantation apparatus without mass spectrometry shown in FIG. 2 is used. , B ₂ H ₆ is more than 0% and 20% or less, preferably 0.
All the ions 19 generated from the doping gas containing more than 01% and less than 5% and the balance of Kr are B,
⁺ 5 × 1 when the ion implantation amount is 1 × 10 ¹³ / cm ² or more
The source / drain region 18 is implanted with energy of 80 kV so as to be in the range of 0 ¹⁵ pieces / cm ² or less. Also,
The Kr implanted at this time stops in the gate insulating film and the gate electrode, and has no effect on the electrical characteristics of the thin film transistor. Next, as shown in FIG. 16 (c), using the ion implantation apparatus of FIG. 2 which does not use mass spectrometry, all the ions 15 generated with 100% H ₂ as a doping gas are 1 × at an energy of 20 kV. 1
0 ¹⁴ pieces / cm ² or more and 1 × 10 ¹⁶ pieces / cm ² or less, more preferably 1 × 10 ¹⁵ pieces / cm ² or more and 5 × 10 ¹⁵ pieces / cm ²
The p-type source / drain regions 18 are implanted in the following range. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, in FIG.
As shown in (d), impurities in the source / drain region are activated by heat treatment at 300 ° C. for 1 hour, and a SiO ₂ film is deposited as the interlayer insulating film 11 to a thickness of 5000 Å or more. A contact hole is formed in the source / drain region 18, and an electrode 16 is formed in the source / drain region with Al or ITO. According to the present invention, a thin film transistor having a thin gate electrode and a flat structure is provided at 300 ° C.
It is possible to stably manufacture at a low temperature.

Example 9 FIG. 17 is a sectional view of another example of a thin film transistor manufactured by using the present invention. Si for preventing diffusion of heavy metals from the glass substrate 5
O ₂ film 6, polycrystalline silicon film 2 having a film thickness of about 1000 Å which becomes a part of p-type source / drain of a thin film transistor
0, thickness of the thin film transistor channel 500 Å
Polycrystalline silicon film 7 and SiO ₂ film 8 having a film thickness of 1200Å formed as a gate insulating film, Ta and A
l, a gate electrode 9 made of Cr, p of a thin film transistor
Type source / drain region 18, interlayer insulating film 11 made of SiO ₂ , source electrode 12 made of Al, A
1 shows the drain electrode 13 made of ITO. The embodiment of FIG. 17 will be described with reference to the process chart of FIG. First, as shown in FIG. 18A, a SiO ₂ film 6 as an insulating film is deposited on the glass substrate 5 to a thickness of 2000 Å, and then a polycrystalline silicon film 20 is deposited to a thickness of 1000 Å and then patterned. To do. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during the heat treatment, and it is not necessary if the purity of the substrate is sufficiently high. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned.
The crystallization rate of the polycrystalline silicon films 7 and 20 is 75%.
Above, preferably 90% or more of the film is used. Then SiO
_Two films are deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, a low resistance metal such as Al, Cr or Ta is deposited by a sputtering method to a thickness of about 3500 Å and patterned to form the gate electrode 9. Next, in FIG.
As shown in (b), the temperature of the insulating substrate is 200 ° C.
While adjusting the beam current as described above, B ₂ H ₆ was used by using the ion implantation apparatus without mass spectrometry shown in FIG.
The 20% or less than 0%, preferably at a concentration of 5% or less than 0.01% for all ions 19 generated from a doping gas balance being Kr, applying amount B ⁺ ions 1 × 10 ¹³ / cm ² or more at 5 × 10 ¹⁵ pieces / cm ²
The source / drain region 18 is implanted with an energy of 80 kV so as to be in the following range. Further, Kr simultaneously implanted at this time remains in the gate insulating film and the gate electrode, and does not affect the electrical characteristics of the thin film transistor. Next, as shown in FIG.
Impurities in the source / drain region are removed in a nitrogen atmosphere to 300
After heat treatment at 1 ° C. for 1 hour to activate, an SiO ₂ film is deposited as the interlayer insulating film 11 to a thickness of 5000 Å or more, a contact hole is formed in the source / drain region 18, and the source / drain region 18 is formed. The electrode 16 is formed of Al, ITO or the like in the drain region. In this embodiment, the polycrystalline silicon film in the source / drain region of the thin film transistor is thick,
Therefore, the resistance value of the source / drain region can be reduced. Further, when the contact hole is formed by the dry etching method, it is possible to perform sufficient over-etching, and there is an advantage that the process stability is improved.

(Embodiment 10) Another manufacturing method of FIG. 17 will be described with reference to the process chart of FIG. First, FIG.
As shown in (a), S is used as an insulating film on the glass substrate 5.
The iO ₂ film 6 is deposited to a thickness of 2000Å, and then the polycrystalline silicon film 20 is deposited to a thickness of 1000Å and patterned. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during the heat treatment, and it is not necessary if the purity of the substrate is sufficiently high. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned. The polycrystalline silicon films 7 and 20 have a crystallization rate of 75% or more, preferably 90% or more. Next, put a SiO ₂ film on 1200 Å
A gate insulating film 8 is formed by depositing the gate insulating film 8 with a certain thickness. Then A
l, Cr, Ta or other low resistance metal is deposited by sputtering or the like to a thickness of about 3500Å, and patterned to obtain a target.
The electrode 9 is formed. Next, as shown in FIG.
The temperature of the insulating substrate should be 200 ° C or higher.
B ₂ H ₆ at a concentration of more than 0% and 20% or less, preferably more than 0.01% and 5% or less by using the ion implantation apparatus shown in FIG. 2 without adjusting the mass current. wherein, all of the ions 19 generated from a doping gas balance being Kr, applying amount B ⁺ ions of 1 × 10
^With the energy of 80 kV, the source / drain region 1 should be in the range of ¹³ / cm ² or more and 5 × 10 ¹⁵ / cm ² or less.
Type in 8. Also, at this time, Kr
Stops in the gate insulating film and the gate electrode,
It has no effect on the electrical characteristics of the thin film transistor. Next, as shown in FIG. 19 (c), using the ion implantation apparatus without mass spectrometry shown in FIG. 2, all the ions 15 generated as pure hydrogen as a doping gas are 1 × 10 at an energy of about 20 keV. 1 x 10 ¹⁶ with ¹⁴ pieces / cm ² or more
Pieces / cm ² or less in the range of, more preferably 1 × 10 ¹⁵ pieces / cm ²
With the above, p-type source within the range of 5 × 10 ¹⁵ pieces / cm ² or less
Implant into the drain region 18. Energy when driving
Can be adjusted according to the thickness of the gate insulating film,
The present invention is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG. 19 (d), impurities in the source / drain region are heated to 300 ° C. in a nitrogen atmosphere at 1 ° C.
After heat treatment for a long time to activate, an SiO ₂ film is deposited as the interlayer insulating film 11 to a thickness of 5000 Å or more, and
A contact hole is formed in the source / drain region 18, and an electrode 16 is formed in the source / drain region with Al or ITO. In this embodiment, the polycrystalline silicon film in the source / drain region of the thin film transistor is thick, and
The resistance value of the source / drain regions can be reduced. Further, when the contact hole is formed by the dry etching method, it is possible to perform sufficient over-etching, and there is an advantage that the process stability is improved.

(Embodiment 11) FIG. 20 shows an embodiment of a complementary (CMOS) thin film transistor formed by using the present invention. A SiO ₂ film 6 for preventing the diffusion of heavy metals from the glass substrate 5, a polycrystalline silicon film 7 having a film thickness of about 500Å to be a channel portion of a thin film transistor, and a Si film having a film thickness of 1200Å formed as a gate insulating film 8.
O ₂ film, gate electrode 9 made of Ta, Al, Cr, n-type source / drain region 10 and p-type source / drain region 18 of thin film transistor, interlayer insulating film 11 made of SiO ₂ , Al or ITO Formed electrode 1
6 is shown. The embodiment of FIG. 20 will be described with reference to the process drawing 21. First, as shown in FIG. 21A, a SiO ₂ film 6 as an insulating film is deposited on the glass substrate 5 to a thickness of 2000 Å. The purpose of the SiO ₂ film 6 is to prevent heavy metals contained in the substrate from diffusing into the element portion during the heat treatment, and it is not necessary if the purity of the substrate is sufficiently high. Next, a polycrystalline silicon film 7 containing no impurities is deposited to a thickness of about 500Å and patterned. A film having a crystallization rate of the polycrystalline silicon of 75% or more, preferably 90% or more is used. Next, a SiO ₂ film is deposited to a thickness of about 1200Å to form the gate insulating film 8. Next, a low resistance metal such as Al, Cr or Ta is deposited by a sputtering method to a thickness of about 3500 Å and patterned to form the gate electrode 9. Next, as shown in FIG. 21B, a material which can be selectively removed from the gate electrode in a region to be an n-type thin film transistor including the n-type source / drain region 10, for example, the gate electrode is made of Cr. Or Ta in the case of Al,
Using a reverse combination of the above and polyimide, which is a heat-resistant organic material, a mask is formed with a thickness that can prevent implantation of p-type impurities. The temperature of the insulating substrate is 200
℃ Tsugumi so that the above - while adjusting the beam current, using an ion implantation apparatus that does not use the mass spectrometer shown in FIG. 2, B ₂
All the ions 19 generated from the doping gas containing H ₆ in a concentration of more than 0% and 20% or less, preferably more than 0.01% and 5% or less and the balance of Kr are B ⁺ ion implantation amount. The p-type source / drain region 18 is implanted with energy of 80 kV so as to be in the range of 1 × 10 ¹³ pieces / cm ² or more and 5 × 10 ¹⁵ pieces / cm ² or less. The Kr implanted at this time stops in the gate insulating film and the gate electrode, and has no effect on the electrical characteristics of the thin film transistor. Next, as shown in FIG. 21C, a region, which includes the p-type source / drain region 18 and becomes the p-type thin film transistor, is made of a material that can be selectively removed from the gate electrode, such as a gate electrode. In the case of Cr or Ta, Al, a reverse combination of the above and polyimide, which is a heat-resistant organic material, are used.
The mask is formed with a thickness that can prevent the implantation of mold impurities. Next, while adjusting the beam current so that the temperature of the insulating substrate becomes 200 ° C. or higher, PH ₃ exceeds 0% and exceeds 20% by using the ion implantation apparatus shown in FIG.
% Or less, preferably more than 0.01% and 5% or less, and the P ⁺ ion implantation amount of all ions 14 generated from the doping gas with the balance being Kr is 1 × 1.
The n-type source / drain region 10 is implanted with an energy of 80 kV so as to be in a range of 0 ¹³ pieces / cm ² or more and 5 × 10 ¹⁵ pieces / cm ² or less. Kr was driven in at the same time
Stops in the gate insulating film and the gate electrode,
It has no effect on the electrical characteristics of the thin film transistor. Next, as shown in FIG. 21D, all ions 15 generated by using 100% H ₂ as a doping gas are converted to 20 k
The energy of V is 1 × 10 ¹⁴ pieces / cm ² and 1 × 10 ¹⁶
Pieces / cm ² or less in the range of, more preferably 1 × 10 ¹⁵ pieces / cm ²
As described above, the implantation is performed in the source / drain regions 10 and 18 in a range of 5 × 10 ¹⁵ pieces / cm ² or less. The energy at the time of implantation may be appropriately adjusted depending on the thickness of the gate insulating film, and is not limited to this embodiment. According to this method, the crystallinity of the polycrystalline silicon film in which impurities are implanted is maintained, and at the same time, the defects in the polycrystalline silicon film are filled with hydrogen. Next, as shown in FIG.
Impurities in the source / drain regions are activated by heat treatment at 300 ° C. for 1 hour to form Si as the interlayer insulating film 11.
An O ₂ film is deposited to a thickness of 5000 Å or more to form contact holes in the source / drain regions 10 and 18, and
The electrode 16 is formed of Al, ITO or the like in the drain region. In the present embodiment, p-type impurities are first implanted, and then n-type impurities are implanted, but there is no particular restriction on the order of implantation, and any impurity may be implanted first. Similarly, in the present embodiment, p-type impurities are implanted, then n-type impurities are implanted, and then hydrogen is collectively implanted into the source / drain regions 10 and 18, but of course individually. It is also possible to inject. Further, if the impurity implantation amount is 5 × 10 ¹⁴ / cm ² or more, the hydrogen implantation step can be omitted. In addition, the source / drain regions 10 and 18 of this embodiment are replaced with those of the fourth embodiment.
Also, it is possible to change to the structure as shown in the ninth embodiment.

(Embodiment 12) FIG. 22 is a sectional view of a liquid crystal display device when an n-type or p-type thin film transistor formed by using the present invention is used as a pixel driving thin film transistor of a liquid crystal display device. Reference numeral 21 is an insulating substrate on which thin film transistors are formed, 22 is a counter substrate, and 23 is a liquid crystal. As the thin film transistor used in FIG. 18, the thin film transistor described in this specification or a similar thin film transistor which can be easily analogized is used. FIG. 23 shows an equivalent circuit diagram. The auxiliary capacitance in FIG. 23 is
It can be built by a method of providing a capacitance line or a method of providing a capacitance between the gate line and the gate line one stage before driving.
Also, the external driver circuit of the liquid crystal display device shown in FIG. 22 can be formed by the complementary (CMOS) thin film transistor described in the eleventh embodiment.

[0035]

The present invention has the following effects.

(1). Injection of a diluent gas into the polycrystalline silicon film in the channel portion of the thin film transistor, which is a problem in the ion implantation apparatus that does not use mass spectrometry, can be prevented without thickening the gate electrode, and a flat thin film transistor can be manufactured.

(2). A thin film transistor can be manufactured at a low temperature of about 300 ° C., and a glass substrate can be used.

(3). Stabilization of the characteristics is achieved due to the implantation method, which has less influence on the characteristics of the thin film transistor.

(4). An inexpensive glass substrate can be used.

(5). It is possible to use a metal having a low resistance for the gate wiring, and the delay of the gate signal can be reduced. Therefore, the image quality is improved.

(6). By using a gas obtained by diluting impurities with Kr for forming the n-type or p-type region, it becomes easy to control the amount of hydrogen required for forming the n-type or p-type region.

(7). Kr ions are inactive and have almost no influence on the characteristics of the thin film transistor.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an example of distributions of phosphorus, Kr, and hydrogen implanted by using an ion implantation apparatus that does not use mass spectrometry.

FIG. 2 is a cross-sectional view showing an example of an ion implantation apparatus that does not use mass spectrometry.

FIG. 3 is a diagram showing a sheet resistance value with respect to an implantation amount of P ⁺ ions.

FIG. 4 is a diagram showing a sheet resistance value of a polycrystalline silicon film in which phosphorus is implanted with respect to the amount of H ⁺ ion implantation.

FIG. 5 is a cross-sectional view showing an example of a thin film transistor manufactured by using the present invention.

FIG. 6 is a process drawing showing an example of a thin film transistor manufactured by using the present invention.

FIG. 7 is a process drawing showing an example of a thin film transistor manufactured by using the present invention.

FIG. 8 is a cross-sectional view showing another example of a thin film transistor manufactured by using the present invention.

FIG. 9 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 10 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 11 is a cross-sectional view showing an example of distributions of boron, Kr, and hydrogen implanted by using an ion implanter that does not use mass spectrometry.

FIG. 12 is a diagram showing the sheet resistance value with respect to the implantation amount of B ⁺ ions.

FIG. 13 is a diagram showing a sheet resistance value of a polycrystalline silicon film in which boron is implanted, with respect to an amount of H ⁺ ions implanted.

FIG. 14 is a cross-sectional view showing an example of a thin film transistor manufactured by using the present invention.

FIG. 15 is a process drawing showing an example of a thin film transistor manufactured by using the present invention.

FIG. 16 is a process drawing showing an example of a thin film transistor manufactured by using the present invention.

FIG. 17 is a cross-sectional view showing another example of a thin film transistor manufactured by using the present invention.

FIG. 18 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 19 is a process drawing showing another example of a thin film transistor manufactured by using the present invention.

FIG. 20 is a sectional view showing an example of a complementary thin film transistor manufactured by using the present invention.

FIG. 21 is a process drawing showing an example of a complementary thin film transistor manufactured by using the present invention.

FIG. 22 is a cross-sectional view showing an example of a liquid crystal display device manufactured using the thin film transistor of the present invention.

FIG. 23 is an equivalent circuit diagram showing an example of a liquid crystal display device manufactured using the thin film transistor of the present invention.

[Explanation of symbols]

1 Plasma Source 2 Impurity Ion 3 Extraction Electrode 4 Acceleration Electrode 5 Glass Substrate 6 SiO ₂ Film 7 Polycrystalline Silicon Film 8 Gate Insulation Film 9 Gate Electrode 10 n-Type Source / Drain Region 11 Interlayer Insulation Film 12 Source Electrode 13 Drain Electrode 14 All ions containing PH ₃ and the rest being Kr made from the doping gas 15 All ions producing pure hydrogen as the doping gas 16 Electrodes 17 Part of the n-type source / drain of the thin film transistor About 1000Å Polycrystalline silicon film 18 p-type source / drain regions 19 B ₂ H ₆ and the rest are all ions generated from a doping gas consisting of Kr 20 A film thickness which is a part of p-type source / drain of a thin film transistor Polycrystalline silicon film of about 1000Å 21 Thin film transistor And an insulating substrate 22 counter substrate 23 liquid crystal

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 27/08 331 H01L 27/08 321B 27/12 29/78 627F 21/336

Claims (21)

[Claims] 1. A polycrystalline silicon film forming step of forming a polycrystalline silicon film on an insulating substrate, and an insulating film forming step of forming an insulating film on the polycrystalline silicon film.
(3) Impurities exceeding 0% and 20% or less and the balance Kr
An impurity ion implantation step of implanting ions generated from a mixed gas consisting of the above into the polycrystalline silicon film through the insulating film while heating the insulating substrate to 200 ° C. or higher; and (4) the impurity ion implantation. A method of manufacturing a semiconductor device, comprising an impurity activation step of heating the insulating substrate to 200 ° C. or higher after the implantation step. 2. A hydrogen ion implanting step of implanting hydrogen ions generated from hydrogen gas into the polycrystalline silicon film through the insulating film between the impurity ion implanting step and the impurity activating step. The method for manufacturing a semiconductor device according to claim 1, further comprising: 3. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is PH ₃ . 4. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is B ₂ H ₆ . 5. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 4. 6. An insulating substrate, a polycrystalline silicon thin film formed on the insulating substrate, and an insulating film formed on the polycrystalline silicon thin film, wherein the polycrystalline silicon and the insulating film are A semiconductor device comprising Kr. 7. A polycrystalline silicon film forming step of forming a polycrystalline silicon film on an insulating substrate, and an insulating film forming step of forming an insulating film on the polycrystalline silicon film.
(3) A gate electrode forming step of forming a gate electrode on the insulating film, and (4) ions generated from a mixed gas containing impurities in an amount of more than 0% and 20% or less and the balance of Kr,
Impurity ions for implanting into the polycrystalline silicon film through the insulating film using the gate electrode as a mask while heating the insulating substrate to 200 ° C. or more to form the source region and the drain region of the thin film transistor in a self-aligned manner. A method of manufacturing a thin film transistor, comprising: an implanting step; and (5) an impurity activating step of activating the impurities by heating the insulating substrate to 200 ° C. or higher after the impurity ion implanting step. 8. A hydrogen ion implanting step of implanting hydrogen ions generated from hydrogen gas into the polycrystalline silicon film through the insulating film between the impurity ion implanting step and the impurity activating step. The method for producing a thin film transistor according to claim 7, further comprising: 9. The method of manufacturing a thin film transistor according to claim 7, wherein the impurity is PH ₃ . 10. The method of manufacturing a thin film transistor according to claim 7, wherein the impurity is B ₂ H ₆ . 11. A thin film transistor manufactured by the method of manufacturing a thin film transistor according to claim 7. 12. A thin film transistor having a planar top gate structure formed on an insulating substrate, wherein Kr is contained in a region of the gate insulating film, which is in contact with the source region or the drain region, the source region and the drain region. And a thin film transistor. 13. The thin film transistor according to claim 11, wherein the source region and the drain region contain phosphorus as an impurity. 14. The thin film transistor according to claim 11, wherein the source region and the drain region contain boron as an impurity. 15. (1) A polycrystalline silicon film forming step of forming a polycrystalline silicon film on an insulating substrate; (2) An insulating film forming step of forming an insulating film on the polycrystalline silicon film; ) A gate electrode forming step of forming a gate electrode on the insulating film, and (4) 0% of a first impurity to be an n-type
Ions generated from a mixed gas containing more than 20% but less than 20% and the remainder being a diluent gas are implanted into the polycrystalline silicon film through the insulating film while heating the insulating substrate to 200 ° C. or more, and self-aligned. N-type impurity ion implantation step for forming an n-type source region and a drain region,
(5) While heating the insulating substrate to 200 ° C. or higher, the ions generated from the mixed gas containing the p-type second impurity in the range of more than 0% and 20% or less and the balance of the dilution gas are
P-type impurity ion implantation step of implanting into the polycrystalline silicon film through the insulating film to form p-type source and drain regions in a self-aligned manner, (6) the insulating substrate at 200 ° C. or higher And a step of activating the impurities to activate the n-type impurities and the p-type impurities. 16. Hydrogen ions generated from hydrogen gas are passed through the insulating film after the n-type impurity ion implantation step and the p-type impurity ion implantation step and before the impurity activation step. 16. The method of manufacturing a complementary thin film transistor according to claim 15, further comprising a step of implanting hydrogen ions into the source region and the drain region of the thin film transistor via the above. 17. The method of manufacturing a complementary thin film transistor according to claim 15, wherein the first impurity is PH ₃ and the second impurity is B ₂ H ₆ . 18. A complementary thin film transistor manufactured by the method for manufacturing a complementary thin film transistor according to claim 15. Description: 19. A complementary (CMOS) thin film transistor comprising an n-type thin film transistor and a p-type thin film transistor, wherein at least one of the n-type thin film transistor and the p-type thin film transistor is included.
9. A complementary thin film transistor, which is the thin film transistor according to any one of items 1. 20. A method of manufacturing a liquid crystal display device, comprising the method of manufacturing a thin film transistor according to claim 7. 21. A first substrate on which the thin film transistor according to claim 11 is formed, a second substrate on which a transparent common electrode is formed, the first substrate and the second substrate. A liquid crystal display device having a liquid crystal layer sandwiched between the substrate and the substrate.