JPH08213596A - Manufacture of semiconductor integration circuit - Google Patents

Abstract

PURPOSE: To realize a manufacturing method of a semiconductor integration circuit allowed to prevent an increase of a leakage current and lowered breakdown voltage of MOS FET without changing a structure of MOS FET to be finally manufactured. CONSTITUTION: In processes forming a MOS FET, a process forming a diffusion layer by performing heat diffusion treatment is followed by a process forming a gate electrode 20 having conductivity by diffusing an impurity into a polycrystalline silicon film 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a high breakdown voltage MOS FE.
The present invention relates to a method of manufacturing a semiconductor integrated circuit for making T.

[0002]

2. Description of the Related Art As a high breakdown voltage MOS FET, for example, there is a double diffusion type MOS FET (hereinafter referred to as DMOS). The DMOS is a MOSFET in which a deep diffusion layer is formed on a substrate by a thermal diffusion process at high temperature for a long time and a shallow diffusion layer is formed in the deep diffusion layer. In the dual diffusion layer, the deep diffusion layer is assigned to the gate region and the shallow diffusion layer is assigned to the source region.

FIG. 2 is a process diagram showing a conventional DMOS manufacturing method. The manufacturing procedure will be described below with reference to the process chart of FIG. (1) As shown in FIG. 2A, an insulating film 2 (for example, an oxide film) is formed on a low-concentration substrate 1 (for example, an N ⁻ type substrate). (2) As shown in FIG. 2B, a polycrystalline silicon film 3 is formed on the insulating film 2, and a high concentration of phosphorus is diffused into the polycrystalline silicon film 3. (3) A resist 4 is formed on the polycrystalline silicon film 3 and the resist 4 is patterned. Then, as shown in FIG. 2C, the polycrystalline silicon film 3 is etched using the patterned resist 4 as a mask to form a gate electrode 5. (4) The resist 4 is removed, and then the resist 6 is formed on the substrate 1. Then, as shown in FIG. 2D, a part of the resist 6 is opened, and a P-type impurity is injected through the opening. The implanted impurities are shown by the dotted line in the figure. (5) As shown in FIG. 2E, a very deep P-type layer 7 is formed by thermal diffusion treatment at high temperature for a long time. At this time,
The P-type layer 7 extends below the gate electrode 5. (6) A resist 8 is formed on the substrate 1. And FIG.
As shown in (f), a part of the resist 8 is opened, and N-type impurities are injected from the opening. The implanted impurities are shown by the dotted line in the figure. (7) The resist 8 is removed, and then an annealing treatment (activation) is performed as shown in FIG.
To form. (8) As shown in FIG. 2H, the insulating film 11 is formed on the substrate 1.
Then, the insulating film is etched to form the electrode lead-out portion 12. (9) Metal electrodes 13 to 15 are formed as shown in FIG. The P-type layer 7, the N-type layer 9 and the N-type layer 10 respectively form a gate, a source and a drain of the MOS FET. The metal electrodes 13, 14 and 15 are connected to the source, the gate and the drain, respectively. A MOS FET is manufactured through the above steps.

However, the conventional example shown in FIG. 2 has the following problems. In this manufacturing method, after phosphorus is diffused into the polycrystalline silicon film 3, a thermal diffusion process is performed at high temperature for a long time in order to form the P-type layer 7. Therefore, phosphorus doped in the polycrystalline silicon film 3 by thermal diffusion treatment at high temperature for a long time precipitates at the crystal grain boundaries, and the rate of self-diffusion of silicon atoms is controlled through the grain boundaries. As a result, silicon crystal grains grow. At this time, stress may be applied to the underlying insulating film 2 of the polycrystalline silicon film 3 to deteriorate its insulating property, which causes an increase in leakage current of the MOS FET and a decrease in breakdown voltage.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the step of diffusing impurities in a polycrystalline silicon film is performed by a thermal diffusion treatment for forming a deep diffusion layer. By bringing it after the process of
It is an object of the present invention to realize a method for manufacturing a semiconductor integrated circuit capable of preventing an increase in leakage current and a decrease in breakdown voltage of a MOS FET without changing the structure of the finally formed MOS FET.

[0006]

According to the present invention, a first step of diffusing an impurity in a polycrystalline silicon film to form a gate electrode having conductivity and an impurity is injected into a substrate to perform a thermal diffusion treatment. A second step of forming a diffusion layer by means of the above method, wherein the first step comes after the second step in the method for manufacturing a semiconductor integrated circuit in which a MOS FET is formed on a substrate. And a method for manufacturing a semiconductor integrated circuit.

[0007]

According to the present invention as described above, in the process of forming a MOS FET, impurities are added to the polycrystalline silicon film after the process of injecting impurities into the substrate and performing thermal diffusion treatment to form a diffusion layer. To form a gate electrode having conductivity.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG.
FIG. 3 is a process chart showing an embodiment of a method according to the present invention. 1 that are the same as those in FIG. 2 are given the same reference numerals. FIG.
The manufacturing procedure will be described with reference to the process chart of FIG. (1) As shown in FIG. 1A, an insulating film 2 is formed on a low-concentration substrate 1. (2) As shown in FIG. 1B, a polycrystalline silicon film 3 is formed on the insulating film 2. The present invention is different from the conventional example,
At this stage, high-concentration phosphorus is not diffused into the polycrystalline silicon film 3. (3) A resist 4 is formed on the polycrystalline silicon film 3 and the resist 4 is patterned. As shown in FIG. 1C, the polycrystalline silicon film 3 is etched using the patterned resist 4 as a mask to form a gate electrode 20. At this time, the gate electrode 20 does not have conductivity because phosphorus has not been diffused yet. (4) The resist 4 is removed, and then the resist 6 is formed on the substrate 1. Then, as shown in FIG. 1D, a part of the resist 6 is opened, and a P-type impurity is injected from the opening. The implanted impurities are shown by the dotted line in the figure. (5) As shown in FIG. 1E, a very deep P-type layer 7 is formed by thermal diffusion treatment at high temperature for a long time. At this time,
The P-type layer 7 extends below the gate electrode 20. (6) A resist 8 is formed on the substrate 1. And FIG.
As shown in (f), a part of the resist 8 is opened, and N-type impurities are injected from the opening. The implanted impurities are shown by the dotted line in the figure. (7) After removing the resist 8, a low temperature oxide layer 21 to which phosphorus is added in an appropriate amount is formed as shown in FIG. Here, the appropriate amount is the amount of phosphorus added in a high concentration to the extent that phosphorus is not diffused into silicon in the annealing treatment performed after this step. As a result, the gate electrode 20 has conductivity. The point different from the conventional example is that high-concentration phosphorus is diffused into the polycrystalline silicon film 3 at this stage. (8) Annealing treatment (activation) as shown in FIG.
Then, N-type layers 9 and 10 are formed. (8) As shown in FIG. 1I, the low temperature oxide layer 21 is etched to form an electrode lead-out portion 22. (9) Metal electrodes 13 to 15 are formed as shown in FIG. The P-type layer 7, the N-type layer 9 and the N-type layer 10 respectively form a gate, a source and a drain of the MOS FET. The metal electrodes 13, 14 and 15 are connected to the source, the gate and the drain, respectively. A MOS FET is manufactured through the above steps.

In the embodiment, the case where the DMOS is manufactured has been described, but the manufactured semiconductor integrated circuit is the DMO.
The semiconductor integrated circuit is not limited to S, and may be any semiconductor integrated circuit manufactured through a process of forming a very deep diffusion layer by a thermal diffusion process at high temperature for a long time.

[0010]

According to the present invention, the gate electrode of the polycrystalline silicon film having no conductivity is formed for the time being,
After performing a thermal diffusion process to form a deep diffusion layer,
Impurities are diffused into the polycrystalline silicon film to make the gate electrode conductive. Therefore, the impurities doped in the polycrystalline silicon film are not precipitated at the crystal grain boundaries in the thermal diffusion process for forming the deep diffusion layer. As a result, it is possible to prevent an increase in leakage current of the MOS FET and a decrease in breakdown voltage. The MOS FET finally manufactured by the present invention is a MOS FET manufactured by the conventional method.
It has the same structure as the FET. From the above, according to the present invention, it is possible to prevent an increase in leakage current and a decrease in breakdown voltage of the MOS FET without changing the structure of the finally formed MOS FET.

[Brief description of drawings]

FIG. 1 is a process chart showing an embodiment of a method according to the present invention.

FIG. 2 is a process drawing showing a conventional DMOS manufacturing method.

[Explanation of symbols]

 1 substrate 3 polycrystalline silicon film 7 P-type layer 20 gate electrode

Claims (1)

[Claims] 1. A first step of diffusing impurities in a polycrystalline silicon film to form a conductive gate electrode, and a second step of implanting impurities into a substrate and performing a thermal diffusion process to form a diffusion layer. And at least the steps of
A method of manufacturing a semiconductor integrated circuit for forming a SFET, wherein the first step comes after the second step.