JPH08203896A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

Info

Publication number
JPH08203896A
JPH08203896A JP1096895A JP1096895A JPH08203896A JP H08203896 A JPH08203896 A JP H08203896A JP 1096895 A JP1096895 A JP 1096895A JP 1096895 A JP1096895 A JP 1096895A JP H08203896 A JPH08203896 A JP H08203896A
Authority
JP
Japan
Prior art keywords
film
based alloy
wafer
temperature
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1096895A
Other languages
Japanese (ja)
Inventor
Kazuyuki Sakata
和之 坂田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1096895A priority Critical patent/JPH08203896A/en
Publication of JPH08203896A publication Critical patent/JPH08203896A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enhance the planarization on the surface of a wafer while stabilizing the resistance of a contact hole at a low value by filling the contact hole easily with a second metallization. CONSTITUTION: A first Al based alloy film 2 and an interlayer insulation film 4 are deposited sequentially on a semiconductor substrate, i.e., an interlayer insulation film 1, by a well known method. A contact hole 5 is then made through the interlayer insulation film 4 to expose a first Al based alloy film 2 on the bottom of the opening. Subsequently, the wafer is exposed to high temperature (25O deg.C) in a vacuum system in order to discharge gas from the interlayer insulation film 4 (a). The wafer is then cooled in the vacuum system (b). The cooling temperature is set at 50 deg.C or below. Finally, a nitride 7, a high melting point metal 6 and a second metal, i.e., a second A1 based alloy 3, are deposited sequentially in the contact hole 5 and exposed to high temperature (450 deg.C or above) thus filling the contact hole 5 with the second A1 based alloy 3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置の製造方
法に関し、特に、金属配線膜の形成技術に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for forming a metal wiring film.

【0002】[0002]

【従来の技術】近年、半導体装置の高集積化、高機能化
により、パターンの微細化が進み、それに伴い金属配線
膜を形成する際の接続孔での微小化及びアスペクト比の
増大化も進んでいる。図4は従来の半導体装置の構造を
示す断面図である。図4において、1は半導体基板とし
ての層間絶縁膜、2は第1の金属配線膜としての第1の
Al系合金膜、3は第2の金属配線膜としての第2のA
l系合金膜、4は第1のAl系合金膜2と第2のAl系
合金膜3を分離する層間絶縁膜、5は層間絶縁膜4に開
口された接続孔、6は第2のAl系合金膜3の下地膜で
ある高融点金属膜、7は第2のAl系合金膜3と高融点
金属膜6との間にある下地膜である窒化膜である。
2. Description of the Related Art In recent years, due to higher integration and higher functionality of semiconductor devices, miniaturization of patterns has progressed, and accordingly, miniaturization of connection holes and increase of aspect ratio when forming metal wiring films have also progressed. I'm out. FIG. 4 is a sectional view showing the structure of a conventional semiconductor device. In FIG. 4, 1 is an interlayer insulating film as a semiconductor substrate, 2 is a first Al-based alloy film as a first metal wiring film, and 3 is a second A as a second metal wiring film.
1-based alloy film, 4 is an interlayer insulating film for separating the first Al-based alloy film 2 and the second Al-based alloy film 3, 5 is a connection hole opened in the interlayer insulating film 4, and 6 is a second Al A refractory metal film that is a base film of the system alloy film 3, and a nitride film 7 that is a base film between the second Al-based alloy film 3 and the refractory metal film 6.

【0003】このような構造を有する半導体装置の製造
方法について説明する。まず、層間絶縁膜1上に第1の
Al系合金膜2及び層間絶縁膜4を順次成膜した後、該
層間絶縁膜4に接続孔5を開口し、第1のAl系合金膜
2の一部を露出させる。この後、真空装置により層間絶
縁膜4からのガス出しを行うためにウエハを高温(25
0℃以上)に晒す。その後、高融点金属膜6、窒化膜
7、及び第2のAl系合金膜3を順次成膜し、ウエハを
高温(450℃以上)に晒すことで、接続孔5に第2の
Al系合金膜3を埋め込む。尚、これらの処理は真空装
置内で連続処理し、その後、所定処理を施しパターンを
形成する。
A method of manufacturing a semiconductor device having such a structure will be described. First, a first Al-based alloy film 2 and an interlayer insulating film 4 are sequentially formed on the interlayer insulating film 1, and then a connection hole 5 is opened in the interlayer insulating film 4 to form the first Al-based alloy film 2. Expose part. After that, the wafer is heated to a high temperature (25
Exposed to 0 ° C or higher). After that, the refractory metal film 6, the nitride film 7, and the second Al-based alloy film 3 are sequentially formed, and the wafer is exposed to a high temperature (450 ° C. or higher) to form the second Al-based alloy in the connection hole 5. Embed the membrane 3. In addition, these processes are continuously processed in a vacuum apparatus, and then a predetermined process is performed to form a pattern.

【0004】[0004]

【発明が解決しようとする課題】上述したように、従来
の半導体装置の製造方法は、第2のAl系合金膜3の成
膜後、高温(450℃以上)に晒し、接続孔5を埋め込
むリフロー技術を用いているが、この従来技術では、接
続孔5への第2のAl系合金膜3の埋め込みにバラツキ
が生じ、ウエハ面上での平坦化も悪く、また、接続孔5
での抵抗値も不安定で高抵抗であり信頼性が不十分とい
う問題があり、改善が望まれている。
As described above, according to the conventional method of manufacturing a semiconductor device, after the second Al-based alloy film 3 is formed, it is exposed to a high temperature (450 ° C. or higher) to fill the connection hole 5. Although the reflow technique is used, in this conventional technique, there is variation in the filling of the second Al-based alloy film 3 in the connection hole 5, the flattening on the wafer surface is poor, and the connection hole 5 is used.
There is a problem that the resistance value is unstable and the resistance value is high and the reliability is insufficient. Therefore, improvement is desired.

【0005】すなわち、層間絶縁膜4に接続孔5を開口
し、その後、第2のAl系合金膜3を成膜する際、真空
装置により層間絶縁膜4からのガス出しのためウエハを
高温(250℃以上)に晒すが、このウエハでの温度が
第2のAl系合金膜3の形成時より高温であると、層間
絶縁膜4からの放出ガスと第2のAl系合金膜3が反応
し、リフローを阻害する酸化物や窒化物などの形成や第
2のAl系合金膜3のグレイン成長によるリフローの阻
害が生じることになる。
That is, when the connection hole 5 is opened in the interlayer insulating film 4 and then the second Al-based alloy film 3 is formed, a high temperature ( However, if the temperature of this wafer is higher than that at the time of forming the second Al-based alloy film 3, the gas released from the interlayer insulating film 4 reacts with the second Al-based alloy film 3. However, the formation of an oxide or a nitride that inhibits the reflow and the inhibition of the reflow due to the grain growth of the second Al-based alloy film 3 occur.

【0006】この発明は上述した従来例に係る問題点を
解消するためになされたもので、半導体デバイスの第2
の金属配線膜を接続孔に容易に埋め込み、また、そのと
きのウエハ面上の平坦性を向上でき、さらに、第1の金
属配線膜と第2の金属配線膜との接続孔での抵抗値を安
定で低抵抗なものとすることができる半導体装置の製造
方法を得ることを目的とする。
The present invention has been made in order to solve the above-mentioned problems associated with the conventional example.
Of the metal wiring film can be easily embedded in the connection hole, the flatness on the wafer surface at that time can be improved, and the resistance value in the connection hole between the first metal wiring film and the second metal wiring film can be further improved. It is an object of the present invention to obtain a method for manufacturing a semiconductor device, which is stable and has low resistance.

【0007】[0007]

【課題を解決するための手段】この発明に係る半導体装
置の製造方法は、半導体基板上に第1の金属配線膜及び
層間絶縁膜を順次成膜する第1の工程と、上記層間絶縁
膜に接続孔を開口させてその開口部の底部に上記第1の
金属配線膜を露出させる第2の工程と、この第2の工程
を経たウエハを真空装置内で高温に晒し上記層間絶縁膜
からのガス放出を行う第3の工程と、上記真空装置内で
上記第3の工程を経たウエハを冷却する第4の工程と、
上記真空装置内で上記接続孔に高融点金属膜と窒化膜及
び第2の金属膜を順次成膜し高温に晒す第5の工程とを
有するものである。
A method of manufacturing a semiconductor device according to the present invention comprises a first step of sequentially forming a first metal wiring film and an interlayer insulating film on a semiconductor substrate, and a step of forming the interlayer insulating film. A second step of opening the connection hole to expose the first metal wiring film at the bottom of the opening, and exposing the wafer that has undergone the second step to a high temperature in a vacuum apparatus to remove the first insulating film from the interlayer insulating film. A third step of releasing gas, and a fourth step of cooling the wafer that has undergone the third step in the vacuum apparatus,
The fifth step comprises sequentially forming a refractory metal film, a nitride film, and a second metal film in the connection hole in the vacuum device and exposing them to a high temperature.

【0008】また、上記第5の工程で上記高融点金属膜
と上記窒化膜の成膜を省略し第2の金属配線膜のみ成膜
することを特徴とするものである。
In the fifth step, the formation of the refractory metal film and the nitride film is omitted and only the second metal wiring film is formed.

【0009】さらに、上記第3の工程での温度を250
℃以上とすると共に上記第5の工程での温度を上記第3
の工程での温度より高い450℃以上とするのに対し、
上記第4の工程での温度を50℃以下とすることを特徴
とするものである。
Further, the temperature in the third step is set to 250.
℃ or above and the temperature in the fifth step above the third
In contrast to the temperature of 450 ° C or higher, which is higher than the temperature in the process of
The temperature in the fourth step is set to 50 ° C. or lower.

【0010】[0010]

【作用】この発明に係る半導体装置の製造方法において
は、第1の工程で半導体基板上に第1の金属配線膜及び
層間絶縁膜を順次成膜した後、第2の工程で上記層間絶
縁膜に接続孔を開口させてその開口部の底部に上記第1
の金属配線膜を露出させ、第3の工程でそのウエハを真
空装置内で高温に晒し上記層間絶縁膜からのガス放出を
行い、その後、第4の工程で上記真空装置内で上記ウエ
ハを冷却し、第5の工程で上記接続孔に高融点金属膜と
窒化膜及び第2の金属膜を順次成膜し高温に晒すように
して、第2の金属配線膜を形成する際、層間絶縁膜から
のガス出し後充分冷却を行うことにより、リフロー時の
接続孔への第2の金属配線膜の埋め込み性の向上及びウ
エハの平坦化向上が達成される。
In the method of manufacturing a semiconductor device according to the present invention, the first metal wiring film and the interlayer insulating film are sequentially formed on the semiconductor substrate in the first step, and then the interlayer insulating film is formed in the second step. The connection hole is opened at the bottom of the opening and the first
Of the metal wiring film is exposed, and in the third step, the wafer is exposed to high temperature in a vacuum device to release gas from the interlayer insulating film, and then in the fourth step, the wafer is cooled in the vacuum device. When the second metal wiring film is formed by sequentially forming the refractory metal film, the nitride film, and the second metal film in the connection hole in the fifth step and exposing them to a high temperature, an interlayer insulating film is formed. After the gas is discharged from the substrate, it is sufficiently cooled to improve the embedding property of the second metal wiring film in the connection hole during reflow and the flatness of the wafer.

【0011】また、上記第5の工程で上記高融点金属膜
と上記窒化膜の成膜を省略し第2の金属配線膜のみ成膜
するようにすることにより、第2の金属配線膜がリフロ
ー時に反応することを回避し、接続孔と第1の金属配線
膜の界面での抵抗値が低く安定したものとする。
Further, the second metal wiring film is reflowed by omitting the formation of the refractory metal film and the nitride film and forming only the second metal wiring film in the fifth step. The reaction is sometimes avoided, and the resistance value at the interface between the connection hole and the first metal wiring film is low and stable.

【0012】さらに、上記第3の工程での温度を250
℃以上とすると共に上記第5の工程での温度を上記第3
の工程での温度より高い450℃以上とするのに対し、
上記第4の工程での温度を50℃以下とすることによ
り、層間絶縁膜からの放出ガスと第2の金属配線膜とが
反応し、リフローを阻害する酸化物や窒化物などの形成
及び第2の金属配線膜のグレイン成長によってリフロー
が阻害されるのを確実に防止する。
Further, the temperature in the third step is set to 250.
℃ or above and the temperature in the fifth step above the third
In contrast to the temperature of 450 ° C or higher, which is higher than the temperature in the process of
By setting the temperature in the fourth step to 50 ° C. or lower, the gas released from the interlayer insulating film reacts with the second metal wiring film to form an oxide or a nitride that inhibits reflow, and It surely prevents the reflow from being hindered by the grain growth of the second metal wiring film.

【0013】[0013]

【実施例】【Example】

実施例1.以下、この発明を図示実施例に基づいて説明
する。まず、この発明の実施例1に係る半導体装置の断
面構造図としては、図4に示す従来例と同様なものであ
るが、その製造方法が異なる。すなわち、図1は本実施
例1に係る半導体装置の製造方法を説明するための工程
図で、主に真空装置内処理時のウエハに晒す温度遷移を
説明するものである。以下、図1に示す工程図を参照し
て、本実施例1に係る半導体装置の製造方法について説
明する。
Example 1. Hereinafter, the present invention will be described based on illustrated embodiments. First, a cross-sectional structure diagram of the semiconductor device according to the first embodiment of the present invention is similar to the conventional example shown in FIG. 4, but the manufacturing method is different. That is, FIG. 1 is a process diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment, and mainly illustrates the temperature transition exposed to the wafer during processing in the vacuum apparatus. Hereinafter, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the process chart shown in FIG.

【0014】まず、従来公知の方法で、半導体基板とし
ての層間絶縁膜1上に第1の金属配線膜としての第1の
Al系合金膜2及び層間絶縁膜4を順次成膜する第1の
工程と上記層間絶縁膜4に接続孔5を開口させてその開
口部の底部に上記第1のAl系合金膜2を露出させる第
2の工程とを経た後、第3の工程でそのウエハを真空装
置内で高温(250℃)に晒し上記層間絶縁膜4からの
ガス放出を行う(図1(a)参照)。このとき、このウ
エハでの温度が後述する第2のAl系合金膜3の形成時
より高温であると、層間絶縁膜4からの放出ガスと第2
のAl系合金膜3が反応し、リフローを阻害する酸化物
や窒化物などの形成や第2のAl系合金膜3のグレイン
成長によるリフローの阻害が生じるので、上記層間絶縁
膜4からのガス放出を行う温度は第2のAl系合金膜3
の形成時より低温とする。
First, a first Al-based alloy film 2 and an interlayer insulating film 4 as a first metal wiring film are sequentially formed on an interlayer insulating film 1 as a semiconductor substrate by a conventionally known method. After the step and the second step of opening the connection hole 5 in the interlayer insulating film 4 and exposing the first Al-based alloy film 2 at the bottom of the opening, the wafer is processed in the third step. Gas is released from the interlayer insulating film 4 by exposing it to a high temperature (250 ° C.) in a vacuum device (see FIG. 1A). At this time, if the temperature of this wafer is higher than that at the time of forming the second Al-based alloy film 3 described later, the gas emitted from the interlayer insulating film 4 and the second
The Al-based alloy film 3 reacts to form an oxide or a nitride that inhibits the reflow, and the grain growth of the second Al-based alloy film 3 inhibits the reflow. The temperature for releasing is the second Al-based alloy film 3
The temperature is lower than that during formation of.

【0015】その後、第4の工程で真空装置内で上記ウ
エハを冷却する(図1(b)参照)。このとき、上述し
たように、真空装置により層間絶縁膜4からのガス出し
のためウエハを高温(250℃以上)に晒すが、このウ
エハでの温度が第2のAl系合金膜3の形成時より高温
のときは、リフローを阻害する酸化物や窒化物などの形
成や第2のAl系合金膜3のグレイン成長によるリフロ
ーの阻害が生じるので、十分に冷却する必要があり、そ
の冷却温度を50℃以下とする。
Then, in a fourth step, the wafer is cooled in a vacuum device (see FIG. 1 (b)). At this time, as described above, the wafer is exposed to a high temperature (250 ° C. or higher) to discharge gas from the interlayer insulating film 4 by the vacuum device. However, the temperature of this wafer is high when the second Al-based alloy film 3 is formed. When the temperature is higher, the formation of oxides or nitrides that inhibit reflow and the inhibition of reflow due to grain growth of the second Al-based alloy film 3 occur. Therefore, it is necessary to sufficiently cool the cooling temperature. It shall be 50 ° C or lower.

【0016】次に、第5の工程で上記接続孔5に窒化膜
7と高融点金属膜6及び第2の金属膜としての第2のA
l系合金膜3を順次成膜し高温(450℃以上)に晒す
ようにして接続孔5へ第2のAl系合金膜3を埋め込む
(図1(c)参照)。尚、ウエハを充分冷却させた後、
第2のAl系合金膜3を成膜し、その後、ウエハを高温
(450℃以上)に晒し接続孔5へ第2のAl系合金膜
3を埋め込むが、これは真空装置内で連続処理する。そ
の後所定処理を施し、パターンを形成する。
Next, in the fifth step, the nitride film 7, the refractory metal film 6 and the second metal A as a second metal film are formed in the connection hole 5.
The 1-based alloy film 3 is sequentially formed, and the second Al-based alloy film 3 is embedded in the connection hole 5 by exposing it to a high temperature (450 ° C. or higher) (see FIG. 1C). After cooling the wafer sufficiently,
The second Al-based alloy film 3 is formed, and then the wafer is exposed to a high temperature (450 ° C. or higher) to fill the connection hole 5 with the second Al-based alloy film 3, which is continuously processed in a vacuum apparatus. . After that, a predetermined process is performed to form a pattern.

【0017】このようにして、第2のAl系合金膜3を
形成する際、層間絶縁膜からのガス出し後、充分冷却を
行うことにより、リフロー時の接続孔への第2の金属配
線膜の埋め込み性の向上及びウエハの平坦化向上が達成
される。また、層間絶縁膜4からの放出ガスと第2のA
l系合金膜3が反応し、リフローを阻害する酸化物や窒
化物などの形成や第2のAl系合金膜3のグレイン成長
によるリフローの阻害されるのを確実に防止できる。
In this way, when the second Al-based alloy film 3 is formed, the second metal wiring film to the connection hole at the time of reflow is sufficiently cooled after the gas is released from the interlayer insulating film. And the flattening of the wafer are achieved. Further, the gas emitted from the interlayer insulating film 4 and the second A
It is possible to reliably prevent the reaction of the 1-based alloy film 3 from forming an oxide or a nitride that inhibits the reflow and the inhibition of the reflow due to the grain growth of the second Al-based alloy film 3.

【0018】実施例2.次に、図2は高融点金属膜6及
び窒化膜7の成膜を省略した半導体装置の製造方法に係
り、図1に対応する真空装置内処理時のウエハに晒す温
度遷移を説明する工程図であり、また、図3は図2に示
す工程を経て得られる半導体装置の断面構造図である。
Example 2. Next, FIG. 2 relates to a method of manufacturing a semiconductor device in which the formation of the refractory metal film 6 and the nitride film 7 is omitted, and is a process diagram illustrating a temperature transition exposed to a wafer during processing in a vacuum device corresponding to FIG. FIG. 3 is a sectional structural view of a semiconductor device obtained through the steps shown in FIG.

【0019】すなわち、この実施例2では、図4に示す
半導体装置の断面図において、従来技術と同様に、層間
絶縁膜4に接続孔5を開口後、真空装置においてウエハ
を高温(250℃以上)に晒し層間絶縁膜4からのガス
出しを行い(図2(a)参照)、その後、充分ウエハを
冷却(50℃以下)させた後(図2(b)参照)、図3
の断面構造図に示すように、高融点金属膜6及び窒化膜
7の成膜を省略し、第2のAl系合金膜3のみを成膜す
る。そして、第2のAl系合金膜3成膜後ウエハを高温
(450℃以上)に晒し、第2のAl系合金膜3を接続
孔5へ埋め込む(図2(c)参照)。尚、これは真空装
置内で連続処理を行う。この後、所定処理を施しパター
ンを形成する。
That is, in the second embodiment, in the sectional view of the semiconductor device shown in FIG. 4, after the connection hole 5 is opened in the interlayer insulating film 4, the wafer is heated to a high temperature (250 ° C. or higher) in the vacuum device as in the prior art. 2) to remove gas from the interlayer insulating film 4 (see FIG. 2A), and after sufficiently cooling the wafer (50 ° C. or lower) (see FIG. 2B), FIG.
As shown in the cross-sectional structure diagram of 1, the formation of the refractory metal film 6 and the nitride film 7 is omitted, and only the second Al-based alloy film 3 is formed. Then, after the second Al-based alloy film 3 is formed, the wafer is exposed to high temperature (450 ° C. or higher), and the second Al-based alloy film 3 is embedded in the connection hole 5 (see FIG. 2C). Incidentally, this is continuously processed in a vacuum apparatus. Then, a predetermined process is performed to form a pattern.

【0020】このように、高融点金属膜6及び窒化膜7
を省略することで、これらと第2のAl系合金膜3がリ
フロー時に反応することを回避し、接続孔5と第1のA
l系合金膜2の界面での抵抗値が低くなり、安定した低
抵抗なオーミックコンタクトを得ることができる。
Thus, the refractory metal film 6 and the nitride film 7 are
By omitting these, it is possible to avoid reacting these with the second Al-based alloy film 3 at the time of reflow, and to prevent the connection hole 5 and the first A
The resistance value at the interface of the l-based alloy film 2 becomes low, and a stable low resistance ohmic contact can be obtained.

【0021】実施例3.上記実施例1及び2では第2の
Al系合金膜について説明したが、これは多層配線を用
いる場合、第3、第4と高層のAl系合金膜でも良く、
上記実施例と同様の効果を奏するのは勿論である。
Example 3. Although the second Al-based alloy film has been described in the above-mentioned first and second embodiments, when a multilayer wiring is used, the third and fourth and higher-layer Al-based alloy films may be used.
As a matter of course, the same effect as that of the above-mentioned embodiment is obtained.

【0022】[0022]

【発明の効果】以上のように、この発明に係る半導体装
置の製造方法によれば、第1の工程で半導体基板上に第
1の金属配線膜及び層間絶縁膜を順次成膜した後、第2
の工程で上記層間絶縁膜に接続孔を開口させてその開口
部の底部に上記第1の金属配線膜を露出させ、第3の工
程でそのウエハを真空装置内で高温に晒し上記層間絶縁
膜からのガス放出を行い、その後、第4の工程で上記真
空装置内で上記ウエハを冷却し、第5の工程で上記接続
孔に高融点金属膜と窒化膜及び第2の金属膜を順次成膜
し高温に晒すようにして、第2の金属配線膜を形成する
際、層間絶縁膜からのガス出し後充分冷却を行うように
したため、リフロー時の接続孔への第2の金属配線膜の
埋め込み性の向上及びウエハの平坦化向上が達成される
という効果がある。
As described above, according to the method of manufacturing the semiconductor device of the present invention, after the first metal wiring film and the interlayer insulating film are sequentially formed on the semiconductor substrate in the first step, Two
Step, a connection hole is opened in the interlayer insulating film to expose the first metal wiring film at the bottom of the opening, and in the third step, the wafer is exposed to a high temperature in a vacuum apparatus. Gas is discharged from the substrate, then the wafer is cooled in the vacuum device in the fourth step, and a refractory metal film, a nitride film, and a second metal film are sequentially formed in the connection hole in the fifth step. When the second metal wiring film is formed by exposing the film to the film and exposing it to a high temperature, sufficient cooling is performed after gas is released from the interlayer insulating film. There is an effect that the embedding property and the flattening of the wafer are improved.

【0023】また、上記第5の工程で上記高融点金属膜
と上記窒化膜の成膜を省略し第2の金属配線膜のみ成膜
するようにすることにより、第2の金属配線膜がリフロ
ー時に反応することを回避し、接続孔と第1の金属配線
膜の界面での抵抗値が低く安定したものとすることがで
きる。
In the fifth step, the formation of the refractory metal film and the nitride film is omitted and only the second metal wiring film is formed, so that the second metal wiring film is reflowed. It is possible to avoid reacting at times and to make the resistance value at the interface between the connection hole and the first metal wiring film low and stable.

【0024】さらに、上記第3の工程での温度を250
℃以上とすると共に上記第5の工程での温度を上記第3
の工程での温度より高い450℃以上とするのに対し、
上記第4の工程での温度を50℃以下とすることによ
り、層間絶縁膜からの放出ガスと第2の金属配線膜とが
反応し、リフローを阻害する酸化物や窒化物などの形成
及び第2の金属配線膜のグレイン成長によってリフロー
が阻害されるのを確実に防止することができる。
Further, the temperature in the third step is set to 250.
℃ or above and the temperature in the fifth step above the third
In contrast to the temperature of 450 ° C or higher, which is higher than the temperature in the process of
By setting the temperature in the fourth step to 50 ° C. or lower, the gas released from the interlayer insulating film reacts with the second metal wiring film to form an oxide or a nitride that inhibits reflow, and It is possible to reliably prevent the reflow from being hindered by the grain growth of the second metal wiring film.

【図面の簡単な説明】[Brief description of drawings]

【図1】 この発明の実施例1に係る半導体装置の製造
方法を説明するもので、主に真空装置内処理時のウエハ
に晒す温度遷移を説明する工程図である。
FIG. 1 is a process diagram for explaining a method for manufacturing a semiconductor device according to a first embodiment of the present invention, which is a process flow diagram mainly explaining a temperature transition exposed to a wafer during processing in a vacuum device.

【図2】 この発明の実施例2に係る半導体装置の製造
方法を説明するもので、主に真空装置内処理時のウエハ
に晒す温度遷移を説明する工程図である。
FIG. 2 is a process chart for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention, which is a process flow diagram mainly explaining the temperature transition exposed to the wafer during the processing in the vacuum apparatus.

【図3】 この発明の実施例2に係る半導体装置の断面
構造図である。
FIG. 3 is a sectional structural view of a semiconductor device according to a second embodiment of the present invention.

【図4】 従来及びこの発明の実施例1に係る半導体装
置を示す断面構造図である。
FIG. 4 is a sectional structural view showing a semiconductor device according to the related art and Embodiment 1 of the present invention.

【符号の説明】[Explanation of symbols]

1 層間絶縁膜、2 第1のAl系合金膜、3 第2の
Al系合金膜、4 層間絶縁膜、5 接続孔、6 高融
点金属膜、7 窒化膜。
1 interlayer insulating film, 2 1st Al type alloy film, 3 2nd Al type alloy film, 4 interlayer insulating film, 5 connection hole, 6 refractory metal film, 7 nitride film.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に第1の金属配線膜及び層
間絶縁膜を順次成膜する第1の工程と、上記層間絶縁膜
に接続孔を開口させてその開口部の底部に上記第1の金
属配線膜を露出させる第2の工程と、この第2の工程を
経たウエハを真空装置内で高温に晒し上記層間絶縁膜か
らのガス放出を行う第3の工程と、上記真空装置内で上
記第3の工程を経たウエハを冷却する第4の工程と、上
記真空装置内で上記接続孔に高融点金属膜と窒化膜及び
第2の金属膜を順次成膜し高温に晒す第5の工程とを有
する半導体装置の製造方法。
1. A first step of sequentially forming a first metal wiring film and an interlayer insulating film on a semiconductor substrate, and a connecting hole is opened in the interlayer insulating film, and the first hole is formed at the bottom of the opening. Second step of exposing the metal wiring film of the above step, a third step of exposing the wafer that has undergone the second step to a high temperature in a vacuum device to release gas from the interlayer insulating film, and a vacuum step in the vacuum device. A fourth step of cooling the wafer which has undergone the third step, and a fifth step of sequentially forming a refractory metal film, a nitride film and a second metal film in the connection hole in the vacuum device and exposing them to a high temperature. And a method of manufacturing a semiconductor device.
【請求項2】 上記第5の工程で上記高融点金属と上記
窒化膜の成膜を省略し第2の金属配線膜のみ成膜するこ
とを特徴とする請求項1記載の半導体装置の製造方法。
2. The method for manufacturing a semiconductor device according to claim 1, wherein the formation of the refractory metal and the nitride film is omitted in the fifth step, and only the second metal wiring film is formed. .
【請求項3】 上記第3の工程での温度を250℃以上
とすると共に上記第5の工程での温度を上記第3の工程
での温度より高い450℃以上とするのに対し、上記第
4の工程での温度を50℃以下とすることを特徴とする
請求項1または2記載の半導体装置の製造方法。
3. The temperature in the third step is set to 250 ° C. or higher, and the temperature in the fifth step is set to 450 ° C. or higher, which is higher than the temperature in the third step. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature in step 4 is set to 50 [deg.] C. or lower.
JP1096895A 1995-01-26 1995-01-26 Fabrication of semiconductor device Pending JPH08203896A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1096895A JPH08203896A (en) 1995-01-26 1995-01-26 Fabrication of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1096895A JPH08203896A (en) 1995-01-26 1995-01-26 Fabrication of semiconductor device

Publications (1)

Publication Number Publication Date
JPH08203896A true JPH08203896A (en) 1996-08-09

Family

ID=11764974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1096895A Pending JPH08203896A (en) 1995-01-26 1995-01-26 Fabrication of semiconductor device

Country Status (1)

Country Link
JP (1) JPH08203896A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107182A (en) * 1997-10-02 2000-08-22 Seiko Epson Corporation Semiconductor device and method of fabricating the same
KR20010033664A (en) * 1997-12-31 2001-04-25 피터 엔. 데트킨 A single step electroplating process for interconnect via fill and metal line patterning
US6429493B1 (en) 1998-10-20 2002-08-06 Seiko Epson Corporation Semiconductor device and method for manufacturing semiconductor device
KR100496716B1 (en) * 1997-08-29 2005-09-30 세이코 엡슨 가부시키가이샤 Semiconductor device and its manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100496716B1 (en) * 1997-08-29 2005-09-30 세이코 엡슨 가부시키가이샤 Semiconductor device and its manufacturing method
US6107182A (en) * 1997-10-02 2000-08-22 Seiko Epson Corporation Semiconductor device and method of fabricating the same
US6614119B1 (en) 1997-10-02 2003-09-02 Seiko Epson Corporation Semiconductor device and method of fabricating the same
KR20010033664A (en) * 1997-12-31 2001-04-25 피터 엔. 데트킨 A single step electroplating process for interconnect via fill and metal line patterning
US6429493B1 (en) 1998-10-20 2002-08-06 Seiko Epson Corporation Semiconductor device and method for manufacturing semiconductor device
US6511910B2 (en) 1998-10-20 2003-01-28 Seiko Epson Corporation Method for manufacturing semiconductor devices

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