KR100705950B1 - Method of forming a metal line in semiconductor device - Google Patents

Method of forming a metal line in semiconductor device Download PDF

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KR100705950B1
KR100705950B1 KR1020010082470A KR20010082470A KR100705950B1 KR 100705950 B1 KR100705950 B1 KR 100705950B1 KR 1020010082470 A KR1020010082470 A KR 1020010082470A KR 20010082470 A KR20010082470 A KR 20010082470A KR 100705950 B1 KR100705950 B1 KR 100705950B1
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forming
copper metal
semiconductor device
metal layer
heat treatment
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KR1020010082470A
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Korean (ko)
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KR20030052485A (en
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김헌도
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Abstract

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 비아홀 및 트랜치를 매립하도록 구리 금속층을 증착한 후 고압에서 열처리 공정을 실시하여 비아홀 내부의 구리 금속층의 결정립을 조대화하여 비아홀 내부에서의 구리 금속의 이탈을 억제함으로써 구리 금속층 증착시 형성된 동공과 같은 보이드를 동시에 제거할 수 있는 반도체 소자의 금속 배선 형성 방법을 제시한다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and includes depositing a copper metal layer so as to fill a via hole and a trench, and then performing a heat treatment at a high pressure to coarsen crystal grains of the copper metal layer inside the via hole. The present invention provides a method for forming metal wirings in a semiconductor device capable of simultaneously removing voids such as pores formed during deposition of a copper metal layer by suppressing the separation of the metal.

반도체 소자, 듀얼 다마신, 구리 금속층, 고압 열처리 Semiconductor device, dual damascene, copper metal layer, high pressure heat treatment

Description

반도체 소자의 금속 배선 형성 방법{Method of forming a metal line in semiconductor device} Method of forming a metal line in semiconductor device             

도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 도시한 반도체 소자의 단면도.
1A to 1E are cross-sectional views of a semiconductor device for explaining a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명>       <Explanation of symbols for the main parts of the drawings>

10 : 반도체 기판 12 : 하부 금속층   10 semiconductor substrate 12 lower metal layer

14 : 제 1 확산 방지막 16 : 제 1 층간 절연막  14 first diffusion barrier film 16 first interlayer insulating film

18 : 식각 베리어층 20 : 제 2 층간 절연막  18: etching barrier layer 20: second interlayer insulating film

22 : 캡핑층 24 : 제 2 확산 방지막  22 capping layer 24 second diffusion barrier film

26 : 구리 금속층 28 : 구리 금속 배선
26: copper metal layer 28: copper metal wiring

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 듀얼 다마신(Dual damascene) 공정을 이용한 구리 금속 배선 형성 방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming copper metal wirings using a dual damascene process.

일반적으로, 구리 금속 배선 형성 공정에서는 CMP(Chemical Mechanical Planarization)를 이용한 평탄화 공정시 연마속도를 일정하게 하고, 구리 금속의 결점(Defect) 등을 최소화하기 위해 평탄화 공정의 전처리 공정으로 열처리 공정을 상압 또는 저압에서 실시하고 있다. 그러나, 이 열처리 공정에 의해 구리 금속의 재결정화가 일어나 조대한 결정립(Coarse grain)이 형성되고, 확산 방지막과 구리 금속 간의 접합력이 한계에 이르러 비아홀 내에서 동공 등과 같은 보이드(Void)가 발생하게 된다. In general, in the copper metal wiring forming process, in order to minimize the defects of the copper metal and to minimize the defects of the copper metal during the planarization process using chemical mechanical planarization (CMP), the heat treatment process is performed at atmospheric pressure or It is carried out at low pressure. However, by the heat treatment process, recrystallization of copper metal occurs, coarse grains are formed, and the bonding strength between the diffusion barrier film and the copper metal reaches a limit, and voids such as pores are generated in the via hole.

이러한, 보이드는 구리 금속층 재결정화시 스트레스가 집중되는 비아홀 하부에서 주로 발생하는데, 구리 금속 재결정화와 금속과 절연막의 열팽창 계수의 차이를 야기시켜 비아홀 불량의 원인이 된다. 또한, 비아홀 불량은 금속 배선의 불량을 야기시켜 구리 금속의 소자 특성에 치명적인 영향을 주고 있으며, 특히 층간 절연막으로 초유전율을 사용하거나, 비아홀의 크기가 작을 경우 이러한 문제가 더욱 심하게 발생하게 된다.
These voids are mainly generated in the lower part of the via hole where stress is concentrated upon recrystallization of the copper metal layer, which causes a difference between the thermal expansion coefficients of the copper metal and the insulating layer and causes the via hole defect. In addition, failure of the via hole causes a defect in the metal wiring, which has a fatal effect on the device characteristics of the copper metal. In particular, when the super dielectric constant is used as the interlayer insulating layer or the size of the via hole is small, the problem occurs more seriously.

따라서, 본 발명은 상기 문제를 해결하기 위해 안출된 것으로, 비아홀 및 트랜치를 매립하도록 구리 금속층을 증착한 후 고압에서 열처리 공정을 실시하여 비 아홀 내부의 구리 금속층의 결정립을 조대화하여 비아홀 내부에서의 구리 금속의 이탈을 억제함으로써 구리 금속층 증착시 형성된 동공과 같은 보이드를 동시에 제거할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다
Accordingly, the present invention has been made to solve the above problems, by depositing a copper metal layer to fill the via holes and trenches, and performing a heat treatment at high pressure to coarse the grains of the copper metal layer inside the via hole to It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device capable of simultaneously removing voids such as pores formed during deposition of a copper metal layer by suppressing detachment of the copper metal.

상술한 목적을 달성하기 위해 본 발명은 하부 도전층 등의 소정의 구조가 형성된 반도체 기판 상부에 층간 절연막을 형성하는 단계; 듀얼 다마신 공정을 실시하여 상기 하부 도전층의 소정 부위가 노출되도록 비아 및 트랜치를 형성는 단계; 상기 비아 및 트랜치를 포함한 전체 구조 상부에 상부 도전층을 증착한 후 고압에서 열처리 공정을 실시하는 단계; 및 상기 상부 도전층을 평탄화하여 상기 비아 및 트랜치를 매립하도록 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.
In order to achieve the above object, the present invention comprises the steps of forming an interlayer insulating film on the semiconductor substrate formed with a predetermined structure, such as a lower conductive layer; Performing a dual damascene process to form vias and trenches to expose predetermined portions of the lower conductive layer; Depositing an upper conductive layer on the entire structure including the vias and trenches, and then performing a heat treatment at a high pressure; And forming metal wirings to planarize the upper conductive layer to fill the vias and trenches.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 구리 금속 배선 형성 방법을 설명하기 위해 도시한 반도체 소자의 단면도이다. 1A to 1C are cross-sectional views of a semiconductor device for explaining a method of forming a copper metal wire in a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 소정의 구조가 형성된 반도체 기판(10) 상에 하부 금속층(12)을 형성한 후 그 상부에 제 1 확산 방지막(14)을 형성한다. 이어서, 제 1 확산 방지막(14) 상에 제 1 층간 절연막(16), 식각 베리어층(18), 제 2 층간 절연막(20) 및 캡핑층(22)을 순차적으로 형성한다. 여기서, 제 1 및 제 2 층간 절연막(16 및 20)은 저유전 물질로 이루어진다. Referring to FIG. 1A, after forming a lower metal layer 12 on a semiconductor substrate 10 having a predetermined structure, a first diffusion barrier 14 is formed thereon. Subsequently, the first interlayer insulating layer 16, the etch barrier layer 18, the second interlayer insulating layer 20, and the capping layer 22 are sequentially formed on the first diffusion barrier layer 14. Here, the first and second interlayer insulating films 16 and 20 are made of a low dielectric material.

이어서, 하부 금속층(12)의 소정 부위가 노출되도록 듀얼 다마신 공정을 실시하여 비아홀 및 트랜치(도시하지 않음)를 형성한 후 비아 및 트랜치를 통해 노출되는 하부 금속층(12)의 상부 표면에 형성된 자연 산화막을 제거한다. 이어서, 비아홀 및 트랜치 내부면을 포함한 전체 구조 상부에 금속층으로 제 2 확산 방지막(24)을 형성한 후 전기 화학적 증착 공정을 실시하여 비아홀 및 트랜치를 매립하도록 전체 구조 상부에 구리 금속층(26)을 증착한다. 이때, 구리 금속층(26)의 결정립계는 도시된 'A'와 같이 미세 결정립으로 이루어진다.Subsequently, a dual damascene process is performed to expose a predetermined portion of the lower metal layer 12 to form via holes and trenches (not shown), and then formed on the upper surface of the lower metal layer 12 exposed through the vias and trenches. Remove the oxide film. Subsequently, after the second diffusion barrier layer 24 is formed of a metal layer on the entire structure including the via hole and the inner surface of the trench, an electrochemical deposition process is performed to deposit a copper metal layer 26 on the entire structure to fill the via hole and the trench. do. At this time, the grain boundary of the copper metal layer 26 is made of fine grains as shown in 'A'.

도 1b를 참조하면, 구리 금속층(26)에 고압에서 열처리 공정을 실시하여 결정립계가 도시된 'B'와 같이 조대화된 결정립을 갖는 구리 금속층(26)을 형성한다. 이때, 열처리 공정은 환원성 분위기에서 1 내지 1000 기압에서 100 내지 450℃의 온도로 30분 내지 3시간 동안 실시하되, 비아홀 및 트랜치를 매립하도록 구리 금속층(26)을 형성한 후 12시간 이내에 실시한다. Referring to FIG. 1B, the copper metal layer 26 is subjected to a heat treatment at high pressure to form a copper metal layer 26 having coarse grains, such as 'B', which shows grain boundaries. At this time, the heat treatment process is carried out for 30 minutes to 3 hours at a temperature of 100 to 450 ℃ at 1 to 1000 atm in a reducing atmosphere, but after 12 hours to form a copper metal layer 26 to fill the via holes and trenches.

도 1c를 참조하면, 구리 금속층(26)에 CMP를 이용한 평탄화 공정을 실시하여 비아 및 트랜치가 매립되도록 구리 금속 배선(28)을 형성한다.
Referring to FIG. 1C, a planarization process using CMP is performed on the copper metal layer 26 to form a copper metal wiring 28 to fill vias and trenches.

본 발명은 비아홀 및 트랜치를 매립하도록 구리 금속층을 증착한 후 고압에 서 열처리 공정을 실시하여 비아홀 내부의 구리 금속층의 결정립을 조대화하여 비아홀 내부에서의 구리 금속의 이탈을 억제함으로써 구리 금속층 증착시 형성된 동공과 같은 보이드를 동시에 제거할 수 있다. 따라서, 반도체 소자의 비아홀 수율 불량을 최소화할 수 있다. The present invention is formed during deposition of a copper metal layer by depositing a copper metal layer to fill a via hole and a trench, and then performing a heat treatment at high pressure to coarse grains of the copper metal layer in the via hole to suppress the removal of the copper metal in the via hole. Voids such as pupils can be removed at the same time. Therefore, poor via hole yield of the semiconductor device can be minimized.

Claims (4)

반도체 기판 상부에 하부 도전층을 형성하는 단계;Forming a lower conductive layer on the semiconductor substrate; 상기 하부 도전층 상부에 층간 절연막을 형성하는 단계;Forming an interlayer insulating layer on the lower conductive layer; 듀얼 다마신 공정을 실시하여 상기 하부 도전층의 소정 부위가 노출되도록 비아 및 트랜치를 형성하는 단계;Performing a dual damascene process to form vias and trenches to expose predetermined portions of the lower conductive layer; 상기 비아 및 트랜치를 포함한 전체 구조 상부에 구리를 이용하여 상부 도전층을 증착한 후 고압의 환원성 분위기에서 열처리 공정을 실시하는 단계; 및Depositing an upper conductive layer on the entire structure including the vias and trenches using copper, and then performing a heat treatment process in a high-pressure reducing atmosphere; And 상기 상부 도전층을 평탄화하여 상기 비아 및 트랜치를 매립하도록 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And forming a metal wiring to planarize the upper conductive layer to fill the vias and trenches. 제 1 항에 있어서, The method of claim 1, 상기 열처리 공정은 1 내지 1000 기압에서 100 내지 450℃의 온도로 30분 내지 3시간 동안 실시하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The heat treatment process is a metal wiring forming method of a semiconductor device, characterized in that carried out for 30 minutes to 3 hours at a temperature of 100 to 450 ℃ at 1 to 1000 atm. 제 1 항에 있어서, The method of claim 1, 상기 열처리 공정은 상기 상부 도전층을 증착한 후 12시간 이내에 실시되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the heat treatment step is performed within 12 hours after depositing the upper conductive layer. 삭제delete
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101038491B1 (en) * 2004-04-16 2011-06-01 삼성테크윈 주식회사 lead frame and the method for manufacturing the same
US8551878B2 (en) 2009-07-13 2013-10-08 Samsung Electronics Co., Ltd. Metal interconnection method of semiconductor device
US9496218B2 (en) 2012-07-17 2016-11-15 Samsung Electronics Co., Ltd. Integrated circuit device having through-silicon-via structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10112445A (en) * 1996-10-04 1998-04-28 Toshiba Corp Manufacture of semiconductor device
KR20000035140A (en) * 1998-11-02 2000-06-26 구마모토 마사히로 Method of forming interconnect film

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10112445A (en) * 1996-10-04 1998-04-28 Toshiba Corp Manufacture of semiconductor device
KR20000035140A (en) * 1998-11-02 2000-06-26 구마모토 마사히로 Method of forming interconnect film
KR100610533B1 (en) * 1998-11-02 2006-08-09 가부시키가이샤 고베 세이코쇼 Method of forming interconnect film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101038491B1 (en) * 2004-04-16 2011-06-01 삼성테크윈 주식회사 lead frame and the method for manufacturing the same
US8551878B2 (en) 2009-07-13 2013-10-08 Samsung Electronics Co., Ltd. Metal interconnection method of semiconductor device
US9496218B2 (en) 2012-07-17 2016-11-15 Samsung Electronics Co., Ltd. Integrated circuit device having through-silicon-via structure

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