JPH08162636A - Field-effect element and formation method of its electrode - Google Patents
Field-effect element and formation method of its electrodeInfo
- Publication number
- JPH08162636A JPH08162636A JP6315388A JP31538894A JPH08162636A JP H08162636 A JPH08162636 A JP H08162636A JP 6315388 A JP6315388 A JP 6315388A JP 31538894 A JP31538894 A JP 31538894A JP H08162636 A JPH08162636 A JP H08162636A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- region
- insulating film
- wiring
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 230000005669 field effect Effects 0.000 title claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 238000002955 isolation Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 15
- 239000002184 metal Substances 0.000 abstract description 15
- 150000002739 metals Chemical class 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 239000000126 substance Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001603 reducing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は電界効果素子の構造およ
びその電極を形成する方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a field effect element and a method of forming an electrode thereof.
【０００２】[0002]
【従来の技術】半導体素子の高集積化，高速化を加速し
ながら、素子の性能向上を図るための努力が継続されて
いる。2. Description of the Related Art Efforts for improving the performance of semiconductor devices are being continued while accelerating the higher integration and higher speed of semiconductor devices.
【０００３】シリコン基板を利用したプレーナ（Plana
r）技術は半導体の製造技術とともに急速度に発展して
いる。Planar using a silicon substrate (Plana
r) Technology is rapidly developing along with semiconductor manufacturing technology.
【０００４】また、シリコンＣＭＯＳ（Complementary
Metal Oxide Semiconductor）素子の製造技術は現在
０．３５μｍのゲート線幅をもつ常用のＡＳＩＣライブ
ラリ（Application Specific Integrated Circuit Libr
ary）の開発および０．１８μｍのゲート線幅をもつ１
ＧＤＲＡＭの開発が進行されており、これによる工程技
術の開発が進行されている。０．１８μｍのゲート線幅
をもつ１ＧＤＲＡＭの製造工程の場合、０．１８μｍの
設計寸法（design rule）による工程の余裕度を確保し
なければならない。In addition, silicon CMOS (Complementary
The manufacturing technology of Metal Oxide Semiconductor (IC) devices is currently a common ASIC library (Application Specific Integrated Circuit Libr) having a gate line width of 0.35 μm.
ary) and 1 with a gate line width of 0.18 μm
The development of GDRAM is in progress, and the process technology based on it is also in progress. In the case of a manufacturing process of a 1G DRAM having a gate line width of 0.18 μm, it is necessary to secure a process margin due to a design rule of 0.18 μm.
【０００５】特に、コンタクト工程の場合、０．２μｍ
×０．２μｍ以下のコンタクトホールを形成するために
写真製版の工程および乾式エッチングの工程の開発が必
要であり、これを克服するためには半導体のコンタクト
装備の性能の向上およびこれによる工程の開発を必要と
する。Especially in the case of the contact process, 0.2 μm
Development of photolithography process and dry etching process is required to form contact holes of 0.2 μm or less. In order to overcome this, improvement of performance of semiconductor contact equipment and development of process by it. Need.
【０００６】図８は従来の典型的なＣＭＯＳの構造を図
示している断面図であり、図９は図８のｎ−ＭＯＳＦＥ
Ｔ部分の平面図である。FIG. 8 is a cross-sectional view showing the structure of a conventional typical CMOS, and FIG. 9 is an n-MOSFE of FIG.
It is a top view of a T portion.
【０００７】図面において、参照番号１，７，１１は電
極を示しており、番号２，３，８は絶縁膜を示してお
り、番号４，６，１２，１３は高濃度の領域を、番号
９，１０はウェルを、また番号１４は基板を、それぞれ
示している。In the drawings, reference numerals 1, 7, and 11 represent electrodes, reference numerals 2, 3, and 8 represent insulating films, and reference numerals 4, 6, 12, and 13 represent high-concentration regions. Reference numerals 9 and 10 represent wells, and reference numeral 14 represents a substrate.
【０００８】従来例では、図８および図９に示すよう
に、ケイ素類の電極または金属類（または異種の金属
類）の電極（４），（６），（７），（１１），（１
２），（１３）を配線電極（１）と電気的に連結するた
めに、絶縁膜（２）を形成し、コンタクトホール（５）
を形成した後に、金属物質または導電性の配線物質によ
ってコンタクトホールを詰めなけれならない。In the conventional example, as shown in FIGS. 8 and 9, electrodes of silicons or electrodes of metals (or different kinds of metals) (4), (6), (7), (11), ( 1
Insulating film (2) is formed to electrically connect 2) and (13) to wiring electrode (1), and contact hole (5) is formed.
After forming the contact holes, the contact holes must be filled with a metal material or a conductive wiring material.
【０００９】コンタクトホールを形成するためには、絶
縁膜（２）の表面にフォトレジストパターンを形成した
後、絶縁膜（２）を蝕刻しなければならない。In order to form the contact hole, it is necessary to etch the insulating film (2) after forming a photoresist pattern on the surface of the insulating film (2).
【００１０】このような従来の技術によると、回路の集
積度が増加することにより、コンタクトホールの形成の
ためのフォトレジストパターンの形成の工程およびコン
タクトホールエッチング工程は、工程の余裕度を悪化さ
せ、歩留りの向上の主要な障害要素として作用する。According to such a conventional technique, since the degree of integration of the circuit is increased, the process of forming the photoresist pattern for forming the contact hole and the process of etching the contact hole deteriorate the process margin. Acts as a major impediment to yield improvement.
【００１１】[0011]
【発明が解決しようとする課題及び課題を解決するため
の手段】本発明は、ケイ素類、金属または異種の金属類
の電極間の配線工程において、コンタクトホールの形成
工程を実行せずに、素子の電気的なコンタクトを自動整
列して形成することができる電界効果素子およびその電
極形成方法を提供することを目的とする。DISCLOSURE OF THE INVENTION The present invention provides a device in which a contact hole forming step is not performed in a wiring process between electrodes of silicons, metals or different kinds of metals. It is an object of the present invention to provide a field effect element and an electrode forming method thereof capable of automatically forming electrical contacts of the above.
【００１２】本発明の一つの特徴によると、素子隔離用
の絶縁膜（フィールド酸化膜）と、ゲート電極の領域
と、配線用の電極と電気的にそれぞれ連結されるソース
電極の領域およびドレイン電極の領域とを備えた本発明
の電界効果素子は、前記ゲート電極の領域を取り囲むよ
うに形成され、しかも前記ソース電極の領域の中で前記
ゲート電極の領域と隣接する一部分の上と、前記ドレイ
ン電極の領域の中で前記ゲート電極の領域と隣接する一
部分の上とに形成された絶縁膜を、さらに備えるととも
に、前記配線用の電極のそれぞれが、前記素子隔離用の
絶縁膜の上と、前記絶縁膜によって覆われていない前記
ソース電極の領域および前記ドレイン電極の領域の残り
の表面上と、前記絶縁膜上とに直接的に形成される一
方、それらの相互間は前記素子隔離用の絶縁膜と前記絶
縁膜によってそれぞれ電気的に絶縁される。According to one feature of the present invention, a device isolation insulating film (field oxide film), a gate electrode region, a source electrode region and a drain electrode electrically connected to the wiring electrode, respectively. A field effect element of the present invention, which is formed so as to surround the region of the gate electrode, and further, in the region of the source electrode adjacent to the region of the gate electrode, and the drain. While further comprising an insulating film formed on a portion adjacent to the gate electrode region in the electrode region, each of the wiring electrodes, on the insulating film for element isolation, Directly formed on the remaining surface of the region of the source electrode and the region of the drain electrode not covered by the insulating film and on the insulating film, and between them. It is electrically insulated each insulating film of the serial device for isolating and by the insulating film.
【００１３】本発明の素子は前記ゲート電極の領域に電
気的に連結される他の一つの配線電極を付加的に備える
ことができる。The device of the present invention may additionally include another wiring electrode electrically connected to the region of the gate electrode.
【００１４】本発明の他の特徴によると、本発明の電極
の形成方法は、素子隔離用の絶縁膜と、ゲート電極の領
域と、配線用の電極と電気的にそれぞれ連結されるソー
ス電極の領域および、ドレイン電極の領域が形成された
基板上に絶縁膜を形成する工程と、前記絶縁膜の中で前
記ゲート電極の領域を取り囲む部分のみ残して残りの部
分を除去して、前記素子隔離用の絶縁膜の表面と、前記
ソース電極の領域の表面の一部および、前記ドレイン電
極の領域の表面の一部が露出されるようにする工程と、
配線電極用の物質を塗布しパターニングして配線電極を
形成する工程をと、を包含する。According to another aspect of the present invention, in the method of forming an electrode of the present invention, a device isolation insulating film, a gate electrode region, and a source electrode electrically connected to a wiring electrode are respectively formed. Region and a region where the drain electrode region is formed, a step of forming an insulating film on the substrate, and removing only the portion of the insulating film surrounding the region of the gate electrode and removing the remaining portion to isolate the device. A surface of the insulating film for use, a part of the surface of the region of the source electrode, and a part of the surface of the region of the drain electrode are exposed,
And forming a wiring electrode by applying a material for the wiring electrode and patterning it.
【００１５】本発明の電極の形成方法は、前記ゲート電
極の領域と前記配線電極との間の電気的な連結の必要性
に応じて、前記絶縁膜の除去工程が前記ゲート電極の領
域上の前記絶縁膜の一部を除去してゲート電極の領域の
表面の一部を露出させる工程を付加的に包含することが
できる。In the method of forming an electrode according to the present invention, the step of removing the insulating film is performed on the area of the gate electrode depending on the necessity of electrical connection between the area of the gate electrode and the wiring electrode. A step of removing a part of the insulating film to expose a part of the surface of the region of the gate electrode may be additionally included.
【００１６】本発明の電極の形成方法は、前記絶縁膜の
除去工程と配線電極用の物質塗布工程との間に、前記ソ
ース電極の領域の前記露出された表面上と前記ドレイン
電極の領域の前記露出された表面上にケイ化物を形成す
る工程を付加的に包含することができる。In the method for forming an electrode of the present invention, between the step of removing the insulating film and the step of applying the substance for the wiring electrode, the exposed surface of the source electrode region and the drain electrode region are formed. The step of forming a silicide on the exposed surface may be additionally included.
【００１７】本発明の電極の形成方法における、コンタ
クトの最小長さは前記絶縁膜の厚さによって決定され
る。In the electrode forming method of the present invention, the minimum contact length is determined by the thickness of the insulating film.
【００１８】以上のような、本発明によると、ケイ素類
の電極、金属または異種金属の電極の間の配線工程にお
いてコンタクトホールの形成工程を実行しないで、素子
の電気的なコンタクトを自動整列することができるよう
になる。As described above, according to the present invention, the electrical contact of the device is automatically aligned without performing the step of forming the contact hole in the wiring step between the electrodes of silicon and the electrodes of the metal or the dissimilar metals. Will be able to.
【００１９】[0019]
【実施例】以下、添付の図面を参照して本発明について
詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings.
【００２０】図１は、本発明の望ましい実施例にかかる
ＣＭＯＳ素子の構造を示す断面図であり、図２は図１の
ｎ−ＭＯＳＦＥＴ部分を示す平面図である。FIG. 1 is a sectional view showing a structure of a CMOS device according to a preferred embodiment of the present invention, and FIG. 2 is a plan view showing an n-MOSFET portion of FIG.
【００２１】図１および図２において、参照番号１５，
１９，２０，２６は電極を示しており、番号１７，２１
は絶縁膜を示しており、番号１６，１８，２４は高濃度
の領域を、番号２２，２３はウェルを、それぞれ示して
いる。In FIGS. 1 and 2, reference numeral 15,
Reference numerals 19, 20, and 26 denote electrodes, and numbers 17, 21
Indicates an insulating film, numbers 16, 18, and 24 indicate high-concentration regions, and numbers 22 and 23 indicate wells, respectively.
【００２２】図１および図２を参照して、ケイ素類また
は金属類の電極（２０），（２６）の電気的な絶縁のた
めの部分のみに絶縁膜（２１），（２５）が形成されて
おり、配線電極（１５），（１９）等はコンタクトホー
ルを介さず、ケイ素類の電極または金属類（異種の金属
類）の電極（１６），（１８），（２４）等とそれぞれ
直接的に接続されている。Referring to FIGS. 1 and 2, insulating films (21) and (25) are formed only on portions for electrically insulating the electrodes (20) and (26) of silicon or metal. The wiring electrodes (15), (19), etc. do not go through contact holes but directly with the electrodes of silicon or the electrodes (16), (18), (24) of metals (different metals), respectively. Connected to each other.
【００２３】したがって、絶縁膜（２１），（２５）は
配線電極（１５），（１９）とゲート電極（２０），
（２６）をそれぞれ電気的に絶縁させる。Therefore, the insulating films (21) and (25) are connected to the wiring electrodes (15) and (19) and the gate electrode (20),
(26) are electrically insulated from each other.
【００２４】これをもって、コンタクトホールの写真製
版工程およびエッチング工程からなるコンタクトホール
の形成工程を実行せずに、電極がケイ素類の電極，金属
類（異種の金属類）の電極（１６），（１８），（２
４）等と電気的に連結される。With this, without performing the contact hole forming process including the photolithography process and the etching process of the contact hole, the electrodes are electrodes of silicons and electrodes (16) of metal (different metals), ( 18), (2
4) etc. are electrically connected.
【００２５】図３は、従来のＣＭＯＳ素子と本発明にか
かるＣＭＯＳ素子のコンタクト抵抗の計算結果をそれぞ
れ示す図であり、設計の寸法（コンタクトの最小の長
さ；Ｌ）に対する、配線の電極がアルミニウムで形成さ
れている場合のコンタクト抵抗を示している。FIG. 3 is a diagram showing the calculation results of the contact resistances of the conventional CMOS device and the CMOS device according to the present invention, respectively, showing that the wiring electrodes correspond to the design size (minimum contact length; The contact resistance when formed of aluminum is shown.
【００２６】既存のコンタクトホール構造の場合には、
よく知られているように、コンタクトの最小長さＬの減
少にともなって、コンタクト抵抗が急激に増加する傾向
が見られる。In the case of the existing contact hole structure,
As is well known, there is a tendency for the contact resistance to rapidly increase as the minimum contact length L decreases.
【００２７】反面、本発明による構造の場合には、既存
のコンタクトホールの構造と比較するとき、最小長さＬ
が０．５μｍ以上のときのコンタクト抵抗は既存の構造
の場合のコンタクト抵抗の約１／２であり、最小長さＬ
が０．０８μｍのときにはコンタクト抵抗は既存の構造
の場合の約１／５となり、コンタクト抵抗の減少効果は
約４００％となることがわかる。On the other hand, in the case of the structure according to the present invention, when compared with the structure of the existing contact hole, the minimum length L
Is 0.5 μm or more, the contact resistance is about 1/2 of the contact resistance of the existing structure, and the minimum length L
It can be seen that when is 0.08 μm, the contact resistance is about ⅕ of the existing structure, and the contact resistance reducing effect is about 400%.
【００２８】このように、本発明によると、そのコンタ
クト抵抗の改善率が大幅に増加する。すなわち、コンタ
クトの最小長さＬの減少によってコンタクト抵抗が増大
するが、本発明では、既存の構造に比べて増大の割合が
小さく、コンタクト抵抗の増大が改善されている。As described above, according to the present invention, the improvement rate of the contact resistance is significantly increased. That is, although the contact resistance increases as the minimum length L of the contact decreases, the increase rate of the contact resistance is improved in the present invention as compared with the existing structure.
【００２９】図４ないし図７は、本発明の実施例により
ＣＭＯＳ素子の配線の電極を形成する方法を工程の順番
にしたがって示した断面図である。4 to 7 are sectional views showing a method of forming an electrode of a wiring of a CMOS device according to an embodiment of the present invention in the order of steps.
【００３０】図４ないし図７を参照して本実施例につい
て説明すると、次のようである。This embodiment will be described below with reference to FIGS. 4 to 7.
【００３１】図４は、標準ＣＭＯＳの製造工程により、
基板上に素子の絶縁のためのフィールド酸化膜（４０）
が形成された後に、不純物がドーピングされたウェル
（４５），（４６）の表面上にソースおよびドレイン
（４３），（４７）、そしてコンタクト用の不純物ドー
ピング（３９参照）、ゲート酸化膜（４１）、ゲート電
極（４２）が形成されたことを図示している。FIG. 4 shows a process of manufacturing a standard CMOS.
Field oxide film (40) for insulating devices on the substrate
Are formed, the source and drains (43) and (47) are formed on the surfaces of the wells (45) and (46) that are doped with impurities, and the impurity doping for contact (see 39) and the gate oxide film (41) are performed. ) And the gate electrode (42) is formed.
【００３２】図５を参照して、図４に図示した基板上に
配線の電極を形成する目的で酸化膜または窒化膜などの
絶縁膜（４８）を形成する。Referring to FIG. 5, an insulating film (48) such as an oxide film or a nitride film is formed on the substrate shown in FIG. 4 for the purpose of forming wiring electrodes.
【００３３】続いて、図６に示すように、配線の電極、
ケイ素類の電極、異種の金属類の電極の接触が形成され
る部分の上およびフィールド酸化膜（４０）の上の絶縁
膜（４８）を除去してゲート酸化膜（４８ａ），（４８
ｂ）のみを残す。Then, as shown in FIG. 6, wiring electrodes,
The gate oxide films (48a), (48) are formed by removing the insulating film (48) on the portion where the contact of the electrodes of silicons, the electrodes of different metals is formed and on the field oxide film (40).
leave only b).
【００３４】このとき、ゲート電極と配線電極との間の
電気的な連結が必要な場合には、ゲート電極のコンタク
ト連結部分の表面を露出させる。At this time, when electrical connection between the gate electrode and the wiring electrode is required, the surface of the contact connecting portion of the gate electrode is exposed.
【００３５】また、露出されたコンタクト部分の電気的
な特性を改善しようする場合には、その表面に高濃度の
イオンを注入するイオン注入工程、ケイ化物の形成工程
またはこれに相当する工程を実行することもできる。Further, in order to improve the electrical characteristics of the exposed contact portion, an ion implantation step of implanting a high concentration of ions on the surface thereof, a silicide formation step or a step corresponding thereto is executed. You can also do it.
【００３６】最終的に、図７に示すように、配線電極用
の物質を塗布し、パターニングして配線電極（４９）を
形成する。Finally, as shown in FIG. 7, a wiring electrode material is applied and patterned to form a wiring electrode (49).
【００３７】これをもって、配線電極（４９）は電極
（３９），（４３），（４７）または電極（４２），
（４４）等と電気的に連結された構造をとる。With this, the wiring electrode (49) becomes the electrode (39), (43), (47) or the electrode (42),
(44) and the like are electrically connected.
【００３８】[0038]
【発明の効果】以上において説明にしたように、本発明
によると、コンタクトホールの形成工程を実行せずに、
コンタクトの上に配線電極が自動整列されるので、コン
タクトの最小長さＬが縮小される程コンタクトの形成工
程を容易に実行することができるばかりでなく、コンタ
クトホールの整列が不必要となる。As described above, according to the present invention, the contact hole forming step is not performed,
Since the wiring electrodes are automatically aligned on the contacts, the process of forming the contacts can be performed more easily as the minimum length L of the contacts is reduced, and the alignment of the contact holes becomes unnecessary.
【００３９】これをもって、本発明のコンタクトの形成
工程によると、従来の工程に比べ工程の余裕度を大幅に
増加することができ、コンタクト面積の増加によってコ
ンタクト抵抗も大幅に減少させることができ、その結
果、回路の性能を改善することができる。Thus, according to the contact forming process of the present invention, the margin of the process can be significantly increased as compared with the conventional process, and the contact resistance can be greatly reduced by increasing the contact area. As a result, the performance of the circuit can be improved.
【図１】本発明の望ましい実施例にかかるＣＭＯＳ素子
の構造を示す断面図である。FIG. 1 is a sectional view showing a structure of a CMOS device according to a preferred embodiment of the present invention.
【図２】図１のｎ−ＭＯＳＦＥＴ部分を示す平面図であ
る。FIG. 2 is a plan view showing an n-MOSFET portion of FIG.
【図３】従来のＣＭＯＳ素子と本発明にかかるＣＭＯＳ
素子のコンタクト抵抗の計算結果を示す図である。FIG. 3 shows a conventional CMOS device and a CMOS according to the present invention.
It is a figure which shows the calculation result of the contact resistance of an element.
【図４】本発明の実施例によりＣＭＯＳ素子の配線の電
極を形成する方法を示す断面図である。FIG. 4 is a cross-sectional view showing a method of forming an electrode of a wiring of a CMOS device according to an embodiment of the present invention.
【図５】本発明の実施例によりＣＭＯＳ素子の配線の電
極を形成する方法を示す断面図である。FIG. 5 is a cross-sectional view showing a method of forming an electrode of a wiring of a CMOS device according to an embodiment of the present invention.
【図６】本発明の実施例によりＣＭＯＳ素子の配線の電
極を形成する方法を示す断面図である。FIG. 6 is a cross-sectional view showing a method of forming an electrode of a wiring of a CMOS device according to an embodiment of the present invention.
【図７】本発明の実施例によりＣＭＯＳ素子の配線の電
極を形成する方法を示す断面図である。FIG. 7 is a cross-sectional view showing a method of forming an electrode of a wiring of a CMOS device according to an embodiment of the present invention.
【図８】従来の典型的なＣＭＯＳの構造を図示している
断面図である。FIG. 8 is a cross-sectional view illustrating the structure of a conventional typical CMOS.
【図９】図８のｎ−ＭＯＳＦＥＴ部分を示す平面図であ
る。9 is a plan view showing an n-MOSFET portion of FIG. 8. FIG.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/8238 27/092 Ｈ０１Ｌ 27/08 ３２１ Ｆ (72)発明者 柳 鍾善 大韓民国大田直轄市儒城区漁隱洞ハンビト アパート122−902─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Internal reference number FI Technical display location H01L 21/8238 27/092 H01L 27/08 321 F (72) Inventor Yanagi Zhongshan, Republic of Korea Daejeon, Daejeon Yuihui-dong Hanbito Apartment 122-902
Claims (6)
と、配線用の電極と電気的にそれぞれ連結されるソース
電極の領域および、ドレイン電極の領域と、を備えた電
界効果素子において、 前記ゲート電極の領域を取り囲むように形成され、しか
も前記ソース電極の領域の中で前記ゲート電極の領域と
隣接する一部分の上と、前記ドレイン電極の領域の中で
前記ゲート電極の領域と隣接する一部分の上とに形成さ
れた絶縁膜を、さらに備えるとともに、 前記配線用の電極のそれぞれが、前記素子隔離用の絶縁
膜の上と、前記絶縁膜によって覆われていない前記ソー
ス電極の領域および前記ドレイン電極の領域の残りの表
面上と、前記絶縁膜上とに直接的に形成される一方、そ
れらの相互間は前記素子隔離用の絶縁膜と前記絶縁膜に
よってそれぞれ電気的に絶縁されることを特徴とする電
界効果素子。1. A field effect element comprising an element isolation insulating film, a gate electrode region, a source electrode region and a drain electrode region electrically connected to a wiring electrode, respectively. It is formed so as to surround the region of the gate electrode, and on a part of the region of the source electrode adjacent to the region of the gate electrode, and adjacent to the region of the gate electrode in the region of the drain electrode. An insulating film formed on a part of the insulating film is further provided, and each of the wiring electrodes has a region of the source electrode not covered by the insulating film for isolating the element and the insulating film, and It is formed directly on the remaining surface of the region of the drain electrode and on the insulating film, and between them is separated by the insulating film for element isolation and the insulating film. Re field effect device, wherein electrically be insulated.
れる他の一つの配線電極を付加的に備えることを特徴と
する請求項１記載の電界効果素子。2. The field effect device according to claim 1, further comprising another wiring electrode electrically connected to the region of the gate electrode.
域と、配線用の電極と電気的にそれぞれ連結されるソー
ス電極の領域および、ドレイン電極の領域が形成された
基板上に絶縁膜を形成する工程と、 前記絶縁膜の中で前記ゲート電極の領域を取り囲む部分
のみ残して残りの部分を除去して、前記素子隔離用の絶
縁膜の表面と、前記ソース電極の領域の表面の一部およ
び、前記ドレイン電極の領域の表面の一部が露出される
ようにする工程と、 配線電極用の物質を塗布しパターニングして配線電極を
形成する工程をと、を包含することを特徴とする電界効
果素子の電極形成方法。3. An insulating film on a substrate on which an insulating film for element isolation, a region of a gate electrode, a region of a source electrode electrically connected to an electrode for wiring, and a region of a drain electrode are formed. And a part of the insulating film that surrounds the region of the gate electrode is removed, and the remaining part is removed, and the surface of the insulating film for device isolation and the surface of the region of the source electrode are removed. And a step of exposing a part of the surface of the drain electrode region, and a step of applying a wiring electrode material and patterning it to form a wiring electrode. Forming method of electrode of field effect element.
の間の電気的な連結の必要性に応じて、前記絶縁膜の除
去工程が前記ゲート電極の領域上の前記絶縁膜の一部を
除去してゲート電極の領域の表面の一部を露出させる工
程を付加的に包含することを特徴とする請求項３記載の
電界効果素子の電極形成方法。4. The step of removing the insulating film removes a part of the insulating film on the region of the gate electrode according to the necessity of electrical connection between the region of the gate electrode and the wiring electrode. The method for forming an electrode of a field effect element according to claim 3, further comprising a step of removing the surface of the gate electrode to expose a part of the surface.
質塗布工程との間に、前記ソース電極の領域の前記露出
された表面上と前記ドレイン電極の領域の前記露出され
た表面上にケイ化物を形成する工程を付加的に包含する
ことを特徴とする請求項３記載の電界効果素子の電極形
成方法。5. Between the step of removing the insulating film and the step of applying a material for a wiring electrode, the exposed surface of the region of the source electrode and the exposed surface of the region of the drain electrode are formed. The method for forming an electrode of a field effect element according to claim 3, further comprising a step of forming a silicide.
さによって決定することを特徴とする請求項３、４また
は５記載の電界効果素子の電極形成方法。6. The method for forming an electrode of a field effect element according to claim 3, wherein the minimum length of the contact is determined by the thickness of the insulating film.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR94-32826 | 1994-12-05 | ||
| KR1019940032826A KR0149889B1 (en) | 1994-12-05 | 1994-12-05 | Field effect device and method for forming electrodes of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08162636A true JPH08162636A (en) | 1996-06-21 |
Family
ID=19400352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6315388A Pending JPH08162636A (en) | 1994-12-05 | 1994-12-19 | Field-effect element and formation method of its electrode |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH08162636A (en) |
| KR (1) | KR0149889B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6737704B1 (en) * | 1999-09-13 | 2004-05-18 | Shindengen Electric Manufacturing Co., Ltd. | Transistor and method of manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63226965A (en) * | 1987-03-17 | 1988-09-21 | Nec Corp | Semiconductor device |
| JPH021942A (en) * | 1988-06-09 | 1990-01-08 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
-
1994
- 1994-12-05 KR KR1019940032826A patent/KR0149889B1/en not_active IP Right Cessation
- 1994-12-19 JP JP6315388A patent/JPH08162636A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63226965A (en) * | 1987-03-17 | 1988-09-21 | Nec Corp | Semiconductor device |
| JPH021942A (en) * | 1988-06-09 | 1990-01-08 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6737704B1 (en) * | 1999-09-13 | 2004-05-18 | Shindengen Electric Manufacturing Co., Ltd. | Transistor and method of manufacturing the same |
| US6872611B2 (en) | 1999-09-13 | 2005-03-29 | Shindengen Electric Manufacturing Co., Ltd. | Method of manufacturing transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR0149889B1 (en) | 1999-03-20 |
| KR960026751A (en) | 1996-07-22 |
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