JPH08162540A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH08162540A
JPH08162540A JP3354265A JP35426591A JPH08162540A JP H08162540 A JPH08162540 A JP H08162540A JP 3354265 A JP3354265 A JP 3354265A JP 35426591 A JP35426591 A JP 35426591A JP H08162540 A JPH08162540 A JP H08162540A
Authority
JP
Japan
Prior art keywords
region
pellet
semiconductor device
corner
uneven
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3354265A
Other languages
Japanese (ja)
Other versions
JP2830564B2 (en
Inventor
Mikio Koike
幹夫 小池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3354265A priority Critical patent/JP2830564B2/en
Publication of JPH08162540A publication Critical patent/JPH08162540A/en
Application granted granted Critical
Publication of JP2830564B2 publication Critical patent/JP2830564B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: To reduce influence of stress of mold resin to an operation region of a pellet and to make physical characteristic of an entire of a pellet uniform by providing an uneven region wherein an element of the same kind as an inner circuit is formed to a corner region of a pellet. CONSTITUTION: In a semiconductor device which has an inner circuit having an MOS structure with a pellet 18, a gate electrode 9 provided to a region excepting a corner region of the pellet 18, an aluminum wiring 10, a diffusion layer region 11 and a contact 12 and is sealed with mold resin, an uneven region 1 wherein an element of the same kind as an inner circuit is provided to a corner region of the pellet 18. For example, the uneven region 1 which is unrelated to operation of a semiconductor device is arranged in a corner region of the pellet 18 of the MOS type semiconductor device. Although the uneven region 1 has gate polysilicon 2, 3, an aluminum wiring 4, a diffusion layer region 5 and a contact 6 and forms an MOS type structure, each region is electrically disconnected to an inner circuit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【産業上の利用分野】本発明は半導体装置に関し、とく
にそのモールド樹脂封入による応力による影響の改善に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to improvement of the influence of stress caused by encapsulation of a mold resin.

【従来の技術】半導体装置のペレットはその面積を小さ
くする為にペレット有効領域ギリギリまで動作領域を使
用している事と、外部接続の為のリード端子を持つリー
ドフレームのリードフレームのリード端子の配置により
従来の半導体装置ペレットは角部にまで動作領域があっ
た。今日の様に半導体デバイス技術が進歩し、その半導
体装置機能の高級化が要求され、ペレット面積はますま
す増大している。しかしペレット面積が増大すると、モ
ールド樹脂の封入時の加熱や、低温−高温の温度サイク
ルによる樹脂の膨張・収縮・硬化収縮により、応力の影
響を受けやすくなる欠点があった。ペレット面積が大き
くなる程、またペレット中心から離れた程応力が大きく
加わると報告されており、特にペレット角の領域下の特
性変動が発生する可能性があった。[「プラスチックで
密封されたLSIのチップ上において水蒸気によるアル
ミ腐蝕とストレスについて」(MOISTURE−IN
DUCED ALUMINUM CORROSIONA
ND STRESS ON THE CHIP IN
PLASTIC−ENCAPSULATED LS
、1979,IEEE,CH1425−8/79/
oooo−D11S参照]。 本発明の目的は前述の応力に対する問題点を解決するこ
とにある。
2. Description of the Related Art In order to reduce the area of a pellet of a semiconductor device, the operating area is used up to the effective area of the pellet, and the lead terminal of a lead frame having a lead terminal for external connection is used. Depending on the arrangement, the conventional semiconductor device pellet has an operating region even at the corners. As in today's semiconductor device technology, semiconductor device functions are required to be sophisticated, and the pellet area is increasing more and more. However, when the area of the pellets is increased, there is a drawback that the resin is easily affected by stress due to heating at the time of encapsulating the mold resin and expansion / contraction / curing shrinkage of the resin due to the low-high temperature cycle. It has been reported that the larger the area of the pellet and the further away from the center of the pellet, the more stress is applied, and there is a possibility that characteristic fluctuations may occur especially under the pellet angle region. ["Aluminum corrosion and stress due to water vapor on LSI chips sealed with plastic" (MOISTURE-IN
DUCED ALUMINUM CORROSIONA
ND STRESS ON THE CHIP IN
PLASTIC-ENCAPSULATED LS
I s, 1979, IEEE, CH1425-8 / 79 /
oooo- see D11S]. An object of the present invention is to solve the above-mentioned problem with stress.

【課題を解決するための手段】本発明による半導体装置
は、ペレットと、前記ペレットの角領域以外に設けられ
ゲート電極、アルミ配線、拡散層領域及びコンタクトを
有するMOS型構造を備える内部回路とを有し、モール
ド樹脂によって封入された半導体装置において、前記ペ
レットの前記角領域に前記内部回路と同種の素子が形成
された凸凹領域を有することを特徴とする。
A semiconductor device according to the present invention comprises a pellet and an internal circuit provided in a region other than a corner region of the pellet and having a MOS type structure having a gate electrode, aluminum wiring, a diffusion layer region and a contact. In the semiconductor device encapsulated by the mold resin, the semiconductor device is characterized in that the corner region of the pellet has an uneven region in which an element of the same type as the internal circuit is formed.

【実施例】次に、本発明の実施例について図面を用いて
説明する。第1図は本発明の一実施例におけるペレット
角領域のレイアウトを示す模式図である。この実施例は
MOS型半導体装置であり、1は、この半導体装置の動
作には無関係な凸凹領域であり、ペレットの角領域に配
置してある。2,3はゲート用ポリシリコン、4はアル
ミ配線、5は拡散層領域、6はコンタクトでMOS型構
造を形成しているが、各領域とも内部回路とは電気的に
切離されている。次に7は半導体装置の本来の動作を有
する回路領域、8は外部接続用パッドである。9はゲー
トポリシリコン、10はアルミ配線で、いずれも内部回
路と接続されている。11は拡散層領域、12はコンタ
クトである。第2図は実施例の断面図で、切断面は第1
図のA−B間に対応する。13は半導体基板、14はモ
ールド樹脂、15はペレット保護用酸化膜、16はゲー
ト酸化膜、17はペレットをとう載するリードフレーム
である。第2図に示すようにモールド樹脂封入された半
導体装置は、そのモールド樹脂と半導体シリコンと金属
の膨張係数が各々異なっており、温度サイクルなどによ
る応力が加わる。本実施例では第2図中の矢印19で示
す方向に応力が加わる。この応力の大きさはペレット中
心から遠くなる程大きく、ペレット角領域で最大とな
る。そこでこの角領域に内部回路とは無関係な凸凹領域
を持つ事により応力はこの凸凹領域に集中し、本来の動
作領域は保護される。さらに、ペレットの角領域にも内
部回路とは電気的に分離されかつ内部回路を構成する素
子と同種の素子による応力吸収領域が形成されている。
このため、半導体装置のペレット全体の物理的特性をも
均一にすることができる。以上、MOS型半導体装置で
説明したが他の型でも同じである。
Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a schematic diagram showing a layout of a pellet corner region in one embodiment of the present invention. This embodiment is a MOS type semiconductor device, and 1 is an uneven region which is irrelevant to the operation of this semiconductor device and is arranged in the corner region of the pellet. 2 and 3 are gate polysilicon, 4 is aluminum wiring, 5 is a diffusion layer region, and 6 is a contact, which forms a MOS type structure, and each region is electrically isolated from the internal circuit. Next, 7 is a circuit region having the original operation of the semiconductor device, and 8 is an external connection pad. Reference numeral 9 is gate polysilicon, and 10 is aluminum wiring, both of which are connected to an internal circuit. Reference numeral 11 is a diffusion layer region, and 12 is a contact. FIG. 2 is a sectional view of the embodiment, and the cut surface is the first
It corresponds to between A and B in the figure. Reference numeral 13 is a semiconductor substrate, 14 is a mold resin, 15 is an oxide film for protecting pellets, 16 is a gate oxide film, and 17 is a lead frame on which pellets are mounted. As shown in FIG. 2, in a semiconductor device encapsulated in a mold resin, the mold resin, the semiconductor silicon, and the metal have different expansion coefficients, and a stress is applied by a temperature cycle or the like. In this embodiment, stress is applied in the direction indicated by arrow 19 in FIG. The magnitude of this stress increases as the distance from the center of the pellet increases, and becomes maximum in the pellet corner region. Therefore, by providing a concavo-convex region unrelated to the internal circuit in this corner region, stress concentrates on this concavo-convex region, and the original operating region is protected. Further, in the corner area of the pellet, a stress absorption area is formed which is electrically separated from the internal circuit and is formed by an element of the same kind as the element forming the internal circuit.
Therefore, the physical characteristics of the entire pellet of the semiconductor device can be made uniform. Although the MOS type semiconductor device has been described above, the same applies to other types.

【発明の効果】以上説明した様に本発明によれば、ペレ
ットの動作領域に対するモールド樹脂の応力の影響が少
なくなる半導体装置が得られる。さらに本発明によれ
ば、ペレットの角領域にも内部回路とは電気的に分離さ
れかつ内部回路を構成する素子と同種の素子による応力
吸収領域が形成されている。このため、半導体装置のペ
レット全体の物理的特性をも均一にすることができる。
As described above, according to the present invention, it is possible to obtain a semiconductor device in which the influence of the stress of the molding resin on the operating region of the pellet is reduced. Further, according to the present invention, a stress absorbing region is formed in the corner region of the pellet, which is electrically separated from the internal circuit and is formed by the same kind of device as the device forming the internal circuit. Therefore, the physical characteristics of the entire pellet of the semiconductor device can be made uniform.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例のレイアウトを示す模式図、
第2図は第1図の本実施例において半導体ペレットをモ
ールド樹脂封入した状態を示す断面図である。 1……凸凹領域、2,3,9……ゲートポリシリコン、
4.10……アルミ配線、5,11……拡散層領域、
6,12……コンタクト、7……半導体装置の動作領
域、8……外部接続用パッド、13……半導体基板、1
4……モールド樹脂、15……ペレット保護用酸化膜、
16……ゲート酸化膜、17……リードフレーム。
FIG. 1 is a schematic view showing a layout of an embodiment of the present invention,
FIG. 2 is a sectional view showing a state in which the semiconductor pellets are encapsulated in a mold resin in the embodiment of FIG. 1 ... uneven area, 2, 3, 9 ... gate polysilicon,
4.10 ... aluminum wiring, 5,11 ... diffusion layer region,
6, 12 ... Contact, 7 ... Operating area of semiconductor device, 8 ... Pad for external connection, 13 ... Semiconductor substrate, 1
4 ... Mold resin, 15 ... Oxide film for pellet protection,
16 ... Gate oxide film, 17 ... Lead frame.

Claims (1)

【特許請求の範囲】[Claims] ペレットと、前記ペレットの角領域以外に設けられたゲ
ート電極、アルミ配線、拡散層領域及びコンタクトを有
するMOS型構造を備える内部回路とを有し、モールド
樹脂によって封入された半導体装置において、前記ペレ
ットの前記角領域に前記内部回路を同種の素子が形成さ
れた凸凹領域を有することを特徴とする半導体装置。
A semiconductor device having a pellet and an internal circuit having a MOS type structure having a gate electrode, an aluminum wiring, a diffusion layer region, and a contact provided in a region other than a corner region of the pellet, the pellet being a mold device, the pellet comprising: 2. A semiconductor device having an uneven area in which the same kind of element is formed in the internal circuit in the corner area.
JP3354265A 1991-11-21 1991-11-21 Semiconductor device Expired - Lifetime JP2830564B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3354265A JP2830564B2 (en) 1991-11-21 1991-11-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3354265A JP2830564B2 (en) 1991-11-21 1991-11-21 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH08162540A true JPH08162540A (en) 1996-06-21
JP2830564B2 JP2830564B2 (en) 1998-12-02

Family

ID=18436385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3354265A Expired - Lifetime JP2830564B2 (en) 1991-11-21 1991-11-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2830564B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5722220A (en) * 1980-07-16 1982-02-05 Matsushita Electric Ind Co Ltd Optical filter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5722220A (en) * 1980-07-16 1982-02-05 Matsushita Electric Ind Co Ltd Optical filter

Also Published As

Publication number Publication date
JP2830564B2 (en) 1998-12-02

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Effective date: 19970401

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