JPH08153950A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH08153950A
JPH08153950A JP29441494A JP29441494A JPH08153950A JP H08153950 A JPH08153950 A JP H08153950A JP 29441494 A JP29441494 A JP 29441494A JP 29441494 A JP29441494 A JP 29441494A JP H08153950 A JPH08153950 A JP H08153950A
Authority
JP
Japan
Prior art keywords
copper
resist
film
solder
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP29441494A
Other languages
Japanese (ja)
Other versions
JP2595917B2 (en
Inventor
Takuya Nakajima
太久哉 中島
Eiji Maehata
栄治 前畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29441494A priority Critical patent/JP2595917B2/en
Publication of JPH08153950A publication Critical patent/JPH08153950A/en
Application granted granted Critical
Publication of JP2595917B2 publication Critical patent/JP2595917B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To provide a printed wiring board manufacturing method by which width fluctuation in the circuit pattern of a printed wiring board can be suppressed and high-density wiring and a micro-circuit can be easily formed, and then, the contaminant in an electroless plating bath with a plating resist can be prevented. CONSTITUTION: After a first copper film 3 is formed on a copper-plated substrate 1 and the film 3 is coated with a plating resist 3, the resist 5 is removed from the area of a circuit pattern forming part. Then a second copper film 6 is formed in the area from which the resist 5 is removed and a circuit pattern is formed. After forming the circuit pattern, the remaining plating resist is removed and the entire surface of the substrate 1 is coated with a solder film 7. Thereafter, a circuit pattern covered with a solder film 8 is formed by fusing the solder film 7.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は印刷配線板の製造方法に
関し、特に表面実装部品を高密度に実装できる印刷配線
板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board on which surface-mounted components can be mounted at a high density.

【0002】[0002]

【従来の技術】従来の印刷配線板の製造方法のサブトラ
クティブ法において、パネルめっき法とパターンめっき
法がその代表例として知られている。
2. Description of the Related Art Among conventional subtractive methods for manufacturing printed wiring boards, a panel plating method and a pattern plating method are known as typical examples.

【0003】図4(a)〜(f)は従来の印刷配線板の
製造方法のパネルめっき法の一例を説明する工程順に示
した断面図である。従来のパネルめっき法は、まず、図
4(a)に示すように、銅箔2の厚みが18〜70μm
の銅張り基板1を形成する。次に、図4(b)に示すよ
うに、この銅張り基板1に穴あけを行い貫通穴4aを形
成した後、図4(c)に示すように、無電解めっき後電
気めっきにより、20〜35μmの銅被膜3aを形成す
る。次に、図4(d)に示すように、銅被膜3aの上に
約50μmの感光性フィルムあるいは約20μmの密着
レジストを形成し活性光線を照射して銅配線パターン形
成部の領域を露光した後、現像により配線パターン形成
部の領域以外の感光性フィルムあるいは密着レジストを
剥離してポジ型のエッチングレジスト13のパターンを
形成する。次に、図4(e)に示すように、塩化第二銅
エッチング液や塩化第二鉄エッチング液にてエッチング
レジスト13に被膜されていない領域の銅箔2を含む銅
被膜3aをエッチングする。最後に、図4(f)に示す
ように、銅被膜3a上に残存するエッチングレジスト1
3を剥離して銅回路パターン9を形成する。
FIGS. 4 (a) to 4 (f) are cross-sectional views showing an example of a panel plating method in a conventional method of manufacturing a printed wiring board in the order of steps. In the conventional panel plating method, first, as shown in FIG.
Is formed. Next, as shown in FIG. 4B, a hole is formed in the copper-clad substrate 1 to form a through hole 4a, and then, as shown in FIG. A copper coating 3a of 35 μm is formed. Next, as shown in FIG. 4D, a photosensitive film of about 50 μm or an adhesion resist of about 20 μm was formed on the copper coating 3a, and an active ray was irradiated to expose the area of the copper wiring pattern forming portion. After that, the photosensitive film or the adhesive resist other than the area of the wiring pattern forming portion is peeled off by development to form a pattern of the positive type etching resist 13. Next, as shown in FIG. 4E, the copper coating 3a including the copper foil 2 in the region not coated with the etching resist 13 is etched with a cupric chloride etching solution or a ferric chloride etching solution. Finally, as shown in FIG. 4F, the etching resist 1 remaining on the copper coating 3a is formed.
3 is peeled off to form a copper circuit pattern 9.

【0004】図5(a)〜(g)は従来の印刷配線板の
製造方法のパターンめっき法の一例を説明する工程順に
示した断面である。従来のパターンめっき法は、まず、
図5(a)に示すように、銅箔2の厚みが5〜9μmの
銅張り基板1を形成する。次に、図5(b)に示すよう
に、この銅張り基板1に穴あけを行った後、無電解銅め
っきにより2〜5μmの第1の銅被膜3を形成する。次
に、図5(c)に示すように、第1の銅被膜3上の配線
パターン形成部の領域以外にめっきレジスト5を形成し
た後、図5(d)に示すように、電気めっきにより第2
の銅被膜6を形成する。次に、図5(e)に示すよう
に、第2の銅被膜6上にはんだ被膜7を形成した後、図
5(f)に示すように、めっきレジスト5を剥離する。
最後に、図5(g)に示すように、エッチングにより不
要な部分の銅箔2を含む第1の銅被膜3を除去してフュ
ージングによりはんだ被膜7の形状を良好なものとし銅
回路パターンを得る。
FIGS. 5 (a) to 5 (g) are cross-sectional views sequentially showing steps of an example of a pattern plating method in a conventional method of manufacturing a printed wiring board. The conventional pattern plating method is
As shown in FIG. 5A, a copper-clad substrate 1 having a copper foil 2 having a thickness of 5 to 9 μm is formed. Next, as shown in FIG. 5B, a hole is formed in the copper-clad substrate 1, and then a first copper coating 3 of 2 to 5 μm is formed by electroless copper plating. Next, as shown in FIG. 5C, a plating resist 5 is formed in a region other than the region of the wiring pattern forming portion on the first copper film 3, and then, as shown in FIG. Second
Is formed. Next, as shown in FIG. 5E, after forming a solder film 7 on the second copper film 6, the plating resist 5 is peeled off as shown in FIG. 5F.
Finally, as shown in FIG. 5 (g), unnecessary portions of the first copper coating 3 including the copper foil 2 are removed by etching, and the shape of the solder coating 7 is improved by fusing to form a copper circuit pattern. obtain.

【0005】[0005]

【発明が解決しようとする課題】この従来の印刷配線板
の製造方法であるパネルめっき法ではエッチングによっ
て回路を形成するため、エッチングの微妙な条件、例え
ば基板の表裏及び同一面内の位置におけるエッチング量
の違いにより回路パターンの幅の精度を低下させてい
る。更に、めっき厚の精度も、回路パターンの幅精度に
影響をあたえるので、高密度配線や微小回路パターンの
形成が困難であるという問題点がある。
In the panel plating method, which is a conventional method for manufacturing a printed wiring board, a circuit is formed by etching. Therefore, delicate conditions of etching, for example, etching at front and back surfaces of a substrate and at positions in the same plane. The difference in the amount reduces the precision of the width of the circuit pattern. Further, since the accuracy of the plating thickness also affects the width accuracy of the circuit pattern, there is a problem that it is difficult to form a high-density wiring or a minute circuit pattern.

【0006】一方、パターンめっき法ではエッチング量
が小量であり回路パターンの幅のばらつきを抑えること
ができる。しかし、めっきレジストを形成している状態
ではんだ被膜を形成するため、めっしレジストによっ
て、はんだ浴が汚染されると言う問題点がある。
On the other hand, in the pattern plating method, the etching amount is small, and the variation in the width of the circuit pattern can be suppressed. However, since the solder film is formed while the plating resist is formed, there is a problem that the solder bath is contaminated by the plating resist.

【0007】本発明の目的は、高密度配線や微小回路の
形成が容易ではんだ浴の汚染のない印刷配線板の製造方
法を提供することにある。
An object of the present invention is to provide a method for manufacturing a printed wiring board in which high-density wiring and microcircuits can be easily formed and there is no contamination of a solder bath.

【0008】[0008]

【課題を解決するための手段】第1の発明の印刷配線板
の製造方法は、銅張り基板の表面に無電解銅めっきを行
い第1の銅被膜を形成する工程と、この第1の銅被膜上
にレジストを被覆し回路パターン形成部の領域の前記レ
ジストを剥離する工程と、このレジストが剥離された領
域に第2の銅被膜を形成する工程と、前記銅張り基板上
に残存する前記レジストを剥離する工程と、露出した前
記第1の銅被膜上と前記第2の銅被膜上に無電解はんだ
めっきによりはんだ被膜を形成する工程と、このはんだ
被膜をフュージングする工程とを有する。
According to a first aspect of the present invention, there is provided a method of manufacturing a printed wiring board, comprising the steps of: forming a first copper film by performing electroless copper plating on a surface of a copper-clad substrate; A step of coating the resist on the film and stripping the resist in the area of the circuit pattern forming portion, a step of forming a second copper film in the area where the resist has been stripped, and the step of remaining on the copper-clad substrate The method includes a step of removing a resist, a step of forming a solder coating on the exposed first copper coating and the second copper coating by electroless solder plating, and a step of fusing the solder coating.

【0009】第2の発明の印刷配線板の製造方法は、絶
縁基板の表面に無電解銅めっきを行い第1の銅被膜を形
成する工程と、この第1の銅被膜上にレジストを被覆し
回路パターン形成部の領域の前記レジストを剥離する工
程と、このレジストが剥離された領域に第2の銅被膜を
形成する工程と、前記絶縁基板上に残存する前記レジス
トを剥離する工程と、露出した前記第1の銅被膜上と前
記第2の銅被膜上に無電解はんだめっきによりはんだ被
膜を形成する工程と、パッドを含む実装部をはんだエッ
チングレジストで被覆しこのはんだエッチングレジスト
で被覆されていない領域の前記はんだ被膜を剥離する工
程と、前記はんだエッチングレジストを剥離し前記はん
だ被膜をフュージングする工程とを有する。
According to a second aspect of the present invention, there is provided a method of manufacturing a printed wiring board, comprising: a step of forming a first copper film by electroless copper plating on a surface of an insulating substrate; and a step of coating a resist on the first copper film. Removing the resist in the region of the circuit pattern forming portion, forming a second copper film in the region where the resist has been removed, removing the resist remaining on the insulating substrate, exposing Forming a solder coating on the first copper coating and the second copper coating by electroless solder plating; and covering a mounting portion including a pad with a solder etching resist and coating with the solder etching resist. And removing the solder etching resist and fusing the solder coating.

【0010】[0010]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0011】図1(a)〜(g)は本発明の第1の実施
例を説明する工程順に示した断面図、図2(a),
(b)はそれぞれ第1の実施例の製造工程中の回路パタ
ーンの平面図である。本発明の第1の実施例は、まず、
図1(a)に示すように、厚みが5〜9μmの銅箔2が
貼布された絶縁基板11を所定形状に成形し銅張り基板
1を形成する。次に、図1(b)に示すように、この銅
張り基板1の所定の位置にドリルを用いて直径0.4m
mの貫通穴を穴あけした後、脱脂,ソフトエッチング,
プリデップ,キャタリスト,アクセラレータの前処理を
行い、硫酸銅,ホルムアルデヒド,EDTA,水酸化ナ
トリウムの無電解銅めっき液を用いて温度70℃にて無
電解銅めっきを行い銅箔2上と貫通穴壁面に2〜5μm
の厚みの第1の銅被膜3を被着しスルーホール4を形成
する。このとき、第1の銅被膜3を形成した後の絶縁基
板11上の銅箔2を含む第1の銅被膜3が15μmをこ
えないようにする。これは、絶縁基板11上の銅被膜が
15μmをこえると後工程ではんだ被膜に置換したとき
に銅残渣が発生するからである。
FIGS. 1A to 1G are sectional views showing the first embodiment of the present invention in the order of steps, FIGS.
(B) is a top view of the circuit pattern in the manufacturing process of 1st Example, respectively. The first embodiment of the present invention is as follows.
As shown in FIG. 1A, a copper-clad substrate 1 is formed by molding an insulating substrate 11 on which a copper foil 2 having a thickness of 5 to 9 μm is adhered into a predetermined shape. Next, as shown in FIG. 1 (b), a predetermined diameter of the copper-clad substrate 1 is
After piercing a through hole, degreasing, soft etching,
Pre-treatment of pre-dip, catalyst, accelerator, and electroless copper plating using copper sulfate, formaldehyde, EDTA, sodium hydroxide at a temperature of 70 ° C and copper foil 2 and through hole wall surface. 2 to 5 μm
The first copper coating 3 having a thickness of 1 is deposited to form the through hole 4. At this time, the first copper coating 3 including the copper foil 2 on the insulating substrate 11 after the formation of the first copper coating 3 is set not to exceed 15 μm. This is because if the copper film on the insulating substrate 11 exceeds 15 μm, a copper residue is generated when the copper film is replaced with a solder film in a later step.

【0012】次に、図1(c)に示すように、第1の銅
被膜3上の感光層として耐めっき液性のある膜厚30〜
50μmのドライフィルムをラミネートし、ポジパター
ンフィルムにより回路パターン形成部以外の領域を超高
圧水銀灯にて露光し、炭酸ナトリウムの現像液で現像し
て回路パターン形成部以外の領域にめっきレジスト5を
形成する。このとき、回路パターンの回路間隔が1mm
以上開いていると、後工程のフュージングにて絶縁基板
11上のはんだが銅の回路パターンの部分に集まらずは
んだボールとなって残る可能性があるのでこのはんだボ
ールの発生を防止するため、図2(a),(b)に示す
ように、はんだを集束するはんだ集束パターン10を設
けると良い。
Next, as shown in FIG. 1C, the photosensitive layer on the first copper film 3 has a thickness of 30 to 30 having plating solution resistance.
A 50 μm dry film is laminated, and a region other than the circuit pattern forming part is exposed by a super high pressure mercury lamp with a positive pattern film and developed with a sodium carbonate developer to form a plating resist 5 in the region other than the circuit pattern forming part. To do. At this time, the circuit interval of the circuit pattern is 1 mm.
If the opening is open, the solder on the insulating substrate 11 may not remain on the copper circuit pattern portion and remain as a solder ball due to the fusing in a later process. As shown in FIGS. 2 (a) and 2 (b), it is preferable to provide a solder focusing pattern 10 for focusing the solder.

【0013】次に、図1(d)に示すように、硫酸銅,
硫酸,光沢剤の電気めっき液に常温にて60〜90分間
浸漬するか、或は硫酸銅,ホルムアルデヒド,EDT
A,水酸化ナトリウムの無電解銅めっき液に温度70℃
で10〜15時間浸漬することにより、めっきレジスト
5に被膜されていない部分の第1の銅被膜3上に第2の
銅被膜6を20〜30μm形成した後、図1(e)に示
すように、めっきレジスト5を苛性ソーダの剥離液にて
剥離する。次に、図1(f)に示すように、有機酸ベー
スの無電解はんだめっき液に温度70℃にて浸漬し露出
している第1の銅被膜3と銅箔2の全てと第2銅被膜6
の表面層7〜15μmの厚みを置換させ、はんだ被膜7
を形成する。最後に、図1(g)に示すように、200
℃以上の温度,ピーク温度220〜240℃にて30〜
60秒間フュージングを行うことにより絶縁基板11上
の置換されたはんだ被膜7は銅回路パターン部に集ま
り、フュージング後のはんだ被膜8に覆われた銅回路パ
ターン9が得られる。
Next, as shown in FIG.
Immerse in an electroplating solution of sulfuric acid and brightener at room temperature for 60 to 90 minutes, or use copper sulfate, formaldehyde, EDT
A, 70 ℃ in electroless copper plating solution of sodium hydroxide
After the second copper film 6 is formed on the portion of the first copper film 3 that is not coated with the plating resist 5 by 20 to 30 μm by immersion for 10 to 15 hours, as shown in FIG. Next, the plating resist 5 is peeled off with a stripping solution of caustic soda. Next, as shown in FIG. 1 (f), all of the exposed first copper coating 3 and copper foil 2 and the second copper are immersed in an organic acid-based electroless solder plating solution at a temperature of 70 ° C. Film 6
The thickness of the surface layer of 7 to 15 μm is
To form. Finally, as shown in FIG.
℃ or more, peak temperature 220 ~ 240 ℃ 30 ~
By performing fusing for 60 seconds, the replaced solder film 7 on the insulating substrate 11 gathers in the copper circuit pattern portion, and a copper circuit pattern 9 covered with the solder film 8 after fusing is obtained.

【0014】図3(a)〜(i)は本発明の第2の実施
例を説明する工程順に示した断面図である。本発明の第
2の実施例は、まず、図2(a)に示すように、銅被膜
のない絶縁基板11の所定の位置にドリルを用いて直径
0.4mmの貫通穴を穴あけした後、脱脂,プリディッ
プ,キャタリスト,アクセラレータの前処理を行い、硫
酸銅,ホルムアルデヒド,EDTA,水酸化ナトリウム
の無電解銅めっき液を用いて温度70℃にて無電解銅め
っきを行い貫通穴壁を含む絶縁基板11表面に第1の銅
被膜3とスルーホール4を形成する。次に、図3(b)
に示すように、第1の銅被膜3上に感光層として耐めっ
き液性のある膜厚30〜50μmのドライフィルムをラ
イネートし、ポジパターンフィルムにより回路パターン
形成部以外の領域にめっきレジスト5を超高圧水銀灯に
て露光し、炭酸ナトリウムの現像液で現象して回路パタ
ーン形成部以外の領域にめっきレジスト5を形成する。
次に、図3(c)に示すように、硫酸銅,硫酸,光沢剤
の電気めっき液に常温にて60〜90分間浸漬するか、
或は硫酸銅,ホルムアルデヒド,EDTA,水酸化ナト
リウムの無電解銅めっき液に温度70℃にて10〜15
時間浸漬することにより、めっきレジスト5に被膜され
ていない部分の第1の銅被膜3上に第2の銅被膜6を2
0〜30μm形成した後、図3(d)に示すように、め
っきレジスト5を苛性ソーダの剥離液にて剥離する。
3 (a) to 3 (i) are sectional views showing a second embodiment of the present invention in the order of steps. In the second embodiment of the present invention, first, as shown in FIG. 2A, a through hole having a diameter of 0.4 mm is drilled at a predetermined position of an insulating substrate 11 having no copper film using a drill. Pre-treatment of degreasing, pre-dip, catalyst, accelerator, electroless copper plating at 70 ° C using copper sulfate, formaldehyde, EDTA, sodium hydroxide electroless copper plating solution, including through hole wall The first copper film 3 and the through hole 4 are formed on the surface of the insulating substrate 11. Next, FIG. 3 (b)
As shown in (1), a 30-50 μm-thick dry film having plating solution resistance is lined as a photosensitive layer on the first copper film 3, and a plating resist 5 is applied to a region other than a circuit pattern forming portion by a positive pattern film. Exposure is performed with an ultrahigh pressure mercury lamp, and the phenomenon occurs with a developing solution of sodium carbonate to form a plating resist 5 in a region other than the circuit pattern forming portion.
Next, as shown in FIG. 3 (c), it is immersed in an electroplating solution of copper sulfate, sulfuric acid, and a brightener at room temperature for 60 to 90 minutes,
Alternatively, it is applied to an electroless copper plating solution of copper sulfate, formaldehyde, EDTA, sodium hydroxide at a temperature of 70 ° C. for 10 to 15
By immersing for 2 hours, the second copper coating 6 is formed on the first copper coating 3 not covered by the plating resist 5.
After the formation of 0 to 30 μm, as shown in FIG. 3D, the plating resist 5 is stripped with a stripping solution of caustic soda.

【0015】次に、図3(e)に示すように、有機酸ベ
ースの無電解はんだめっき液に温度70℃にて浸漬し露
出している第1の銅被膜3の全てと第2の銅被膜6の表
面層7〜15μmの厚みを置換させ、はんだ被膜7を形
成する。次に、図3(f)に示すように、パッドなどの
実装部をはんだエッチングレジスト12で被覆した後、
図3(g)に示すように、被覆されていない領域のはん
だ被膜7を剥離する。これにより、フュージングをした
ときに銅回路パターンの回路間隔が1mm以上に開きす
ぎた箇所の絶縁基板11上ではんだボールが発生する現
象を防止することができる。次に、図3(h)に示すよ
うにはんだエッチングレジスト12を剥離した後、図3
(i)に示すように、200℃以上の温度,ピーク温度
220〜240℃にて30〜60秒間フュージングを行
うことにより、パッドなどの実装部がフュージング後の
はんだ被膜8に覆われた銅回路パターン9が得られる。
Next, as shown in FIG. 3 (e), all of the exposed first copper coating 3 is immersed in an organic acid-based electroless solder plating solution at a temperature of 70.degree. The thickness of the surface layer 7 to 15 μm of the coating 6 is replaced to form the solder coating 7. Next, as shown in FIG. 3F, after mounting parts such as pads are covered with a solder etching resist 12,
As shown in FIG. 3 (g), the solder coating 7 in the uncoated area is peeled off. Thereby, it is possible to prevent a phenomenon that a solder ball is generated on the insulating substrate 11 at a location where the circuit interval of the copper circuit pattern is too large to be 1 mm or more when performing the fusing. Next, after the solder etching resist 12 is peeled off as shown in FIG.
As shown in (i), a copper circuit in which a mounting portion such as a pad is covered with the solder coating 8 after fusing by performing fusing at a temperature of 200 ° C. or higher and a peak temperature of 220 to 240 ° C. for 30 to 60 seconds. A pattern 9 is obtained.

【0016】[0016]

【発明の効果】以上説明したように本発明は、めっきレ
ジストを被覆し回路パターン形成部の領域のめっきレジ
ストを剥離した後この剥離した領域に回路パターンを形
成し、さらに、この回路パターン上にはんだ被膜を形成
してこのはんだ被膜をフュージングするので、エッチン
グによる表裏両面および同一面内における回路パターン
の幅のばらつきを抑え高密度配線や微小回路の形成が容
易となる効果がある。
As described above, according to the present invention, the plating resist is coated, the plating resist in the area of the circuit pattern forming portion is peeled off, and then a circuit pattern is formed in the peeled area. Since the solder film is formed and the solder film is fused, variations in the width of the circuit pattern on both the front and back surfaces and in the same surface due to etching are suppressed, and there is an effect that high-density wiring and minute circuits can be easily formed.

【0017】また、めっきレジストによる無電解めっき
浴の汚染を防止できる効果もある。
Further, there is an effect that the electroless plating bath can be prevented from being contaminated by the plating resist.

【0018】[0018]

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(g)は本発明の第1の実施例を説明
する工程順に示した断面図である。
FIGS. 1A to 1G are cross-sectional views shown in the order of steps for explaining a first embodiment of the present invention.

【図2】(a),(b)はそれぞれ第1の実施例の製造
工程中の銅回路パターンの平面図である。
2A and 2B are plan views of a copper circuit pattern during the manufacturing process of the first embodiment, respectively.

【図3】(a)〜(i)は本発明の第2の実施例を説明
する工程順に示した断面図である。
3 (a) to 3 (i) are cross-sectional views shown in the order of steps for explaining a second embodiment of the present invention.

【図4】(a)〜(f)は従来の印刷配線板の製造方法
のパネルめっき法の一例を説明する工程順に示した断面
図である。
FIGS. 4A to 4F are cross-sectional views sequentially illustrating steps of an example of a panel plating method in a conventional method of manufacturing a printed wiring board.

【図5】(a)〜(g)は従来の印刷配線板の製造方法
のパターンめっき法の一例を説明する工程順に示した断
面図である。
5A to 5G are cross-sectional views showing the order of steps for explaining an example of a pattern plating method of a conventional method for manufacturing a printed wiring board.

【符号の説明】[Explanation of symbols]

1 銅張り基板 2 銅箔 3 第1の銅被膜 3a 銅被膜 4 スルーホール 4a 貫通穴 5 めっきレジスト 6 第2の銅被膜 7 はんだ被膜 8 フュージング後のはんだ被膜 9 銅回路パターン 10 はんだ集束パターン 11 絶縁基板 1 Copper-clad substrate 2 Copper foil 3 First copper film 3a Copper film 4 Through hole 4a Through hole 5 Plating resist 6 Second copper film 7 Solder film 8 Solder film after fusing 9 Copper circuit pattern 10 Solder focusing pattern 11 Insulation substrate

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 銅張り基板の表面に無電解銅めっきを行
い第1の銅被膜を形成する工程と、この第1の銅被膜上
にレジストを被覆し回路パターン形成部の領域の前記レ
ジストを剥離する工程と、このレジストが剥離された領
域に第2の銅被膜を形成する工程と、前記銅張り基板上
に残存する前記レジストを剥離する工程と、露出した前
記第1の銅被膜上と前記第2の銅被膜上に無電解はんだ
めっきによりはんだ被膜を形成する工程と、このはんだ
被膜をフュージングする工程とを有することを特徴とす
る印刷配線板の製造方法。
1. A step of forming a first copper film by performing electroless copper plating on a surface of a copper-clad substrate, and coating a resist on the first copper film and removing the resist in a region of a circuit pattern forming portion. Stripping, forming a second copper film in a region where the resist has been stripped, stripping the resist remaining on the copper-clad substrate, and exposing the exposed first copper film. A method for manufacturing a printed wiring board, comprising: a step of forming a solder film on the second copper film by electroless solder plating; and a step of fusing the solder film.
【請求項2】 絶縁基板の表面に無電解銅めっきを行い
第1の銅被膜を形成する工程と、この第1の銅被膜上に
レジストを被覆し回路パターン形成部の領域の前記レジ
ストを剥離する工程と、このレジストが剥離された領域
に第2の銅被膜を形成する工程と、前記絶縁基板上に残
存する前記レジストを剥離する工程と、露出した前記第
1の銅被膜上と前記第2の銅被膜上に無電解はんだめっ
きによりはんだ被膜を形成する工程と、パッドを含む実
装部をはんだエッチングレジストで被覆しこのはんだエ
ッチングレジストで被覆されていない領域の前記はんだ
被膜を剥離する工程と、前記はんだエッチングレジスト
を剥離し前記はんだ被膜をフュージングする工程とを有
することを特徴とする印刷配線板の製造方法。
2. A step of forming a first copper film by performing electroless copper plating on a surface of an insulating substrate, and coating a resist on the first copper film and peeling the resist in a region of a circuit pattern forming portion. Performing a step of forming a second copper film in a region where the resist has been removed, removing the resist remaining on the insulating substrate, and removing the second copper film on the exposed first copper film. Forming a solder film on the copper film by electroless solder plating, and covering the mounting portion including the pad with a solder etching resist, and removing the solder film in a region not covered with the solder etching resist. Stripping the solder etching resist and fusing the solder coating.
JP29441494A 1994-11-29 1994-11-29 Manufacturing method of printed wiring board Expired - Fee Related JP2595917B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29441494A JP2595917B2 (en) 1994-11-29 1994-11-29 Manufacturing method of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29441494A JP2595917B2 (en) 1994-11-29 1994-11-29 Manufacturing method of printed wiring board

Publications (2)

Publication Number Publication Date
JPH08153950A true JPH08153950A (en) 1996-06-11
JP2595917B2 JP2595917B2 (en) 1997-04-02

Family

ID=17807450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29441494A Expired - Fee Related JP2595917B2 (en) 1994-11-29 1994-11-29 Manufacturing method of printed wiring board

Country Status (1)

Country Link
JP (1) JP2595917B2 (en)

Also Published As

Publication number Publication date
JP2595917B2 (en) 1997-04-02

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