JP2000188460A - Manufacture of wiring substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate etching residue and etching irregularity of an electroless plating layer when a wiring layer of a wiring substrate is formed by a semiadditive method. SOLUTION: In a wiring layer formation process by a semiadditive method, an electroless copper plating layer 9 is heated previously and thereafter the exposed electroless copper plating layer 9 is removed by etching. It is possible to eliminate etching residue and prevent over etching without applying guard plating by making the electroless copper plating layer 9 0.3 to 0.9 μm thick.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a wiring board having, for example, a wiring layer comprising an electroless plating layer and an electrolytic plating layer on a substrate surface.

[0002]

2. Description of the Related Art Conventionally, for example, when a wiring layer is formed on the surface of a resin wiring board, the wiring layer is usually formed by electroless plating or electrolytic plating. A method called a semi-additive method is known.

According to the semi-additive method, for example, a copper wiring layer made of, for example, copper is formed by the following method (see FIG. 3). A plating catalyst core of palladium (Pd) is provided on the entire surface of the substrate. By electroless copper (Cu) plating,
An electroless copper (Cu) plating layer having a thickness of 2 μm is formed. A photosensitive film is stuck and exposed and developed. An electrode is attached to the end of the substrate, electrolytic copper plating (copper sulfate plating) is performed on the exposed electroless copper (Cu) plating layer, and a 15 μm thick electrolytic copper (C) is
u) Form a plating layer. The photosensitive film is peeled off, and the electroless copper (Cu) plating layer under the film is removed by soft etching to complete a copper wiring layer (Cu wiring).

[0004]

However, in the above-described semi-additive method, when a wiring layer is formed, etching (soft etching) is performed to remove an extra electroless plating layer. Insufficient etching causes etching residue between wiring layers, which causes a short circuit.

In order to completely remove an unnecessary electroless plating layer. Excessive etching causes over-etching, and causes problems such as thinning, disconnection, and peeling of the wiring layer.

[0006] In addition, such etching residue and over-etching may occur simultaneously in the same wiring board. That is, even within one wiring board, over-etching may occur in a certain portion, and etching residue may occur in another portion. This is presumed to be because the arrangement of metal particles in the electroless plating layer is not always uniform in the wiring board, and there is a slight difference, so that the etching rate is affected to cause a difference in the board. You.

[0007] Therefore, conventionally, in order to avoid such a problem, it is necessary to take the following countermeasures (see FIG. 4). An electroless copper (Cu) plating layer is formed on the entire surface of the substrate. A resist pattern is formed on the surface of the electroless plating layer. An electrolytic copper (Cu) plating layer is formed on the electroless copper (Cu) plating layer in the opening of the resist pattern. Masking for etching guard is performed on the electrolytic copper (Cu) plating layer. The resist pattern is removed. The electroless copper (Cu) plating layer is removed by etching. After removing the masking (layer), a copper wiring layer (Cu wiring)
To complete. A blackening process is performed on the copper wiring layer (Cu wiring).

That is, in this method, as a countermeasure for over-etching for protecting the copper wiring layer, etching is performed by applying masking or guard plating on the electrolytic copper plating layer. However, in this method, it is necessary to perform masking and guard plating, and there is a problem that a process of forming a wiring layer becomes very complicated and cost is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a method of manufacturing a wiring board which can be easily operated and effectively prevent problems such as overetching and remaining etching when manufacturing the wiring board. With the goal.

[0010]

According to a first aspect of the present invention, there is provided a wiring board having a structure in which an electroplating layer is formed on an electroless plating layer. A step of forming an electroless plating layer, and a step of forming a plating resist layer having an opening of a predetermined pattern on the electroless plating layer, and on the electroless plating layer corresponding to the opening of the pattern, A step of forming an electrolytic plating layer by electrolytic plating, a step of removing the plating resist layer, a heating step of performing a heat treatment on the electroless plating layer, and an extra step corresponding to a portion where the plating resist layer is removed. A method for manufacturing a wiring board, comprising: an etching step of removing an electrolytic plating layer.

According to the present invention, by performing the heat treatment, there is no variation in the etching rate in the subsequent etching step, and the etching is performed at a substantially uniform rate over the entire substrate. And no etching residue occurs. The reason is presumed that the heat treatment makes the arrangement of the metal particles in the electroless plating layer uniform and also makes the etching rate uniform.

Further, the invention of claim 2 provides a method of manufacturing a wiring board according to claim 1, wherein the thickness of the electroless plating layer is 0.3 to 0.9 μm. I do. The present invention, over-etching and etching residue,
Furthermore, a method for manufacturing a suitable wiring board without pinholes is shown.

More specifically, first, a thickness of 0.3
An electroless plating layer having a thickness of ~ 0.9 µm is formed, and a plating resist layer (photosensitive resist) is formed on the electroless plating layer.
To form Then, an electroplating layer is formed on the electroless plating layer in the opening of the plating resist layer, and after the plating resist layer is removed, a heat treatment is applied to the electroless plating layer. Is removed.

That is, according to the present invention, the electroless plating layer is subjected to a heat treatment before etching, and the electroless plating layer has a thickness as small as 0.9 μm or less. Even without applying masking or guard plating, without damaging the electrolytic plating layer,
The electrolytic plating layer can be quickly removed. In addition, since the etching is performed at a uniform etching rate over the entire wiring substrate, there is no risk of over-etching (see FIG. 2A) or remaining etching even if the etching conditions are not strictly controlled. Efficiency is greatly improved. Also, since there is no need to apply masking or guard plating, the manufacturing process can be simplified. Further, since the thickness of the electroless plating layer is reduced to 0.9 μm, the time for forming the electroless plating layer can be shortened, which can contribute to a reduction in manufacturing cost.

Further, the thickness of the electroless plating layer is 0.3
Since it is at least μm, the substrate surface can be reliably covered by electroless plating. Therefore, even if electrolytic plating is performed later, a pinhole (see FIG. 2B) does not occur in the formed wiring layer.

Further, the invention according to claim 3 has a gist of the method of manufacturing a wiring board according to claim 1 or 2, wherein the substrate surface is etched after the etching step.

In the present invention, since the substrate surface is etched after the etching step, even if the electroless plating layer remaining on the substrate surface is scattered, it can be removed together with the resin on the substrate surface. The etchant for the substrate surface may be appropriately selected and used according to the material of the substrate surface, and for example, a potassium permanganate solution or the like is used.

As a material of the plating resist layer of the present invention, for example, a photosensitive resin such as a photosensitive epoxy resin is preferable. That is, by performing processing such as exposure and development on the photosensitive resin, a desired resist pattern,
That is, a so-called negative pattern that forms the periphery of the wiring pattern to be formed can be formed.

As a method of disposing the photosensitive resin on the substrate surface, a method of applying the photosensitive resin by screen printing or spin coating, or a method of attaching a photosensitive film made of the photosensitive resin can be adopted.

Examples of the type of the wiring layer include a wiring layer made of a conductive metal such as copper, nickel, gold, and silver. Therefore, an electroless plating layer or an electrolytic plating layer is used for these wirings. It is made of metal. Also,
When performing the electroless plating, as a pretreatment,
A method in which a growth nucleus (Pd, Au, or the like) for electroless plating is adhered to a place (opening) where an electroless plating layer is to be formed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment (embodiment) of a method of manufacturing a wiring board according to the present invention will be sequentially described with reference to FIGS. The method for manufacturing a wiring board according to the present embodiment is an improvement of the so-called semi-additive method.

(1) First, in order to form a base, B
An epoxy resin (Provicoat; trade name) is applied to the surface of the T substrate 3 and is heated and cured at 150 ° C. for 1 hour to form a base layer 5. (2) Next, in order to enhance the adhesion to the copper wiring layer 7 to be formed, the surface of the base epoxy resin is etched with a potassium permanganate aqueous solution to roughen the surface. Thus, a substrate S including the BT substrate 3 and the underlayer 5 is prepared as shown in FIG.

(3) Next, as shown in FIG. 1B, as a pretreatment for electroless plating, Pd is applied to the entire surface of the substrate S by a well-known catalyst treatment and accelerator treatment.
Attach nuclei. (4) Next, as shown in FIG. 1C, an electroless copper plating material (Emplate Cu406A manufactured by Meltex Co., Ltd .;
A known electroless plating is performed on the portion where the Pd nucleus is adhered (namely, the entire surface of the substrate S) using a trade name (trade name), and the thickness is in the range of 0.3 to 0.9 μm (for example, the thickness of 0.1 μm). 7μ
m) An electroless copper plating layer 9 is formed.

That is, at this time, the electroless copper plating layer 9
The thickness is controlled to 0.7 μm. Specifically, the plating time is controlled, and the plating solution is controlled by an automatic analyzer and replenisher to stabilize the composition of the plating solution. The thickness of the copper plating layer 9 is adjusted.

(5) Next, as shown in FIG. 1D, a dry film is adhered on the electroless copper plating layer 9 to a thickness of 20 μm to form a photosensitive epoxy resin layer 13. (6) Next, using a photomask (not shown), the photosensitive epoxy resin layer 13 is subjected to UV exposure,
The part other than the part where the copper wiring layer 7 is formed is cured.

(7) Next, as shown in FIG. 1E, the unexposed portion (that is, the portion where the copper wiring layer 7 is formed) is dissolved and removed with a 1% aqueous solution of sodium carbonate. Therefore, a portion of the photosensitive epoxy resin layer 13 that is not dissolved and removed becomes a plating resist layer 15 in a plating process described later.

(8) Next, as shown in FIG. 1 (f), an electric current is applied to the electroless copper plating layer 9 so that an electrolytic copper plating solution (World Metal Corporation copper sulfate plating solution ACB-9) is applied.
0; trade name) and performing well-known electrolytic plating.
An electrolytic copper plating layer 11 having a thickness of μm is formed on the electroless copper plating layer 9.

The above-mentioned plating method is the same as a well-known plating method for a multilayer printed wiring board, and will not be described in detail (for example, “multilayer printed wiring board step 365”;
Co-authored by Fujihira and Fujimori; Industrial Research Committee; published in 1989).

(9) Next, as shown in FIG. 1 (g), the plating resist layer 15 is removed by using a well-known aqueous sodium hydroxide solution, and the electroless copper plating layer at the position where the plating resist layer 15 is removed. 9 and exposed at 150 ° C. for 120
Heat treatment for a minute.

(10) Next, the electroless copper plating layer 9 where the plating resist layer 15 has been removed is removed by using a sodium sulfate-based etching solution (EBARA UZelite PB-228: trade name) (FIG. 1). (H)). After that, the surface of the electrolytic copper plating layer 11 is roughened by using an etching solution (MEC etch bond CZ-8100: trade name). (11) Then, the surface of the underlayer 5 exposed in the etching step of the electroless copper plating layer 9 is subjected to resin etching using a potassium permanganate solution to remove unnecessary deposits on the surface of the underlayer 5. It is removed together with the resin on the surface to complete the copper wiring layer 7. The copper wiring layer 7 formed in this way can obtain an adhesion strength equal to or higher than that of a conventional blackening treatment with a resin insulating layer (not shown) further laminated on the copper wiring layer 7. .

As described above, in the present embodiment, since the heating treatment is performed at 150 ° C. for 120 minutes before the etching treatment of the electroless copper plating layer 9, the etching rate in the etching step of the electroless copper plating layer 9 is increased. Can be made substantially uniform over the entire surface of the substrate. Therefore, the etching residue of the electroless plating layer 9 does not occur locally.

In this embodiment, since the electroless copper plating layer 9 exposed at portions other than the copper wiring layer 7 is as thin as 0.9 μm or less, the electroless copper plating layer 9 is etched in a short time. Moreover, it can be sufficiently removed. Also,
Since neither masking nor guard plating is required, the working process can be simplified and the manufacturing cost can be reduced.

In the above embodiment, the example in which the wiring layer is formed on the surface of the substrate S has been described, but the following (12) to (1)
By appropriately repeating the step 8), a desired multilayer wiring board can be obtained. (12) A photosensitive resin insulating layer is formed on the copper wiring layer 7 (see FIG. 1H). (13) Via holes are formed in the resin insulating layer by a known photolithography technique, and a part of the copper wiring layer 7 is exposed. (14) The exposed upper surface of the copper wiring layer 7, the inner peripheral surface of the via hole,
Then, an electroless copper plating layer of 0.3 to 0.9 μm is formed on the resin insulating layer. (15) A plating resist layer having openings of a predetermined pattern is formed on the electroless copper plating layer. (16) An electrolytic copper plating layer is formed by electrolytic copper plating on the electroless plating layer corresponding to the opening of the pattern. (17) The plating resist layer is removed. (18) The surface of the electrolytic copper plating layer is roughened, and an excess electroless copper plating layer corresponding to a portion where the plating resist layer has been removed is removed to form a copper wiring layer.

The etchant used in the surface roughening treatment of the wiring layer in this embodiment includes, in addition to the above-mentioned MEC etch bond (trade name) manufactured by MEC, neo-brown (trade name) manufactured by EBARA ) Can also be used. Materials for the etchant include sulfuric acid as oxo acid, hydrogen peroxide or peroxo (mono) acid (salt) as peroxide, chlorine as sodium chloride as auxiliary, and pyrrolol, oxazole, thiazole as azole. And the like can be used.

[0035]

As described above in detail, according to the method of manufacturing a wiring board of the present invention, the variation in the etching rate of the electroless plating layer is reduced, and therefore, the etching residue of the electroless plating layer and the electrolytic etching are reduced. The occurrence rate of over-etching of the plating layer can be greatly reduced.

Further, the surface roughening treatment of the wiring layer and the unnecessary electroless plating layer removal treatment can be performed in the same process, and furthermore, since masking and guard plating are not required, the working process can be simplified. And manufacturing costs can be reduced.

After the surface of the wiring layer is roughened, the surface of the underlayer 5 is etched with a resin, so that unnecessary deposits on the surface (electroless copper plating layer (metal particles) remaining scattered and remaining) are formed. And plating catalyst nuclei such as palladium, and metal particles eluted from the wiring layer during the surface roughening treatment of the wiring layer and adhered to the underlayer 5) can be reliably removed together with the underlying resin. Furthermore, the thickness of the electroless plating layer is 0.3 μm
Since the thickness is sufficiently large as described above, the occurrence of pinholes can be prevented. Further, since the thickness is as small as 0.9 μm or less, problems such as over-etching and residual etching can be effectively prevented.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating a method for manufacturing a wiring board according to an embodiment.

FIGS. 2A and 2B are explanatory diagrams showing a defect of a conventional wiring board, in which FIG.
FIG. 4 is an explanatory view showing a defect of a wiring layer due to a pinhole.

FIG. 3 is an explanatory diagram showing a conventional technique.

FIG. 4 is an explanatory diagram showing a conventional technique.

[Explanation of symbols]

 3: BT substrate 5: Underlayer 7: Copper wiring layer 9: Electroless copper plating layer 11: Electrolytic copper plating layer 13: Photosensitive epoxy resin layer 15: Plating resist layer S: Substrate

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Naoki Kito 14-18 Takatsuji-cho, Mizuho-ku, Nagoya-shi, Aichi Japan Inside Nihon Toku Toi Co., Ltd. (72) Inventor Satoshi Hirano 14th Takatsuji-cho, Mizuho-ku, Nagoya-shi, Aichi No. 18 F-term in Japan Special Ceramics Co., Ltd. (reference) 5E343 AA16 AA17 BB14 BB23 BB24 BB25 BB44 CC43 CC73 DD33 DD43 DD76 EE37 ER16 ER18 ER26 ER33 GG20

Claims (3)

[Claims] 1. A wiring board having a structure in which an electrolytic plating layer is formed on an electroless plating layer, wherein: a step of forming an electroless plating layer on the substrate surface by electroless plating; Forming a plating resist layer having an opening of a predetermined pattern, on the electroless plating layer corresponding to the opening of the pattern,
A step of forming an electrolytic plating layer by electrolytic plating, a step of removing the plating resist layer, a heating step of performing a heat treatment on the electroless plating layer, and an extra step corresponding to a portion where the plating resist layer is removed. An etching step of removing an electrolytic plating layer, comprising: 2. The thickness of the electroless plating layer is 0.3 to 0.3.
The method of claim 1, wherein the thickness is 0.9 μm. 3. The substrate according to claim 1, wherein the substrate surface is etched after the etching step.
3. The method for manufacturing a wiring board according to claim 1.