JP3760396B2 - Wiring board manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a wiring board having, for example, a wiring layer comprising an electroless plating layer and an electrolytic plating layer on the surface of the board.
[0002]
[Prior art]
Conventionally, for example, when a wiring layer is formed on the surface of a resin wiring board, the wiring layer is usually formed by electroless plating or electrolytic plating, and this wiring layer forming method is called a semi-additive method. The method is known.
[0003]
According to this semi-additive method, for example, a copper wiring layer made of, for example, copper is formed by the following method (see FIG. 3).
(1) A plating catalyst nucleus of palladium (Pd) is attached to the entire substrate surface.
(2) An electroless copper (Cu) plating layer having a thickness of 1 to 2 μm is formed on the entire surface of the substrate by electroless copper (Cu) plating.
(3) A photosensitive film is attached, and exposure and development are performed.
(4) An electrode is attached to the end of the substrate, and electrolytic copper plating (copper sulfate plating) is performed on the exposed electroless copper (Cu) plating layer, and electrolytic copper having a thickness of 15 μm is formed on the electroless copper (Cu) plating layer. (Cu) A plating layer is formed.
(5) The photosensitive film is peeled off and the electroless copper (Cu) plating layer under the film is removed by soft etching to complete a copper wiring layer (Cu wiring).
[0004]
[Problems to be solved by the invention]
However, in the above-described semi-additive method, when forming a wiring layer, etching (soft etching) is performed in order to remove an unnecessary electroless plating layer. If etching is insufficient, etching is performed between wiring layers. The rest occurs, causing a short circuit.
[0005]
Also, to completely remove the excess electroless plating layer. If etching is performed excessively, over-etching occurs, and problems such as thinning, disconnection, and peeling of the wiring layer occur.
[0006]
Moreover, such etching residue and over-etching may occur simultaneously in the same wiring board. That is, even within one wiring board, overetching may occur in a certain portion, and etching residue may occur in another portion. This is presumed that the arrangement of metal particles in the electroless plating layer is not necessarily uniform in the wiring board, and there is a subtle difference, which affects the etching rate even in the board. The
[0007]
Therefore, conventionally, in order to avoid such a problem, for example, it has been necessary to take the following countermeasures (see FIG. 4).
(1) An electroless copper (Cu) plating layer is formed on the entire surface of the substrate.
(2) A resist pattern is formed on the surface of the electroless plating layer.
(3) An electrolytic copper (Cu) plating layer is formed on the electroless copper (Cu) plating layer in the opening of the resist pattern.
(4) Masking for etching guard is performed on the electrolytic copper (Cu) plating layer.
(5) The resist pattern is removed.
(6) The electroless copper (Cu) plating layer is removed by etching.
(7) The masking (layer) is removed to complete the copper wiring layer (Cu wiring).
(8) Blackening treatment is applied to the copper wiring layer (Cu wiring).
[0008]
That is, in this method, as an overetching measure for protecting the copper wiring layer, etching is performed by applying masking or guard plating on the electrolytic copper plating layer. However, this method requires masking or guard plating, and the process of forming the wiring layer is very complicated, resulting in high costs.
[0009]
An object of the present invention is to provide a method of manufacturing a wiring board that is easy to work and can effectively prevent problems such as over-etching and etching residue when manufacturing a wiring board. To do.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 is a wiring board having a structure in which an electroplating layer is formed on an electroless plating layer, wherein the electroless plating layer is formed on the substrate surface by electroless plating. And forming a plating resist layer having an opening of a predetermined pattern on the electroless plating layer, and forming an electroplating layer by electroplating on the electroless plating layer corresponding to the opening of the pattern A step, a step of removing the plating resist layer, a heating step of performing a heat treatment on the electroless plating layer, and an etching step of removing an excess electroless plating layer corresponding to the location where the plating resist layer is removed. A gist of a method for manufacturing a wiring board, comprising:
[0011]
According to the present invention, by performing the heat treatment, there is no variation in the etching rate in the subsequent etching step, and etching is performed at a substantially uniform rate over the entire substrate, so that overetching locally in the substrate, Alternatively, no etching residue occurs.
The reason is presumed that the heat treatment makes the arrangement of the metal particles in the electroless plating layer uniform and the etching rate uniform.
[0012]
Furthermore, the invention of claim 2 is summarized in the method for manufacturing a wiring board according to claim 1, wherein the electroless plating layer has a thickness of 0.3 to 0.9 μm.
The present invention shows a method of manufacturing a suitable wiring board without over-etching, etching residue, and pinholes.
[0013]
Specifically, first, an electroless plating layer having a thickness of 0.3 to 0.9 μm is formed on the substrate surface, and a plating resist layer (photosensitive resist) is formed on the electroless plating layer. Then, an electrolytic plating layer is formed on the electroless plating layer in the opening of the plating resist layer, and after removing the plating resist layer, the electroless plating layer is subjected to a heat treatment, and then an unnecessary electroless plating layer is etched. Remove.
[0014]
That is, in the present invention, the electroless plating layer is subjected to heat treatment before etching, and the thickness of the electroless plating layer is as thin as 0.9 μm or less. Even without masking or guard plating, the electrolytic plating layer can be quickly removed without damaging the electrolytic plating layer. Moreover, since etching is performed at a uniform etching rate over the entire wiring board, there is no fear of over-etching (see FIG. 2 (a)) or remaining etching even if the etching conditions are not strictly controlled. Efficiency is greatly improved. Further, since it is not necessary to perform masking or guard plating, the manufacturing process can be simplified. Further, since the thickness of the electroless plating layer is reduced to 0.9 μm, the time for forming the electroless plating layer can be shortened, which can contribute to the reduction of the manufacturing cost.
[0015]
Furthermore, since the thickness of the electroless plating layer is 0.3 μm or more, the substrate surface can be reliably covered by electroless plating. Therefore, even if electrolytic plating is performed later, no pinhole (see FIG. 2B) is generated in the formed wiring layer.
[0017]
In the present invention, since the substrate surface is etched after the etching step, even if the electroless plating layer remaining on the substrate surface is scattered, it can be removed together with the resin on the substrate surface. The etching solution for the substrate surface may be appropriately selected and used according to the material for the substrate surface. For example, a potassium permanganate solution or the like is used.
[0018]
As a material of the plating resist layer of the present invention, for example, a photosensitive resin such as a photosensitive epoxy resin is suitable. That is, a desired resist pattern, that is, a so-called negative pattern that forms the periphery of the wiring pattern to be formed can be formed by performing a process such as exposure and development on the photosensitive resin.
[0019]
In addition, as a method of arranging the photosensitive resin on the substrate surface, a method of applying the photosensitive resin by screen printing, spin coating, or the like, or a method of attaching a photosensitive film made of the photosensitive resin can be employed.
[0020]
As the type of the wiring layer, a wiring layer made of a conductive metal such as copper, nickel, gold, silver or the like can be cited. Therefore, the electroless plating layer or the electrolytic plating layer is made of a metal used for these wirings. Has been.
Further, when the electroless plating is performed, as a pretreatment, growth nuclei (Pd, Au, etc.) of the electroless plating are attached to a place (opening) where the electroless plating layer is formed. The method can be adopted.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Next, an example (Example) of an embodiment of a method for manufacturing a wiring board according to the present invention will be sequentially described with reference to FIG. 1 and FIG. The wiring board manufacturing method of this embodiment is an improvement of the so-called semi-additive method.
[0022]
(1) First, in order to form the base, an epoxy resin (Provicoat; trade name) is applied to the surface of the BT substrate 3 and is cured by heating at 150 ° C. for 1 hour to form the base layer 5.
(2) Next, in order to improve the adhesion to the copper wiring layer 7 to be formed, the base epoxy resin is subjected to resin etching with an aqueous potassium permanganate solution to roughen the surface. Thus, a substrate S composed of the BT substrate 3 and the base layer 5 is prepared as shown in FIG.
[0023]
(3) Next, as shown in FIG. 1B, Pd nuclei are attached to the entire surface of the substrate S by a well-known catalyst process and an accelerator process as a pretreatment of electroless plating.
(4) Next, as shown in FIG. 1 (c), a portion (that is, the substrate S of the substrate S) to which Pd nuclei are attached using an electroless copper plating material (Emplate Cu406A manufactured by Meltex; trade name). A known electroless plating is performed on the entire surface to form an electroless copper plating layer 9 having a thickness in the range of 0.3 to 0.9 μm (for example, a thickness of 0.7 μm).
[0024]
In other words, at this time, the thickness of the electroless copper plating layer 9 is controlled to 0.7 μm. Specifically, automatic analysis supplementation is performed in order to control the plating time and stabilize the composition of the plating solution. The thickness of the electroless copper plating layer 9 is adjusted by managing the plating solution by the apparatus.
[0025]
(5) Next, as shown in FIG.1 (d), a dry film is affixed on the electroless copper plating layer 9 by the thickness of 20 micrometers, and the photosensitive epoxy resin layer 13 is formed.
(6) Next, using a photomask (not shown), the photosensitive epoxy resin layer 13 is subjected to UV exposure to cure portions other than the portion where the copper wiring layer 7 is formed.
[0026]
(7) Next, as shown in FIG. 1E, the epoxy resin in the unexposed portion (that is, the portion where the copper wiring layer 7 is formed) is dissolved and removed with a 1% aqueous solution of sodium carbonate. Accordingly, a portion of the photosensitive epoxy resin layer 13 that is not dissolved and removed becomes a plating resist layer 15 in a plating process described later.
[0027]
(8) Next, as shown in FIG.1 (f), an electric current is sent with respect to the electroless copper plating layer 9, and an electrolytic copper plating liquid (copper sulfate plating liquid ACB-90 by World Metal Co., Ltd .; ), A known electrolytic plating is performed to form an electrolytic copper plating layer 11 having a thickness of 15 μm on the electroless copper plating layer 9.
[0028]
Note that the plating method described above is the same as the plating method for well-known multilayer printed wiring boards, and therefore will not be described in detail (for example, “Multilayer printed wiring board step 365”; Fujihira and Fujimori co-author; Industrial Research Committee; see 1989 issue) ).
[0029]
(9) Next, using a known sodium hydroxide aqueous solution, as shown in FIG. 1G, the plating resist layer 15 is removed, and the electroless copper plating layer 9 where the plating resist layer 15 is removed is exposed. And heat treatment at 150 ° C. for 120 minutes.
[0030]
(10) Next, the electroless copper plating layer 9 where the plating resist layer 15 has been removed is removed using a sodium sulfate-based etching solution (Hagiwara UG light PB-228: trade name) (FIG. 1 (h)). reference). Thereafter, the surface of the electrolytic copper plating layer 11 is roughened using an etching solution (MEC etch bond CZ-8100: trade name).
(11) Thereafter, the surface of the underlayer 5 exposed in the etching process of the electroless copper plating layer 9 is subjected to resin etching with a potassium permanganate solution, and unnecessary deposits on the surface of the underlayer 5 are removed from the underlayer 5. The copper wiring layer 7 is completed by removing together with the resin on the surface.
The copper wiring layer 7 formed in this way can obtain an adhesion strength equal to or higher than that of a resin insulation layer (not shown) further laminated on the copper wiring layer 7 as compared with the conventional blackening treatment. .
[0031]
Thus, in this example, since the heat treatment was performed at 150 ° C. for 120 minutes before the etching process of the electroless copper plating layer 9, the etching rate in the etching process of the electroless copper plating layer 9 was changed over the entire surface of the substrate. It can be almost uniform over the entire area. Therefore, no etching residue of the electroless plating layer 9 is generated locally.
[0032]
Further, in this embodiment, the electroless copper plating layer 9 exposed at a place other than the copper wiring layer 7 is as thin as 0.9 μm or less. Therefore, the electroless copper plating layer 9 is sufficiently etched in a short time. Can be removed. Further, since masking and guard plating are not required, the work process can be simplified and the manufacturing cost can be reduced.
[0033]
In the above embodiment, the example in which the wiring layer is formed on the surface of the substrate S has been described. However, a desired multilayer wiring substrate can be obtained by appropriately repeating the following steps (12) to (18). .
(12) A photosensitive resin insulating layer is formed on the copper wiring layer 7 (see FIG. 1H).
(13) Via holes are formed in the resin insulating layer by a known photolithography technique, and a part of the copper wiring layer 7 is exposed.
(14) An electroless copper plating layer of 0.3 to 0.9 μm is formed on the exposed upper surface of the copper wiring layer 7, the inner peripheral surface of the via hole, and the resin insulating layer.
(15) A plating resist layer having openings of a predetermined pattern is formed on the electroless copper plating layer.
(16) An electrolytic copper plating layer is formed on the electroless plating layer corresponding to the opening of the pattern by electrolytic copper plating.
(17) The plating resist layer is removed.
(18) The surface of the electrolytic copper plating layer is roughened, and an unnecessary electroless copper plating layer corresponding to the portion where the plating resist layer is removed is removed to form a copper wiring layer.
[0034]
In addition, as etching liquid used by the wiring layer surface roughening process of a present Example, in addition to the above-mentioned MEC etch bond (trade name) manufactured by MEC, Neo Brown (trade name) manufactured by Ebara Densan Can be used. Etching solution materials include sulfuric acid as oxo acid, hydrogen peroxide or peroxo (mono) acid (salt) as peroxide, chlorine as sodium chloride as auxiliary agent, pyrrole, oxazole and thiazole as azoles. Etc. can be used.
[0035]
【The invention's effect】
As described above in detail, according to the method for manufacturing a wiring board of the present invention, the variation in the etching rate of the electroless plating layer is reduced, and therefore, the etching residue of the electroless plating layer and the over etching of the electroplating layer are reduced. Occurrence rate can be greatly reduced.
[0036]
Furthermore, the surface roughening process of the wiring layer and the removal process of the unnecessary electroless plating layer can be performed in the same process. Further, since masking and guard plating are not required, the work process can be simplified. Manufacturing cost can be reduced.
[0037]
In addition, since the surface of the underlayer 5 is resin-etched after the surface of the wiring layer is roughened, unnecessary deposits on the surface (electroless copper plating layers (metal particles), palladium, etc. remaining scattered) In addition, the plating catalyst nuclei and metal particles eluted from the wiring layer during the surface roughening treatment of the wiring layer and adhering to the underlying layer 5 can be reliably removed together with the resin thereunder.
Furthermore, since the electroless plating layer thickness is sufficiently thick at 0.3 μm or more, pinholes can be prevented, and since it is as thin as 0.9 μm or less, problems such as over-etching and etching residue are effectively prevented. can do.
[Brief description of the drawings]
FIG. 1 is an explanatory view showing a method for manufacturing a wiring board according to an embodiment.
2A and 2B are diagrams illustrating defects in a conventional wiring board, in which FIG. 2A is an explanatory diagram illustrating a defect in a wiring layer due to overetching, and FIG. 2B is an explanatory diagram illustrating a defect in the wiring layer due to a pinhole;
FIG. 3 is an explanatory diagram showing a conventional technique.
FIG. 4 is an explanatory diagram showing a conventional technique.
[Explanation of symbols]
3: BT substrate 5: foundation layer 7: copper wiring layer 9: electroless copper plating layer 11: electrolytic copper plating layer 13: photosensitive epoxy resin layer 15: plating resist layer S: substrate

Claims (2)

In a wiring board having a structure in which an electroplating layer is formed on an electroless plating layer,
Forming an electroless plating layer on the substrate surface by electroless plating;
Forming a plating resist layer having openings of a predetermined pattern on the electroless plating layer;
Forming an electroplating layer by electroplating on the electroless plating layer corresponding to the opening of the pattern;
Removing the plating resist layer;
A heating step of performing a heat treatment on the electroless plating layer;
An etching step of removing an excess electroless plating layer corresponding to the place where the plating resist layer is removed;
Roughening the surface of the wiring by the electrolytic plating layer;
A resin etching step of etching the surface of the resin that forms the underlying layer exposed in the etching step of the electroless plating layer;
A method of manufacturing a wiring board, wherein the steps are performed in this order.   2. The method for manufacturing a wiring board according to claim 1, wherein the electroless plating layer has a thickness of 0.3 to 0.9 [mu] m.

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