JPH06169144A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

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Publication number
JPH06169144A
JPH06169144A JP32083792A JP32083792A JPH06169144A JP H06169144 A JPH06169144 A JP H06169144A JP 32083792 A JP32083792 A JP 32083792A JP 32083792 A JP32083792 A JP 32083792A JP H06169144 A JPH06169144 A JP H06169144A
Authority
JP
Japan
Prior art keywords
copper
resist
plating
copper layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32083792A
Other languages
Japanese (ja)
Other versions
JPH0738497B2 (en
Inventor
Akira Maniwa
亮 馬庭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP32083792A priority Critical patent/JPH0738497B2/en
Publication of JPH06169144A publication Critical patent/JPH06169144A/en
Publication of JPH0738497B2 publication Critical patent/JPH0738497B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

PURPOSE:To improve a copper etching operation in accuracy when a fine pattern smaller than a specific value is formed through a printed wiring board manufacturing method. CONSTITUTION:Applying properties of tin that electroless plating tin is substituted with copper nearly in the ratio of 1 to 1, a photosensitive resin resist layer 17 is selectively formed on the specific part of a copper plating layer 5 formed on both sides of a board 1, and the exposed copper plating layer 5 is replaced with an electroless tin plating layer 8 at a certain depth. The copper plating layer 5 thinned by separating off tin metal is removed by copper etching solution, whereby copper is lessened in amount of etching in a vertical direction and etching time, and thus a fine pattern can be formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、プリント配線板の製造
方法に関し、特に配線パターンの精度を向上し、パター
ンの高密度化に対応したプリント配線板の製造方法に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board which improves the accuracy of a wiring pattern and is compatible with high density of the pattern.

【0002】[0002]

【従来の技術】近年の電子機器の小型軽量化,高機能化
の進展により、実装する半導体の高集積化,プリント配
線板上の実装部品数の増加が進み、さらにプリント配線
板のパターンの高密度化が問題となってきている。
2. Description of the Related Art Due to recent advances in downsizing, weight reduction, and enhancement of functions of electronic equipment, the degree of integration of semiconductors to be mounted has increased, the number of mounted parts on a printed wiring board has increased, and the pattern of a printed wiring board has a higher height. Densification is becoming a problem.

【0003】従来の技術の高密度パターンを製造する方
法として、図5に示すように電着レジスト(EDレジス
ト)を用いたパターン形成方法がある。
As a conventional method for producing a high density pattern, there is a pattern forming method using an electrodeposition resist (ED resist) as shown in FIG.

【0004】この製造方法は、まず図5(a)に示すよ
うに例えば厚さ1.6mmの基板1の表裏面に厚さ12
μmの銅箔2を張り付けて銅張り積層板3を形成し、銅
張り積層板3に直径0.4mmのドリルで貫通孔4を穿
設する。次に図5(b)に示すように貫通孔4を含む銅
張り積層板3全面に厚さ25μmの銅めっき層5を形成
し、スルーホール6を形成する。
In this manufacturing method, first, as shown in FIG. 5A, for example, a thickness of 12 is formed on the front and back surfaces of a substrate 1 having a thickness of 1.6 mm.
A copper foil 2 having a thickness of μm is attached to form a copper-clad laminate 3, and a through hole 4 is formed in the copper-clad laminate 3 with a drill having a diameter of 0.4 mm. Next, as shown in FIG. 5B, a copper plating layer 5 having a thickness of 25 μm is formed on the entire surface of the copper-clad laminate 3 including the through holes 4, and through holes 6 are formed.

【0005】次に図5(c)に示すようにスルーホール
6を含む銅めっき層5上に電着により全面にレジストを
塗布し、フォトツールを用いて紫外線露光及び現像工程
を経てEDレジスト層11を厚さ20μmに形成する。
Next, as shown in FIG. 5C, a resist is applied on the entire surface by electro-deposition on the copper plating layer 5 including the through holes 6, and the ED resist layer is subjected to ultraviolet exposure and development processes using a photo tool. 11 is formed to a thickness of 20 μm.

【0006】次に図5(d)に示すように露出した銅め
っき層5及び銅箔2からなる銅層をエッチング除去を行
った後、EDレジスト層11を3%水酸化ナトリウムで
剥離し、図5(e)のようにたとえば、スクリーン印刷
によりフォトソルダーレジストを塗布し、その後フォト
ツールを用いて紫外線露光を行い、1%炭酸ナトリウム
により現像し、加熱130℃,45分で硬化し、フォト
ソルダーレジスト層9を形成する。
Next, as shown in FIG. 5 (d), the exposed copper layer consisting of the copper plating layer 5 and the copper foil 2 is removed by etching, and then the ED resist layer 11 is peeled off with 3% sodium hydroxide. As shown in FIG. 5 (e), for example, a photo solder resist is applied by screen printing, then exposed to ultraviolet rays using a photo tool, developed with 1% sodium carbonate, and cured by heating at 130 ° C. for 45 minutes. The solder resist layer 9 is formed.

【0007】[0007]

【発明が解決しようとする課題】従来の技術では、ED
レジスト層11を形成後、銅めっき層5と銅箔2とから
なる銅層のエッチング工程でパターンを形成する。この
とき、銅層が厚く、配線パターンの間隙が狭いと、配線
パターンすそ部同士の短絡が生じる。また、エッチング
時に横方向エッチングにより、配線パターン幅の細りが
生じるため、EDレジストで覆われる配線パターン幅を
狭くすることはできない。
In the prior art, the ED is used.
After the resist layer 11 is formed, a pattern is formed in the step of etching the copper layer including the copper plating layer 5 and the copper foil 2. At this time, if the copper layer is thick and the gap between the wiring patterns is narrow, a short circuit occurs between the skirt portions of the wiring patterns. In addition, since the width of the wiring pattern is narrowed due to the lateral etching at the time of etching, the width of the wiring pattern covered with the ED resist cannot be narrowed.

【0008】従って、銅層のエッチングを実施する際、
エッチングファクターといわれる銅層の垂直方向のエッ
チング量と水平方向のエッチング量の差異から形成され
る比率を考慮して、パターン幅とその間隙を設計しなく
てはならず、銅層が厚いと、必然的に配線パターン間隙
幅,配線パターン幅ともに大きくしなければならない。
例えば、銅箔2と銅めっき層5の厚さの和が50μmの
とき、パターン幅及びパターン間隙幅は、100μm以
上必要となる。それ故、さらにパターン高密度化を行う
ため、微細パターンを形成するには、垂直方向の銅層の
厚さを薄化することにより、微細パターン間の間隙にお
けるパターンすそ部同士の短絡を防ぐ方法が一般に知ら
れている。
Therefore, when etching the copper layer,
The pattern width and its gap must be designed in consideration of the ratio formed by the difference between the etching amount in the vertical direction of the copper layer and the etching amount in the horizontal direction, which is called an etching factor, and if the copper layer is thick, Inevitably, both the wiring pattern gap width and the wiring pattern width must be increased.
For example, when the sum of the thicknesses of the copper foil 2 and the copper plating layer 5 is 50 μm, the pattern width and the pattern gap width need to be 100 μm or more. Therefore, in order to further increase the pattern density, in order to form a fine pattern, a method of preventing a short circuit between pattern skirts in the gap between the fine patterns by thinning the thickness of the copper layer in the vertical direction Is generally known.

【0009】ところが、銅層の厚さを薄化するために
は、銅張り積層板3の銅箔2の厚さを薄化する方法と、
スルーホール6を形成するための銅めっき層5を薄化す
る方法とがある。しかしながら、銅張り積層板3の銅箔
2の薄化を進めると、基板1の樹脂ベースと銅箔2の密
着力を失うという問題があり、一方銅めっき層5の薄化
を進めると、スルーホール6の信頼性がなくなるという
問題がある。
However, in order to reduce the thickness of the copper layer, a method of reducing the thickness of the copper foil 2 of the copper-clad laminate 3,
There is a method of thinning the copper plating layer 5 for forming the through hole 6. However, when the thickness of the copper foil 2 of the copper-clad laminate 3 is advanced, there is a problem in that the adhesive force between the resin base of the substrate 1 and the copper foil 2 is lost. There is a problem that the reliability of the hole 6 is lost.

【0010】本発明の目的は、無電解スズ系めっきを銅
と置換させ、それを剥離し、残存する薄膜化された銅を
エッチングすることにより、微細パターンを形成するプ
リント配線板の製造方法を提供することにある。
An object of the present invention is to provide a method for producing a printed wiring board, which comprises forming a fine pattern by replacing electroless tin-based plating with copper, peeling it off, and etching the remaining thinned copper. To provide.

【0011】[0011]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係るプリント配線板の製造方法は、レジス
ト塗布工程と、めっき工程と、めっき剥離工程と、微細
パターン形成工程とを有するプリント配線板の製造方法
であって、レジスト塗布工程は、基板上の銅層表面に感
光性樹脂レジストを選択的に塗布するものであり、めっ
き工程は、感光性樹脂レジストが塗布されずに露出して
いる銅層表面に、銅との置換析出性を有する無電解スズ
系のめっきを施し、一定深さまでの銅層をスズ系金属に
置換するものであり、めっき剥離工程は、前記スズ系金
属を剥離,除去し、露出している銅層を薄膜化するもの
であり、微細パターン形成工程は、薄膜化された銅層を
エッチングして除去し、微細パターンを形成するもので
ある。
In order to achieve the above object, a method of manufacturing a printed wiring board according to the present invention is a print including a resist coating step, a plating step, a plating stripping step, and a fine pattern forming step. In the method of manufacturing a wiring board, the resist coating step selectively coats the photosensitive resin resist on the surface of the copper layer on the substrate, and the plating step exposes the photosensitive resin resist without coating. The surface of the copper layer is subjected to electroless tin-based plating having a substitution and deposition property with copper, and the copper layer up to a certain depth is replaced with a tin-based metal. Is removed and the exposed copper layer is thinned. In the fine pattern forming step, the thinned copper layer is etched and removed to form a fine pattern.

【0012】また、本発明に係るプリント配線板の製造
方法は、第1のレジスト塗布工程と、めっき工程と、第
2のレジスト塗布工程と、めっき剥離工程と、微細パタ
ーン形成工程と、レジスト剥離工程とを有するプリント
配線板の製造方法であって、第1のレジスト塗布工程
は、基板上の銅層表面に感光性樹脂レジストを選択的に
塗布するものであり、めっき工程は、感光性樹脂レジス
トが塗布されずに露出している銅層表面に無電解はんだ
めっき層を形成した後、無電解はんだめっき浴での浸漬
処理により、一定深さまでの銅層を無電解はんだに置換
するものであり、第2のレジスト塗布工程は、無電解は
んだに置換された領域に感光性樹脂レジストを選択的に
塗布して、表面実装用パッドのパターンを形成するもの
であり、めっき剥離工程は、感光性樹脂レジストが塗布
されずに露出している無電解はんだを剥離,除去し、感
光性樹脂レジストでマスクされていない銅層を薄膜化す
るものであり、微細パターン形成工程は、薄膜化された
銅層をエッチングして除去し、微細パターンを形成する
ものであり、レジスト剥離工程は、残存している感光性
樹脂レジストを剥離,除去するものである。
The method for manufacturing a printed wiring board according to the present invention also includes a first resist coating step, a plating step, a second resist coating step, a plating stripping step, a fine pattern forming step, and a resist stripping step. A method of manufacturing a printed wiring board, the first resist coating step selectively coating a photosensitive resin resist on a copper layer surface on a substrate, and the plating step comprising a photosensitive resin. After forming an electroless solder plating layer on the exposed copper layer surface without resist coating, the copper layer up to a certain depth is replaced with electroless solder by immersion treatment in an electroless solder plating bath. In the second resist coating step, the photosensitive resin resist is selectively coated on the area replaced with the electroless solder to form the pattern of the surface mounting pad. Is to peel and remove the electroless solder exposed without being coated with the photosensitive resin resist, and to thin the copper layer not masked by the photosensitive resin resist. The thinned copper layer is etched and removed to form a fine pattern, and the resist stripping step is to strip and remove the remaining photosensitive resin resist.

【0013】[0013]

【作用】本発明のプリント配線板の製造方法は、無電解
スズ系めっきが銅とほぼ1:1で置換される特性を微細
パターン形成に応用したものである。すなわち、絶縁基
板の表裏面に設けられた銅層の所定部分に選択的に感光
性レジストを形成し、露出した銅層を無電解スズ系めっ
きにより一定深さでスズ系金属に置換し、そのスズ系金
属を剥離し、薄化された銅層部分を銅のエッチング液に
てエッチング除去することにより、銅の垂直方向のエッ
チング量を減らし、エッチングに要する時間を短くし、
微細パターンを形成し、その後感光性レジストを剥離す
る。
The method of manufacturing a printed wiring board according to the present invention applies the characteristic that electroless tin-based plating is replaced with copper at a ratio of about 1: 1 to form a fine pattern. That is, a photosensitive resist is selectively formed on a predetermined portion of the copper layer provided on the front and back surfaces of the insulating substrate, and the exposed copper layer is replaced with a tin-based metal at a constant depth by electroless tin-based plating, By removing the tin-based metal and removing the thinned copper layer portion by etching with a copper etching solution, the vertical etching amount of copper is reduced, and the time required for etching is shortened.
A fine pattern is formed, and then the photosensitive resist is peeled off.

【0014】[0014]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0015】(実施例1)図1,図2は本発明の実施例
1を工程順に示す断面図である。
(Embodiment 1) FIGS. 1 and 2 are sectional views showing Embodiment 1 of the present invention in the order of steps.

【0016】図1(a)に示すように、基板1の表裏面
に厚さ12μmの銅箔2を張り付けた銅張り積層板3
に、直径0.4mmの貫通孔4をドリルで穿設する。
As shown in FIG. 1 (a), a copper-clad laminate 3 in which a 12 μm-thick copper foil 2 is adhered to the front and back surfaces of a substrate 1
Then, a through hole 4 having a diameter of 0.4 mm is drilled.

【0017】次に図1(b)に示すように貫通孔4を含
む銅張り積層板3全面に電解銅めっきを施し、25μm
厚の銅めっき層5を形成し、スルーホール6を形成す
る。次に図1(c)に示すように25μm厚の感光性樹
脂レジスト(ダイナケム社製ラミナーGAドライフィル
ム)を被着し、スルーホール6部分及びパターン幅75
μm,パターン間隙75μmとなるようにパターン部に
マスクを施し、フォトツールを用いて紫外線露光及び現
像工程を経て感光性樹脂レジスト層7をパターニングす
る。感光性樹脂レジスト層7は、100〜120℃,圧
力3〜5kg/cm2にてラミネートを行い、フォトツ
ールを両面に合わせて真空脱気した後、紫外線約60〜
200mJ/cm2にて露光し、1〜3%炭酸ナトリウ
ムにて約30〜90秒現象を実施する。
Next, as shown in FIG. 1 (b), electrolytic copper plating is applied to the entire surface of the copper-clad laminate 3 including the through holes 4 to obtain a thickness of 25 μm.
A thick copper plating layer 5 is formed and a through hole 6 is formed. Next, as shown in FIG. 1 (c), a photosensitive resin resist (Laminar GA dry film manufactured by Dynachem Co., Ltd.) having a thickness of 25 μm is applied, and 6 through holes and a pattern width 75 are applied.
A mask is applied to the pattern portion so that the pattern gap is 75 μm and the pattern gap is 75 μm, and the photosensitive resin resist layer 7 is patterned through a UV exposure and development process using a photo tool. The photosensitive resin resist layer 7 is laminated at 100 to 120 ° C. and a pressure of 3 to 5 kg / cm 2 , and the photo tool is vacuum degassed on both sides.
Exposure is carried out at 200 mJ / cm 2, and a phenomenon is carried out with 1 to 3% sodium carbonate for about 30 to 90 seconds.

【0018】次に図1(d)に示すように、露出してい
る銅めっき層5に無電解スズめっき層8を形成する。無
電解スズめっき層8は、Sn(BF42−(NH22
S−HBF4を含むスズめっき浴を用い、65℃,3時
間浸漬することにより、15μmの深さまで銅との置換
反応により形成する。
Next, as shown in FIG. 1D, an electroless tin plating layer 8 is formed on the exposed copper plating layer 5. Electroless tin plating layer 8, Sn (BF 4) 2 - (NH 2) 2 C
A tin plating bath containing S-HBF 4 is used, and it is formed by a substitution reaction with copper to a depth of 15 μm by immersion at 65 ° C. for 3 hours.

【0019】次に図2(e)に示すように、銅張り積層
板3を酸系剥離溶液(荏原電産社製)にて温度25℃で
1分間浸漬し、無電解スズめっき層8を剥離し、銅めっ
き層5の厚さを10μmに薄膜化する。その後、図2
(f)に示すように、露出し薄膜化された残存の銅めっ
き層5を塩化第二鉄溶液にて90秒エッチング除去す
る。このとき、残存する銅めっき層5の薄膜化された部
分の厚さは、当初の厚さ25μmに比べ15μmも少な
い10μmの厚さになるため、垂直方向のエッチングに
要する時間は90秒以内ですみ、同時に銅箔2の12μ
mと残存銅めっき層5の10μmとを合わせた銅層22
μmをエッチングするため、従来の37μmの銅層の厚
さのエッチングに比較して横方向のエッチング量は1/
2ですみ、パターン幅75μm,パターン間隙幅75μ
mの微細パターンが容易に形成される。また、レジスト
層7を除去する。
Next, as shown in FIG. 2 (e), the copper-clad laminate 3 is immersed in an acid-based stripping solution (made by Ebara Densan Co., Ltd.) at a temperature of 25 ° C. for 1 minute to form an electroless tin-plated layer 8. The copper plating layer 5 is peeled off to reduce the thickness of the copper plating layer 5 to 10 μm. After that, Figure 2
As shown in (f), the exposed and thinned residual copper plating layer 5 is removed by etching with a ferric chloride solution for 90 seconds. At this time, the thickness of the remaining thin portion of the copper plating layer 5 is 10 μm, which is 15 μm less than the initial thickness of 25 μm, so the time required for vertical etching is 90 seconds or less. At the same time, 12μ of copper foil 2
m and 10 μm of the remaining copper plating layer 5
Since the etching is performed in a thickness of .mu.m, the etching amount in the lateral direction is 1 / thick as compared with the conventional etching of a copper layer thickness of 37 .mu.m.
2 only, pattern width 75μm, pattern gap width 75μ
A fine pattern of m is easily formed. Further, the resist layer 7 is removed.

【0020】最後に図2(g)に示すように、スクリー
ン印刷でフォトソルダレジストを全面塗布し、フォトツ
ールを用いて紫外線露光後、1%炭酸ナトリウムで現像
し、130℃,45分により加熱硬化することでフォト
ソルダーレジスト層9を形成する。
Finally, as shown in FIG. 2 (g), a photo solder resist is applied on the entire surface by screen printing, exposed to ultraviolet rays using a photo tool, developed with 1% sodium carbonate, and heated at 130 ° C. for 45 minutes. The photo solder resist layer 9 is formed by curing.

【0021】(実施例2)図3,図4は本発明の実施例
2を工程順に示す断面図である。
(Embodiment 2) FIGS. 3 and 4 are sectional views showing Embodiment 2 of the present invention in the order of steps.

【0022】図3(a)に示すように、基板1の表裏面
に厚さ12μmの銅箔2を張り付けた銅張り積層板3
に、直径0.4mmの貫通孔4をドリルで穿設する。
As shown in FIG. 3A, a copper-clad laminate 3 in which a copper foil 2 having a thickness of 12 μm is adhered to the front and back surfaces of a substrate 1
Then, a through hole 4 having a diameter of 0.4 mm is drilled.

【0023】次に図3(b)に示すように貫通孔4を含
む銅張り積層板3全面に電解銅めっきを施し、25μm
厚の銅めっき層5を形成し、スルーホール6を形成す
る。次に図3(c)に示すように25μm厚の感光性レ
ジスト(ダイナケム社製ラミナーGAドライフィルム)
を被着し、スルーホール6部分及び、パターン幅75μ
m,パターン間隙75μmとなるようにパターン部にマ
スクを施し、フォトツールを用いて紫外線露光及び現像
工程を経て感光性樹脂レジスト層7をパターニングす
る。感光性樹脂レジスト層7は、100〜120℃,圧
力3〜5kg/cm2にてラミネートを行い、フォトツ
ールを両面に合わせ、真空脱気した後、紫外線約60〜
200mJ/cm2にて露光し、1〜3%炭酸ナトリウ
ムにて約30〜90秒現像を実施する。
Next, as shown in FIG. 3B, electrolytic copper plating is applied to the entire surface of the copper-clad laminate 3 including the through holes 4, and the thickness is 25 μm.
A thick copper plating layer 5 is formed and a through hole 6 is formed. Next, as shown in FIG. 3C, a photosensitive resist having a thickness of 25 μm (Laminar GA dry film manufactured by Dynachem).
And the through hole 6 part and pattern width 75μ
m, the pattern portion is masked to have a pattern gap of 75 μm, and the photosensitive resin resist layer 7 is patterned through a UV exposure and development process using a photo tool. The photosensitive resin resist layer 7 is laminated at 100 to 120 ° C. and a pressure of 3 to 5 kg / cm 2, and a photo tool is attached to both sides, vacuum deaeration is performed, and then ultraviolet rays of about 60 to
It is exposed at 200 mJ / cm 2 and developed with 1 to 3% sodium carbonate for about 30 to 90 seconds.

【0024】次に図3(d)に示すように、露出してい
る銅めっき層5に無電解はんだめっき層10を形成す
る。無電解はんだめっき層10は、無電解はんだめっき
浴(上村工業製ビームソルダーPC)を用い、70℃,
20分浸漬することにより、15μmの深さまで銅との
置換反応により形成する。
Next, as shown in FIG. 3D, an electroless solder plating layer 10 is formed on the exposed copper plating layer 5. The electroless solder plating layer 10 uses an electroless solder plating bath (beam solder PC manufactured by Uemura Kogyo) at 70 ° C.
It is formed by a substitution reaction with copper to a depth of 15 μm by immersion for 20 minutes.

【0025】次に図4(e)に示すように、図3(c)
と同様に25μm厚の感光性樹脂レジストを被着し、表
面実装用パッドを形成するようにマスクを施し、フォト
ツールを用いて紫外線露光及び現像工程を経て感光性樹
脂レジスト層7をパターニングする。感光性樹脂レジス
ト層7は図3(c)と同様に形成する。
Next, as shown in FIG. 4E, FIG.
Similarly, a photosensitive resin resist having a thickness of 25 μm is deposited, a mask is formed so as to form a surface mounting pad, and the photosensitive resin resist layer 7 is patterned through a UV exposure and development process using a photo tool. The photosensitive resin resist layer 7 is formed similarly to FIG.

【0026】その後、図4(f)に示すように、銅張り
積層板3を酸系剥離溶液(荏原電産社製)にて温度25
℃,1分間浸漬し、無電解はんだめっき層10を剥離
し、銅めっき層5の厚さを10μmに薄膜化する。
After that, as shown in FIG. 4 (f), the copper-clad laminate 3 was heated at a temperature of 25 with an acid-based stripping solution (made by Ebara Densan Co., Ltd.).
The electroless solder plating layer 10 is peeled off by immersing at 1 ° C. for 1 minute to reduce the thickness of the copper plating layer 5 to 10 μm.

【0027】その後、図4(g)に示すように、露出し
薄膜化された残存銅を塩化第二鉄溶液にて90秒エッチ
ング除去し、図2(f)と同様にパターン幅75μm,
パターン間隙幅75μmの微細パターンを形成する。ま
た、15μm厚さの無電解はんだめっき層を被着した表
面実装用パッド10を形成する。
Thereafter, as shown in FIG. 4 (g), the exposed and thinned residual copper is removed by etching with a ferric chloride solution for 90 seconds, and the pattern width is 75 μm, as in FIG. 2 (f).
A fine pattern having a pattern gap width of 75 μm is formed. Further, the surface-mounting pad 10 on which the electroless solder plating layer having a thickness of 15 μm is adhered is formed.

【0028】最後に図4(h)に示すように、パッド1
0を除いてスクリーン印刷でフォトソルダーレジストを
全面塗布し、フォトツールを用いて紫外線露光後、1%
炭酸ナトリウムで現像し、130℃,45分により加熱
硬化することで、フォトソルダーレジスト層9を形成す
る。
Finally, as shown in FIG. 4 (h), the pad 1
Except for 0, apply the photo solder resist on the entire surface by screen printing, and use a photo tool to expose it to ultraviolet rays and then 1%
The photo solder resist layer 9 is formed by developing with sodium carbonate and heating and curing at 130 ° C. for 45 minutes.

【0029】[0029]

【発明の効果】以上説明したように本発明は、無電解ス
ズ系めっきを銅と置換させ、それを剥離し、残存する薄
化した銅をエッチングすることにより、パターン75μ
m,パターン間隙75μmの微細パターンを、スルーホ
ールの信頼性を保ち、かつ銅箔の感光性を損わずに形成
することができる。
As described above, according to the present invention, the electroless tin-based plating is replaced with copper, the copper is peeled off, and the remaining thinned copper is etched.
It is possible to form a fine pattern having m and a pattern gap of 75 μm while maintaining the reliability of the through hole and without impairing the photosensitivity of the copper foil.

【0030】さらに実施例2によれば、選択的に無電解
はんだをパッド上に5〜20μm残すことで、実装工程
で必要なはんだを微細パッド上より供給可能となり、実
装工程におけるショート不良を1/10以下にすること
ができる。
Further, according to the second embodiment, by selectively leaving the electroless solder on the pad by 5 to 20 μm, the solder required in the mounting process can be supplied from the fine pad, and the short-circuit defect in the mounting process can be reduced to 1 It can be / 10 or less.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1を工程順に示す断面図であ
る。
FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.

【図2】本発明の実施例1を工程順に示す断面図であ
る。
FIG. 2 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

【図3】本発明の実施例2を工程順に示す断面図であ
る。
FIG. 3 is a cross-sectional view showing a second embodiment of the present invention in process order.

【図4】本発明の実施例2を工程順に示す断面図であ
る。
FIG. 4 is a cross-sectional view showing a second embodiment of the present invention in process order.

【図5】従来例に係る高密度パターンの製造方法を工程
順に示す断面図である。
FIG. 5 is a cross-sectional view showing a method of manufacturing a high-density pattern according to a conventional example in the order of steps.

【符号の説明】[Explanation of symbols]

1 基板 2 銅箔 3 銅張り積層板 4 貫通孔 5 銅めっき層 6 スルーホール 7 感光性レジスト 8 無電解スズめっき層 9 フォトソルダーレジスト 10 無電解はんだめっき層 11 EDレジスト層 1 substrate 2 copper foil 3 copper-clad laminate 4 through hole 5 copper plating layer 6 through hole 7 photosensitive resist 8 electroless tin plating layer 9 photo solder resist 10 electroless solder plating layer 11 ED resist layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 レジスト塗布工程と、めっき工程と、め
っき剥離工程と、微細パターン形成工程とを有するプリ
ント配線板の製造方法であって、 レジスト塗布工程は、基板上の銅層表面に感光性樹脂レ
ジストを選択的に塗布するものであり、 めっき工程は、感光性樹脂レジストが塗布されずに露出
している銅層表面に、銅との置換析出性を有する無電解
スズ系のめっきを施し、一定深さまでの銅層をスズ系金
属に置換するものであり、 めっき剥離工程は、前記スズ系金属を剥離,除去し、露
出している銅層を薄膜化するものであり、 微細パターン形成工程は、薄膜化された銅層をエッチン
グして除去し、微細パターンを形成するものであること
を特徴とするプリント配線板の製造方法。
1. A method for manufacturing a printed wiring board, comprising: a resist coating step, a plating step, a plating stripping step, and a fine pattern forming step, wherein the resist coating step is a photosensitive layer on the surface of a copper layer on a substrate. A resin resist is selectively applied.In the plating process, the surface of the copper layer that is exposed without the photosensitive resin resist being applied is subjected to electroless tin-based plating that has the property of precipitating substitution with copper. , The copper layer up to a certain depth is replaced with tin-based metal, and the plating stripping process strips and removes the tin-based metal and thins the exposed copper layer to form a fine pattern. The method is a method for producing a printed wiring board, wherein the thinned copper layer is etched and removed to form a fine pattern.
【請求項2】 第1のレジスト塗布工程と、めっき工程
と、第2のレジスト塗布工程と、めっき剥離工程と、微
細パターン形成工程と、レジスト剥離工程とを有するプ
リント配線板の製造方法であって、 第1のレジスト塗布工程は、基板上の銅層表面に感光性
樹脂レジストを選択的に塗布するものであり、 めっき工程は、感光性樹脂レジストが塗布されずに露出
している銅層表面に無電解はんだめっき層を形成した
後、無電解はんだめっき浴での浸漬処理により、一定深
さまでの銅層を無電解はんだに置換するものであり、 第2のレジスト塗布工程は、無電解はんだに置換された
領域に感光性樹脂レジストを選択的に塗布して、表面実
装用パッドのパターンを形成するものであり、 めっき剥離工程は、感光性樹脂レジストが塗布されずに
露出している無電解はんだを剥離,除去し、感光性樹脂
レジストでマスクされていない銅層を薄膜化するもので
あり、 微細パターン形成工程は、薄膜化された銅層をエッチン
グして除去し、微細パターンを形成するものであり、 レジスト剥離工程は、残存している感光性樹脂レジスト
を剥離,除去するものであることを特徴とするプリント
配線板の製造方法。
2. A method of manufacturing a printed wiring board comprising a first resist coating step, a plating step, a second resist coating step, a plating stripping step, a fine pattern forming step, and a resist stripping step. The first resist coating step selectively coats the photosensitive resin resist on the surface of the copper layer on the substrate, and the plating step exposes the copper layer exposed without being coated with the photosensitive resin resist. After the electroless solder plating layer is formed on the surface, the copper layer up to a certain depth is replaced with the electroless solder by immersion treatment in the electroless solder plating bath. The surface of the pads for surface mounting is formed by selectively applying a photosensitive resin resist to the areas replaced with solder.In the plating peeling process, the photosensitive resin resist is not applied and exposed. The copper layer not masked by the photosensitive resin resist is thinned by removing and removing the electroless solder that is being used. In the fine pattern forming step, the thinned copper layer is removed by etching. A method for manufacturing a printed wiring board, wherein a fine pattern is formed, and the resist stripping step strips and removes the remaining photosensitive resin resist.
JP32083792A 1992-11-30 1992-11-30 Method for manufacturing printed wiring board Expired - Lifetime JPH0738497B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32083792A JPH0738497B2 (en) 1992-11-30 1992-11-30 Method for manufacturing printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32083792A JPH0738497B2 (en) 1992-11-30 1992-11-30 Method for manufacturing printed wiring board

Publications (2)

Publication Number Publication Date
JPH06169144A true JPH06169144A (en) 1994-06-14
JPH0738497B2 JPH0738497B2 (en) 1995-04-26

Family

ID=18125797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32083792A Expired - Lifetime JPH0738497B2 (en) 1992-11-30 1992-11-30 Method for manufacturing printed wiring board

Country Status (1)

Country Link
JP (1) JPH0738497B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113766747A (en) * 2021-09-14 2021-12-07 江西景旺精密电路有限公司 PCB (printed Circuit Board) micro-etching process for fine circuit and circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113766747A (en) * 2021-09-14 2021-12-07 江西景旺精密电路有限公司 PCB (printed Circuit Board) micro-etching process for fine circuit and circuit board

Also Published As

Publication number Publication date
JPH0738497B2 (en) 1995-04-26

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