JPH08147970A - Dram controller - Google Patents

Abstract

PURPOSE: To minimize the performance lowering in a DRAM controller system caused by refreshment of a DRAM. CONSTITUTION: By access from a CPU 1 to a DRAM controller 8, upper/lower limit values of a row address related to the use area of the DRAM 7 are stored in an upper limit register 9 and a lower limit register 10. A refreshment request signal generation circuit 21 generates a refreshment request signal RR at frequency proportional to the difference between the row address upper/lower limit values calculated by a subtractor 11. A bus arbiter 5 gains the use right of a bus according to the refreshment request signal RR, and generates a refreshment start signal RI. A control signal generation circuit 4 sends a row address strobe signal RAS and a count up signal UP whenever receiving the refreshment start signal RI. A refreshment address renewal circuit 22 provided with a refreshment address counter 3 and a comparator 14 updates a refreshment address between the upper limit value and the lower limit value of the row address in response to the count up signal UP.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM controller used in a system using a DRAM (dynamic random access memory).

[0002]

2. Description of the Related Art Since a DRAM uses a capacitor as a memory element, it is necessary to perform refresh before rewriting the stored information before the charge in the capacitor is lost by the leakage current.

FIG. 5 is a block diagram showing a typical structure of a conventional DRAM controller that controls the refresh control of the DRAM. In FIG. 5, CPU 1 and DRAM 7
The DRAM controller 8 interposed between the address controller 2 and the refresh address counter 3
A control signal generating circuit 4, a bus arbiter 5, and a refresh timer 6.

The operation at the time of refreshing the conventional DRAM controller 8 configured as above will be described.

The DRAM controller 8 of FIG.
The DRAM 7 is refreshed by the only refresh method. The refresh timer 6 generates a refresh request signal RR to the bus arbiter 5 at regular intervals. Assuming that the refresh cycle is 2.048 ms and the DRAM 7 has a structure of 128 rows, the refresh timer 6 is 2.048 ms / 128 =
The refresh request signal RR is generated once every 16 μs.

The bus arbiter 5 generates a bus request signal BR to the CPU 1 in order to acquire the right to use the bus in response to the refresh request signal RR and receives the bus use permission signal BG from the CPU 1 to indicate that the bus is in use. At the same time as returning the bus acknowledge signal BACK shown to the CPU 1, the refresh start signal RI is sent to the control signal generating circuit 4.

Upon receiving the refresh activation signal RI, the control signal generation circuit 4 generates a row address strobe signal RAS necessary for refreshing the DRAM 7, and at the same time, outputs a refresh address select signal SEL to the address multiplexer 2 and a refresh address counter 3 The count-up signal UP is sent to the. On the other hand, the refresh address counter 3 includes a control signal generation circuit 4
In response to the count-up signal UP from, the refresh address is sent to the address multiplexer 2 and the count value is incremented. The address multiplexer 2 sends the refresh address from the refresh address counter 3 to the DRAM 7 instead of the address (row address) from the CPU 1 in response to the refresh address select signal SEL from the control signal generation circuit 4.

Assuming that the DRAM 7 has a structure of 128 rows, a 7-bit counter is adopted as the refresh address counter 3, and its count value (hexadecimal display) is 00 after 7F. That is, the refresh address supplied to the DRAM 7 specifies the entire area of the DRAM 7.

[0009]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the configuration of the RAM controller 8, the entire area of the DRAM 7 is refreshed, so that the area that is not actually used is refreshed. In other words, the CPU 1 passes the bus use right to the DRAM controller 8 for useless refresh,
There was a problem that the system performance deteriorated.

It is an object of the present invention to minimize DRA system performance degradation due to DRAM refresh.
To provide an M controller.

[0011]

In order to achieve the above object, the present invention enables a DRAM controller to refresh only a required area in a DRAM.

More specifically, the invention of claim 1 is as follows.
As illustrated in FIGS. 1 to 4, an upper limit register 9 for storing an upper limit value of a row address, a lower limit register 10 for storing a lower limit value of a row address, and a row address stored in the upper limit register 9. Of the row address stored in the lower limit register 10 and the subtracter 11 for calculating the difference between the lower limit value of the row address stored in the lower limit register 10, and refreshing at a frequency according to the difference between the upper and lower limit values of the row address calculated by the subtractor 11. Request signal RR
Refresh request signal generation circuit 21 for generating
A control signal generating circuit 4 for generating a row address strobe signal RAS necessary for refreshing the DRAM 7 in response to the refresh request signal RR; and a row address stored in the upper limit register 9 in response to the refresh request signal RR. The configuration is provided with a refresh address update circuit 22 for updating the refresh address necessary for refreshing the DRAM 7 within the range of the upper limit value and the lower limit value of the row address stored in the lower limit register 10.

In the second aspect of the invention, the refresh request signal generating circuit 21 counts clock signals and refresh request signal RR as shown in FIGS.
The refresh timer 6 which is cleared in step 1, the divider 12 for calculating the quotient obtained by dividing the overflow value of the refresh timer 6 by the difference between the row address upper and lower limit values calculated by the subtractor 11, and the count of the refresh timer 6. Comparator 13 for generating a refresh request signal RR when the value equals the quotient calculated by the divider 12.
And decided to prepare.

According to the third aspect of the invention, the refresh request signal generating circuit 21 is provided with D as shown in FIGS.
A divider 12 for calculating a quotient obtained by dividing the number of all row addresses in the RAM 7 by the difference between the row address upper and lower limit values calculated by the subtractor 11, and a frequency division corresponding to the quotient calculated by the divider 12. Divider 15 for dividing the clock signal by the ratio
And a refresh timer 6 for counting the clock signals divided by the frequency divider 15 and generating a refresh request signal RR when overflowing.

According to a fourth aspect of the invention, the refresh address updating circuit 22 increments the count value used as a refresh address and generates the load signal LD each time the refresh request signal RR is generated, as shown in FIGS. Is given, the lower limit register 10
The refresh address counter 3 to which the lower limit value of the row address stored in is loaded, and the load signal L when the count value of the refresh address counter 3 becomes equal to the upper limit value of the row address stored in the upper limit register 9.
And a comparator 14 for generating D.

According to a fifth aspect of the present invention, the refresh address updating circuit 22 is a modification of the configuration shown in FIGS.
Each time the refresh request signal RR is generated, the count value used as the refresh address is decremented, and when the load signal LD is applied, the upper limit register 9
The refresh address counter 3 to which the upper limit value of the row address stored in is loaded, and the load signal LD when the count value of the refresh address counter 3 becomes equal to the lower limit value of the row address stored in the lower limit register 10. And a comparator 14 for generating.

In the invention of claim 6, the upper limit register 9
And the lower limit register 10, as shown in FIG. 1 and FIG.
It is assumed that the settings are made before the access to the DRAM 7 is started by means such as the CPU 1.

According to a seventh aspect of the present invention, as shown in FIGS. 3 and 4, the upper limit register 9 is set in accordance with a row address given by means such as the CPU 1 during access of the DRAM 7.
And a register update control circuit 23 for controlling the update of the lower limit register 10.

In the eighth aspect of the present invention, the register update control circuit 23, as shown in FIGS.
DR when the row address to access M7 is given
The address decoder 16 for generating the AM access signal ACC, and the given row address by comparing the given row address with the upper limit value of the row address stored in the upper limit register 9 when the DRAM access signal ACC is generated. Is greater than the upper limit value of the row address stored in the upper limit register 9, first means 17 and 19 for loading the given row address into the upper limit register 9;
Lower limit register 1 when DRAM access signal ACC is generated
When the given row address is smaller than the lower limit value of the row address stored in the lower limit register 10, the lower limit value of the row address stored in 0 is compared with the given row address. And second means 18, 20 for loading the assigned row address.

[0020]

According to the present invention, the refresh address supplied to the DRAM 7 is required to be between the upper limit value of the row address stored in the upper limit register 9 and the lower limit value of the row address stored in the lower limit register 10. Limited to the area. In response to this, when the difference between the upper and lower limit values calculated from the upper and lower limit values of the row address stored in the upper limit register 9 and the lower limit register 10 is large, the refresh request signal RR and the row address strobe signal RAS are high in frequency. Occurs in
When the difference between the upper and lower limit values of the row address is small, the refresh request signal RR and the row address strobe signal RAS are generated at a low frequency in a required refresh cycle. Therefore, the C trying to access the DRAM 7
From the perspective of PU1, the bus release time at the time of refresh is reduced, and the system performance is improved.

According to the inventions of claims 2 and 3, the difference between the upper and lower limit values calculated from the upper and lower limit values of the row address stored in the upper limit register 9 and the lower limit register 10 is realized while realizing the required refresh cycle. The refresh request signal RR is generated at a proportional frequency.

According to the fourth and fifth aspects of the present invention, by using the increment counter or the decrement counter, the upper limit value of the row address stored in the upper limit register 9 and the lower limit value of the row address stored in the lower limit register 10 are set. Refresh addresses are limited in the meantime.

According to the sixth aspect of the invention, before the access to the DRAM 7 is started, for example, the set values are given from the CPU 1 to the upper limit register 9 and the lower limit register 10 through the data bus.

According to the inventions of claims 7 and 8, for example, C
By monitoring the address sent from PU1 to the address bus, the used area of DRAM 7 is automatically recognized, and the settings of upper limit register 9 and lower limit register 10 are updated according to the recognition result.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a first embodiment of the present invention. In FIG. 1, CPU1 and DR
The DRAM controller 8 interposed between the AM 7 and the AM 7, in addition to the address multiplexer 2, the refresh address counter 3, the control signal generation circuit 4, the bus arbiter 5, and the refresh timer 6, a row address upper limit value storage register (upper limit register) 9, Row address lower limit value storage register (lower limit register) 10, subtractor 11, and divider 12
And two comparators 13 and 14. Of these, the refresh timer 6, the divider 12, and the comparator 13
Constitutes a refresh request signal generation circuit 21 for generating a refresh request signal RR at a frequency according to the difference between the row address upper and lower limit values calculated by the subtractor 11. Further, the refresh address counter 3 and the comparator 14 configure a refresh address updating circuit 22 for updating the refresh address between the upper limit value and the lower limit value of the row address.

The R according to the present embodiment configured as described above
The operation of the AS-only refresh type DRAM controller 8 at the time of refresh will be described.

The upper limit register 9 and the lower limit register 10 are
Before starting access to the DRAM 7, C via the data bus
By accessing the DRAM controller 8 from the PU 1, the row address upper limit value and the row address lower limit value of the used area of the DRAM 7 are stored respectively. The subtractor 11 calculates a difference D between the row address upper limit value and the row address lower limit value stored in the upper limit register 9 and the lower limit register 10.

In the refresh request signal generation circuit 21, the refresh timer 6 counts up by the clock signal, and the refresh request signal R from the comparator 13 is counted.
It is cleared when R is output. The divider 12 calculates the quotient when the overflow value of the refresh timer 6 is divided by the difference D between the row address upper and lower limits, and sends the calculated quotient to the comparator 13. Comparator 13 generates refresh request signal RR when the quotient given from divider 12 and the count value of refresh timer 6 become equal. Refresh cycle is 2.048ms, DRA
Assuming that M7 has a structure of 128 rows, the difference D between the row address upper and lower limit values indicates the entire area of the DRAM 7 128.
Then, the refresh timer 6 generates the refresh request signal RR once every 16 μs, as in the conventional example (see FIG. 5). However, if the difference D between the upper and lower limit values of the row address is 64, the refresh timer 6 is set to 32 μs.
The refresh request signal RR is generated only once every time, and the frequency of occurrence is halved.

The bus arbiter 5 generates a bus request signal BR to the CPU 1 in order to acquire the right to use the bus in response to the refresh request signal RR from the comparator 13, and C
When the bus use permission signal BG is received from PU1, the bus acknowledge signal BACK indicating that the bus is in use is returned to the CPU 1, and at the same time, the refresh start signal RI is sent to the control signal generation circuit 4.

When the control signal generation circuit 4 receives the refresh activation signal RI, it generates a row address strobe signal RAS necessary for refreshing the DRAM 7, and at the same time, a refresh address select signal SEL to the address multiplexer 2 and a refresh address counter 3 are generated. The count-up signal UP is sent to the.

On the other hand, the refresh address updating circuit 22
At, the refresh address counter 3 receives the count-up signal UP from the control signal generation circuit 4,
The refresh address necessary for refreshing the DRAM 7 is sent to the address multiplexer 2 and the count value is incremented. When the count value of the refresh address counter 3 becomes equal to the row address upper limit value stored in the upper limit register 9, the comparator 1
4, the load signal LD is generated, and the row address lower limit value stored in the lower limit register 10 is loaded into the refresh address counter 3.

The address multiplexer 2 receives the refresh address select signal SE from the control signal generating circuit 4.
In response to L, not the address (row address) from the CPU 1 but the refresh address from the refresh address counter 3 is sent to the DRAM 7.

As described above, according to this embodiment, the DRA
The range of refresh address supplied to M7 is CPU
It is restricted according to the designation from 1. In response to this, D
A refresh request signal RR and a row address strobe signal R while realizing a required refresh cycle of the RAM 7
The occurrence frequency of AS can be reduced. Therefore, the DRAM 7
The bus release time of the CPU 1 due to the refresh is reduced, and the system performance is improved. That is, DRAM
Since only the 7 designated areas can be refreshed, useless refresh cycles can be reduced, and deterioration of system performance due to refresh can be minimized. When it becomes necessary to enlarge or reduce the use area of the DRAM 7, the CPU 1 may change the settings of the upper limit register 9 and the lower limit register 10 before starting access to the DRAM 7 each time.

(Embodiment 2) FIG. 2 is a block diagram of a second embodiment of the present invention. The configuration of FIG. 2 is obtained by changing only the internal configuration of the refresh request signal generating circuit 21 in the first embodiment (see FIG. 1). The refresh request signal generation circuit 21 of FIG.
It includes a divider 12 and a frequency divider 15.

The refresh request signal generation circuit 21 of FIG.
In, the divider 12 calculates the quotient when the number of all the row addresses of the DRAM 7 is divided by the difference D between the row address upper and lower limits, and sends the calculated quotient to the frequency divider 15. Frequency divider 15
Divides the clock signal by using the quotient given from the divider 12 as the reciprocal of the division ratio, and sends the divided clock signal to the refresh timer 6. Refresh timer 6
Counts up with the clock signal from the frequency divider 15 and generates a refresh request signal RR when it overflows.

Assuming that the refresh cycle is 2.048 ms and the DRAM 7 has a structure of 128 rows,
If the difference D between the upper and lower limit values of the row address is 128 indicating the entire area of the DRAM 7, the frequency division ratio in the frequency divider 15 becomes 1, so that the refresh timer 6 is 16 μs as in the conventional example (see FIG. 5). The refresh request signal RR is generated once every time. However, if the difference D between the upper and lower limit values of the row address is 64, the frequency division ratio in the frequency divider 15 is 1 /.
As a result, the refresh timer 6 generates the refresh request signal RR only once every 32 μs, and the frequency of occurrence thereof is halved. From the above, according to this embodiment, the same effect as that of the first embodiment can be obtained.

(Embodiment 3) FIG. 3 is a block diagram of a third embodiment of the present invention. The configuration of FIG. 3 is obtained by adding a register update control circuit 23 for automatically updating the upper limit register 9 and the lower limit register 10 to the configuration of the first embodiment (see FIG. 1). The register update control circuit 23 includes an address decoder 16, two subtractors 17 and 18, and two AND gates 19 and 20. In this embodiment, the upper limit register 9 and the lower limit register 10 are not given the upper and lower limit values of the row address through the data bus in advance from the CPU 1, but the upper limit register 9 is the CPU when the enable signal EN1 is given during the access of the DRAM 7.
The address from 1 is stored as the row address upper limit value, and the lower limit register 10 stores the address from the CPU 1 as the row address lower limit value when the enable signal EN2 is applied during the access of the DRAM 7.

In the register update control circuit 23, the address decoder 16 asserts the DRAM access signal ACC when the address (row address) in the range assigned to the DRAM 7 is supplied from the CPU 1. That is, the DRAM access signal ACC is a signal that is asserted when the DRAM 7 is actually accessed for reading or writing. The subtractor 17 and the AND gate 19 are provided for updating control of the upper limit register 9, and the subtracter 18 and the AND gate 20 are provided for controlling update of the lower limit register 10.

More specifically, the subtractor 17 compares the row address upper limit value stored in the upper limit register 9 with the address from the CPU 1, and asserts the upper limit value update request signal U1 when the latter is larger. To do. AND gate 19
Generates an enable signal EN1 from the DRAM access signal ACC and the upper limit value update request signal U1. That is, when the CPU 1 accesses the DRAM 7,
When the row address related to the access is larger than the value stored in the upper limit register 9, the new upper limit value is automatically stored in the upper limit register 9.

Similarly, the subtractor 18 includes a lower limit register 10
The lower limit value of the row address stored in is compared with the address from the CPU 1, and when the latter is smaller, the lower limit value update request signal U2 is asserted. AND gate 20 is DRA
An enable signal EN2 is generated from the M access signal ACC and the lower limit value update request signal U2. That is, DRAM
When the CPU 1 accesses 7, the new lower limit value is automatically stored in the lower limit register 10 when the row address related to the access is smaller than the value stored in the lower limit register 10.

The range of the refresh address supplied to the DRAM 7 is limited based on the upper and lower limit values of the row address stored in the upper limit register 9 and the lower limit register 10, and the refresh request signal RR and the row address strobe signal RAS are generated. The frequency is reduced as in the first embodiment (see FIG. 1). Therefore, according to the present embodiment, in addition to the effects of the first embodiment, the DRAM controller 8 automatically recognizes the used area of the DRAM 7 and only that area can be refreshed. That is, it is advantageous that the CPU 1 does not have to specify the range of the refresh address of the DRAM 7.

(Embodiment 4) FIG. 4 is a block diagram of a fourth embodiment of the present invention. The configuration of FIG. 4 is similar to that of the third embodiment (see FIG. 3) for automatically updating the upper limit register 9 and the lower limit register 10 in the configuration of the second embodiment (see FIG. 2). Is added.

Since the operation of this embodiment is clear from the description of the second and third embodiments, its detailed description will be omitted. Also in this embodiment, the same effect as that of the third embodiment can be obtained.

Although the refresh address counter 3 is an increment counter in each of the above embodiments, it may be replaced with a decrement counter. In this case, when the control signal generation circuit 4 receives the refresh activation signal RI, it sends a countdown signal to the refresh address counter 3. The count value of the refresh address counter 3 is the lower limit register 1
When it becomes equal to the row address lower limit value stored in 0,
The load signal LD is generated by the comparator 14, and the row address upper limit value stored in the upper limit register 9 is loaded into the refresh address counter 3.

Although the above-described embodiments are examples of the RAS only refresh system, the row address strobe signal RAS and the column address strobe signal CAS are DRA.
If it is necessary for refreshing M7, the RAS, C
Needless to say, the present invention can be applied when the control signal generating circuit 4 generates both AS signals.

[0047]

As described above, claims 1 to 8
According to the invention, since the unused area in the DRAM does not need to be refreshed, only the used area of the DRAM can be refreshed. Therefore, a system in which the performance deterioration caused by the refresh of the DRAM is minimized. Can be realized. Particularly, according to the inventions of claims 7 and 8, DR
Since the DRAM controller automatically recognizes the AM use area, it is advantageous in that the CPU does not have to specify the area.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a DRAM controller according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a DRAM controller according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a DRAM controller according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a DRAM controller according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional DRAM controller.

[Explanation of symbols]

 1 CPU 2 Address Multiplexer 3 Refresh Address Counter 4 Control Signal Generation Circuit 5 Bus Arbiter 6 Refresh Timer 7 DRAM 8 DRAM Controller 9 Row Address Upper Limit Value Storage Register (Upper Limit Register) 10 Row Address Lower Limit Value Storage Register (Lower Limit Register) 11 Subtractor 12 Divider 13,14 Comparator 15 Divider 16 Address decoder 17,18 Subtractor 19,20 AND gate 21 Refresh request signal generation circuit 22 Refresh address update circuit 23 Register update control circuit ACC DRAM access signal BACK bus Acknowledge signal BG bus Use enable signal BR bus request signal EN1, EN2 enable signal LD load signal RAS row address strobe signal RI refresh start signal RR refref Gerhard request signal SEL refresh address select signal UP count up signal U1 upper limit value update request signal U2 lower limit value update request signal

Claims (8)

[Claims] 1. A DRAM controller for refreshing only a required area in a DRAM, comprising an upper limit register for storing an upper limit value of a row address and a lower limit register for storing a lower limit value of a row address. A subtracter for calculating a difference between an upper limit value of the row address stored in the upper limit register and a lower limit value of the row address stored in the lower limit register; and a row address upper and lower limit value calculated by the subtractor A refresh request signal generating circuit for generating a refresh request signal at a frequency according to the difference between the two, and a control signal generating circuit for generating a row address strobe signal necessary for refreshing the DRAM in response to the refresh request signal. The upper limit value and the previous value of the row address stored in the upper limit register in response to the refresh request signal, A DRAM controller comprising: a refresh address updating circuit for updating a refresh address necessary for refreshing the DRAM within a range of a lower limit value of a row address stored in the lower limit register. 2. The DRAM controller according to claim 1, wherein the refresh request signal generation circuit counts a clock signal and is cleared by the refresh request signal, and the overflow value of the refresh timer is subtracted from the refresh timer. And a refresh request signal when the count value of the refresh timer is equal to the quotient calculated by the divider. And a comparator for generating the. 3. The DRAM controller according to claim 1, wherein the refresh request signal generation circuit divides the number of all row addresses of the DRAM by the difference between the row address upper and lower limit values calculated by the subtractor. A divider for calculating, a divider for dividing the clock signal by a dividing ratio according to the quotient calculated by the divider, and counting the clock signal divided by the divider. And a refresh timer for generating the refresh request signal when it overflows. 4. D according to any one of claims 1 to 3.
In the RAM controller, the refresh address update circuit increments a count value used as the refresh address each time the refresh request signal is generated, and when a load signal is applied, a lower limit of the row address stored in the lower limit register. A refresh address counter to which a value is loaded; and a comparator for generating the load signal when the count value of the refresh address counter becomes equal to the upper limit value of the row address stored in the upper limit register. A DRAM controller characterized in that. 5. D according to any one of claims 1 to 3.
In the RAM controller, the refresh address update circuit decrements a count value used as the refresh address each time the refresh request signal is generated, and when a load signal is applied, the upper limit of the row address stored in the upper limit register is given. A refresh address counter to which a value is loaded; and a comparator for generating the load signal when the count value of the refresh address counter becomes equal to the lower limit value of the row address stored in the lower limit register. A DRAM controller characterized in that. 6. D according to any one of claims 1 to 5.
In the RAM controller, the upper limit register and the lower limit register are respectively set before starting access to the DRAM. 7. D according to any one of claims 1 to 5.
The DRAM controller further comprises a register update control circuit for controlling updating of the upper limit register and the lower limit register according to a row address given during access of the DRAM. 8. The DRAM controller according to claim 7, wherein the register update control circuit includes an address decoder for generating a DRAM access signal when a row address for accessing the DRAM is given, and the DRAM access signal. Is generated, the upper limit value of the row address stored in the upper limit register is compared with the given row address, and when the given row address is larger than the upper limit value of the row address stored in the upper limit register, the upper limit First means for loading the given row address into a register, comparing the lower limit value of the row address stored in the lower limit register with the given row address when the DRAM access signal is generated, and The given row address is lower than the lower limit value of the row address stored in the lower limit register. DRAM controller when again, characterized in that a second means for loading a row address given above to the lower limit register.