JP2007219998A - Storage control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage control device that can efficiently reduce power consumption necessary for refreshing in accordance with the use status of a semiconductor storage device. <P>SOLUTION: In data writing and reading control on a DRAM 30, use status information representing the use status of the storage area of the DRAM 30 is stored and updated in a register 22, and according to the use status information stored and updated in the register 22, used areas 30A and 30C are refreshed at predetermined refresh periods to hold the storage state. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a storage control device that controls writing and reading of data to and from a semiconductor memory device that requires a refresh operation for holding stored contents.

  A semiconductor storage device, for example, a DRAM (Dynamic Random Access Memory) is configured by a large number of capacitor units, and stores data by varying the amount of charge accumulated in each capacitor unit according to the data.

  In an information processing apparatus having a DRAM as a memory, in order to prevent loss of memory due to spontaneous discharge of the capacitor part constituting the DRAM, the storage controller periodically charges the capacitor part for the purpose of holding data. A refresh to charge is being executed.

  Since this refresh operation is normally performed for every capacitor section of all DRAMs equipped in the apparatus at a predetermined refresh cycle, increasing the storage capacity of the DRAM also increases the power consumption by the refresh operation. Resulting in.

  In recent years, with the power saving of electronic devices, it is required to reduce power consumption in information processing apparatuses. On the other hand, the storage capacity of DRAM tends to increase as the performance of electronic devices increases.

  Therefore, conventionally, when a memory access is made to the DRAM, the memory access address is recorded, and when refreshing the DRAM, if there is a memory access record for the address to be refreshed, It has been proposed to clear the memory access record and set the next address as a refresh target (see, for example, Patent Document 1).

  That is, in Patent Document 1, power consumption for refresh is reduced by omitting refresh for an address that has been accessed.

Conventionally, a memory array composed of a volatile memory is divided into N partial memory arrays, and the partial memory array is refreshed one by one in one refresh operation, so that the maximum power consumption during refresh is increased. It has been proposed to reduce the power consumption of the entire storage device (see, for example, Patent Document 2).
JP-A-8-31170 JP-A-5-135578

  However, in the above-described conventional technology, refresh is performed even in an area where refresh is not required regardless of the use state of the DRAM, and if the storage capacity of the DRAM in the entire device increases, it is inevitable that the power consumption increases. There was a problem.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a storage control device that can efficiently reduce power consumption required for refresh according to the use state of a semiconductor storage device.

  In order to solve the above-mentioned problem, the invention described in claim 1 is a storage control device that controls writing and reading of data to and from a semiconductor memory device, and usage status information indicating a usage status of a storage area of the semiconductor memory device. A storage unit that updates and stores the data, and a refresh that executes a refresh operation for maintaining the storage state at a predetermined refresh cycle for the storage area being used based on the usage status information stored in the storage unit Operation execution control means.

  According to the first aspect of the present invention, when controlling the writing and reading of data to and from the semiconductor memory device, the usage status information indicating the usage status of the storage area of the semiconductor memory device is updated and stored in the storage means, and the usage status Based on the information, the refresh operation for holding the storage state is executed at a predetermined refresh cycle for the storage area being used, so that the refresh operation can be performed according to the usage status of the semiconductor memory device. By reducing the target storage area, the power consumption required for refresh can be efficiently reduced.

  That is, since it is not necessary to maintain the storage state of the unused area, it is not necessary to perform the refresh operation for the unused area.

  Further, according to the present invention, as in the second aspect of the present invention, an address of the used storage area may be applied as the usage status information.

  The usage status information includes, in addition to the address of the storage area being used, information associated with the information stored in the semiconductor memory device and the storage area, the address of the non-use area, and the like.

  As described above, according to the present invention, when controlling the writing and reading of data to and from the semiconductor memory device, the usage status information indicating the usage status of the storage area of the semiconductor memory device is updated and stored in the storage means. Based on this, the refresh operation for maintaining the storage state is executed at a predetermined refresh cycle for the storage area being used, so the power consumption required for refresh can be efficiently reduced according to the usage status of the semiconductor memory device. It has the excellent effect of being able to.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, FIG. 1 is a schematic diagram showing a configuration of the information storage device 10 according to the present embodiment. Hereinafter, a schematic configuration of the information storage device 10 will be described.

  The information storage device 10 is incorporated in an information processing device and used as storage means.

  As shown in the figure, the information storage device 10 includes a DRAM controller 20 and a DRAM. The DRAM 30 is connected to the DRAM controller 20, and the DRAM controller 20 performs processing such as data writing, reading, and erasing.

  The DRAM controller 20 controls access to the DRAM 30 in response to a request signal from each part (hereinafter referred to as “external”) of the device in which the information storage device 10 is incorporated. As the request signal, a signal indicated by a data storage instruction, a data read instruction, a data erase instruction, or the like is input.

  Here, the storage area of the DRAM 30 is constituted by a large number of capacitor units, and data is stored by controlling the accumulation of electric charges in each capacitor unit. Each capacitor unit is given a unique address, and the DRAM controller 20 specifies the capacitor unit to be accessed using the address, and executes data writing, reading, erasing, and the like. . In the access using this address, bank switching or the like can be used as appropriate.

  In addition, the DRAM controller 20 charges the capacitor portion constituting the storage area of the DRAM 30 with a predetermined refresh cycle based on a time-up signal based on a time not shown by a timer (not shown) or a clock signal input from the outside. The refresh operation is executed at a predetermined refresh cycle.

  By the way, in the present embodiment, a storage area (hereinafter referred to as “refresh area”) to be refreshed is determined according to the usage state of the DRAM 30.

  That is, by repeatedly writing and erasing data by the DRAM controller 20, the use areas 30 </ b> A and 30 </ b> C and the non-use areas 30 </ b> B and 30 </ b> D are mixed in the storage area of the DRAM 30.

  Therefore, the DRAM controller 20 includes a register 22 and stores an address indicating a used area in the register 22 as usage status information. As a result, the DRAM controller 20 performs a refresh operation for the used area stored in the register 22.

  The address indicating the used area stored in the register 22 is updated and stored every time data is written to and erased from the DRAM 30.

  Hereinafter, the operation of the present embodiment will be described.

  The DRAM controller 20 executes main processing when a request signal is input from the outside.

  FIG. 2 is a flowchart showing a flow of main processing executed by the DRAM controller 20, and the main processing according to the present embodiment will be described below with reference to FIG.

  First, in step 200, it is determined whether or not the input request signal indicates a data storage instruction. If the determination is affirmative, the process proceeds to step 202, and the input data is stored in the DRAM 30. Remember. Thereafter, the process proceeds to the next step 204, and after adding the storage destination address to the register, the main process is terminated.

  On the other hand, if a negative determination is made in step 200, the process proceeds to step 206 to determine whether or not the input request signal indicates a data erasure instruction. If the determination is affirmative, step 208 is performed. Migrate to

  In step 208, the storage destination address of the data to be erased is released, and then the process proceeds to step 210. In step 210, the storage address of the erased data is deleted from the register 22, and then the main process is terminated.

  On the other hand, if the determination in step 206 is negative, it is determined that the input request signal indicates a data read instruction, and the process proceeds to step 212 to start from the storage destination address of the data to be read. Data is read and output, and then the main process is terminated.

  In addition, the DRAM controller 20 executes a refresh operation process at a predetermined refresh cycle.

  FIG. 3 is a flowchart showing a flow of a refresh operation process executed by the DRAM controller 20 when a request signal is input from the outside. Hereinafter, with reference to FIG. 3, the refresh operation process according to the present embodiment will be described. Will be described.

  First, in step 220, the refresh area is determined by referring to the register 22, and in the next step 222, the refresh operation is executed by designating the determined refresh area, and then the refresh process is terminated.

  As described above in detail, according to the present embodiment, when controlling the writing and reading of data to / from the DRAM 30, the usage status information indicating the usage status of the storage area of the DRAM 30 is updated and stored in the register 22, and Based on the usage status information updated and stored in the register 22, the refresh operation for holding the storage state is executed for the usage areas 30 </ b> A and 30 </ b> C at a predetermined refresh cycle, so that the refresh is performed according to the usage status of the DRAM 30. Can be efficiently reduced.

(Other forms)
In place of the DRAM 30 of the above embodiment, a first-in first-out buffer (FIFO) DRAM 70 (see FIG. 4) used as a ring buffer may be applied. In this case, since the same configuration can be applied to the configuration of the information storage device 10 and the flow of the refresh operation process, illustration and description thereof are omitted here.

  As shown in FIG. 4, the DRAM 70 sequentially stores input data in a buffer of a predetermined storage capacity unit, and outputs it in the input order. Of the buffers storing data, the FIFO buffer area existing between the output pointer P1 indicating the buffer storing data first and the input pointer P2 indicating the buffer storing data most recently is used area It becomes. Each time the output process is executed, the output pointer P1 is sequentially moved to the next buffer, and every time the storage process is executed, the input pointer P2 is sequentially moved to the next buffer. Become.

  FIG. 5 is a flowchart showing the flow of the main process executed by the DRAM controller 20, and the main process according to the other embodiment will be described below with reference to FIG.

  First, in step 300, it is determined whether or not the input request signal indicates a data storage instruction. If the determination is affirmative, the process proceeds to step 302.

  In step 302, after the input pointer P2 is moved to the next buffer, the process proceeds to step 304. In step 304, the input data is stored in the buffer indicated by the input pointer P2, and then the process proceeds to step 310.

  On the other hand, if a negative determination is made in step 300, the process proceeds to step 306, where the buffer data indicated by the output pointer P1 is read and output to the outside, and then the process proceeds to step 308. In step 308, the output pointer is moved to the next buffer to change the FIFO buffer area, and then the process proceeds to step 310.

  In step 310, the FIFO buffer area changed by data storage or output is stored in the register 22 as a use area, and then the main process is terminated.

  As a result, in the refresh operation processing (see FIG. 3) executed by the DRAM controller 20 at a predetermined refresh cycle, only the FIFO buffer area is targeted, and the refresh operation for the unused area is not executed. The power consumption can be easily reduced without changing the hardware configuration.

  The configuration of the information storage device 10 according to the above embodiment (see FIG. 1) is merely an example, and can be changed as appropriate without departing from the spirit of the present invention.

  Further, the processing flow according to each of the above-described embodiments (see FIGS. 2, 3 and 5) is also an example, and can be appropriately changed without departing from the gist of the present invention.

It is the schematic which shows the structure of the information storage device which concerns on embodiment. It is a flowchart which shows the flow of the main process which concerns on embodiment. It is a flowchart which shows the flow of the refresh operation process which concerns on embodiment. It is the schematic which shows typically an example of the use condition of DRAM which concerns on another form. It is a flowchart which shows the flow of a process of the main process program which concerns on another form.

Explanation of symbols

10 Information storage device 20 DRAM controller (refresh operation execution control means)
22 registers (storage means)
30 DRAM (semiconductor memory device)

Claims (2)

A storage control device for controlling writing and reading of data to and from a semiconductor storage device,
Storage means for updating and storing usage status information indicating a usage status of a storage area of the semiconductor storage device;
A refresh operation execution control means for executing a refresh operation for maintaining a storage state at a predetermined refresh cycle for a storage area being used based on the use state information stored in the storage means;
A storage control device.   The storage control device according to claim 1, wherein the usage status information is an address of the storage area being used.

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