TWI740773B - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided, which can suppress the increase in power consumption, and avoid data damage due to the row hammer problem. The semiconductor memory device includes a controlling part 10. The controlling part 10 controls an interval of a refresh operation of a memory. The higher a frequency of a read or write access request for the memory during a determined period is, the shorter the controlling part 10 controls the interval of the refresh operation of the memory.

Description

Semiconductor memory device

The present invention relates to semiconductor memory devices.

DRAM (Dynamic Random Access Memory) in semiconductor memory devices is a type of volatile memory that stores information by accumulating charges in capacitors. Once power is not supplied, the stored information will be lost. Since the charge accumulated in the capacitor is discharged after a certain period of time, the DRAM needs to be charged periodically. Such a memory retention operation is called refresh.

However, during the refresh period, if multiple read and/or write requests for the same row address are too concentrated, a row hammer problem may occur. The so-called row hammering problem is that when multiple accesses to the same row address are too concentrated within a certain period of time, the row address physically adjacent to the row address has the charge of the corresponding data bit due to discharge And cause the problem of data destruction.

In order to solve the problem of column hammering, for example, some people have considered setting the refresh interval of the memory to be shorter. However, in this case, refreshing will become frequently performed at short intervals, so the power consumption of the semiconductor memory device may increase.

The object of the present invention is to provide a semiconductor memory device that can suppress the increase in power consumption while avoiding data damage caused by the row hammering problem.

The present invention provides a semiconductor memory device, including: a control unit, which controls the interval of refresh operations of the memory; The interval of refresh operations becomes shorter.

According to the semiconductor memory device of the present invention, the increase in power consumption can be suppressed, and data damage caused by the row hammering problem can be avoided at the same time.

Hereinafter, the semiconductor memory device related to the embodiment of the present invention will be described in detail with reference to the attached drawings. However, this embodiment is an illustrative example, and the present invention is not limited to this.

FIG. 1 is a block diagram showing a configuration example of the semiconductor memory device according to the first embodiment of the present invention. The semiconductor memory device includes a control unit 10 and a memory 20. Each of the control unit 10 and the memory 20 can be constituted by dedicated hardware devices or logic circuits.

In an embodiment, the semiconductor memory device may be a pSRAM (pseudo-Static Random Access Memory, virtual static random access memory) constructed by internally controlling the refresh operation. In the existing DRAM, there is generally a dedicated circuit to solve the row hammering problem by registering the address of the disturbing word line or recovering the data with an additional refresh operation. However, compared with existing DRAM, pSRAM is moving towards miniaturization, so it is difficult to have space for such a dedicated circuit. When such a dedicated circuit is installed in the pSRAM, the cost of the pSRAM may also be high. Therefore, when the present invention is applied to pSRAM, there is no need to provide such a dedicated circuit, which can suppress the increase in power consumption and avoid data damage caused by the column hammering problem.

Please refer to FIG. 1, the control unit 10 controls the interval of the refresh operation of the memory 20. In one embodiment, if the frequency of read or write access requests to the memory 20 within a predetermined period is higher, the interval at which the control unit 10 controls the refresh operation of the memory 20 becomes shorter. In another embodiment, if the frequency of the read or write access request to the memory 20 within a predetermined period is higher, the control unit 10 may also control the refresh request (in this embodiment, the refresh signal described later is The shorter the interval of REF) becomes, the refresh request is generated at regular intervals in order to perform the refresh operation of the memory 20. In this way, if the frequency of the read or write access request to the memory 20 in a predetermined period is higher, the refresh request can be generated at a shorter interval. Therefore, the refresh operation of the memory 20 can be performed frequently, and data damage caused by the row hammering problem can be avoided. In addition, the detailed configuration of the control unit 10 will be described later.

Continuing to refer to FIG. 1, the memory 20 is a semiconductor memory (for example, DRAM, etc.) that needs to be refreshed. The memory 20 includes a command decoder 21, a column control unit 22, a row control unit 23, and a memory cell array 24. The command decoder 21 interprets the command signal provided from the outside and generates the command control signal. For example, if the instruction provided from the outside is a read instruction, the instruction decoder 21 outputs the trigger signal CMDRD of the read operation to the column control section 22 and the row control section 23. In addition, if the command provided from the outside is a write command, the command decoder 21 outputs the trigger signal CMDWR of the write operation to the column control section 22 and the row control section 23.

The column control unit 22 controls the enabling/disabling of the corresponding memory array in the memory cell array 24 according to the trigger signals CMDRD, CMDWR or the refresh signal REF described later. For example, the column control unit 22 outputs the signal WLON for enabling the column word line and the signal WLOFF for disabling the column word line to the memory cell array 24, and then selects the character to be read, written or refreshed. String.

In addition, the column control unit 22 outputs the signal SAEN used to enable the sense amplifier to the memory cell array 24 and the row control unit 23.

In addition, the column control unit 22 outputs a signal ACCESS indicating a request for read or write access and a signal ACCFREQ indicating the frequency of read or write access to the memory cell array 24 to the control unit 10. Here, the frequency of read or write access to the memory cell array 24, for example, can be obtained by counting the trigger signals CMDRD and CMDWR using a counter (not shown) provided in the column control section 22. The column control unit 22 may also indicate the frequency of read or write access within the predetermined period every time a predetermined period has elapsed (for example, when the frequency is less than the first threshold, it is "Low"; when the frequency is greater than The signal ACCFREQ that is equal to the first threshold and less than the second threshold (the first threshold <the second threshold) is "Middle"; when the frequency is greater than or equal to the second threshold, the signal ACCFREQ is output to the control unit 10.

In addition, if a high-level refresh signal REF is input from the control unit 10, the column control unit 22 performs a refresh operation for the column address shown in the refresh address signal RFA output from the control unit 10.

The row control unit 23 outputs a signal CLEN for enabling the row bit line to the memory cell array 24 based on the trigger signals CMDRD, CMDWR, etc. Then select the row bit line to perform read or write access, etc.

In addition, the address and data control of the memory cell array 24 are also well-known technologies, so the description is omitted in this embodiment.

In this embodiment, the instruction decoder 21, the column control section 22, the row control section 23, and the memory cell array 24 are provided in the memory 20 as an example; however, the present invention is not limited to this, when the memory When the body 20 exists outside the semiconductor memory device, at least one of the respective sections 21 to 24 may be provided in the semiconductor memory device together with the control section 10.

With reference to Fig. 2, the configuration of the control unit 10 will be described. The control unit 10 includes an oscillator 100, a counter 110, a look-up table 120, a comparator 130, a timing generator 140, a sequencer 150, and a refresh address counter 160. The oscillator 100 generates an oscillation signal SROSC for refresh operation at a predetermined interval and inputs it to the counter 110.

The counter 110 counts the pulses of the oscillation signal SROSC output from the oscillator 100, and outputs the n+1 (n is a positive integer) bit signal SRCNT<n:0> representing the count value of the pulse to the comparator 130 and timekeeping Producer 140. In addition, if the signal SRRST for resetting the count value to the initial value (for example, 0) is input to the comparator 130, the counter 110 resets the count value to the initial value.

Each time the signal ACCFREQ representing the frequency of read or write access in a predetermined period is input from the column control unit 22, the comparison table 120 will indicate the number of pulses of the oscillation signal SROSC corresponding to the signal ACCFREQ, and is n+ The 1 (n is a positive integer) bit signal SRDIV<n:0> is output to the comparator 130. Here, the comparison table 120 may also correspond to different pulse numbers according to the frequency of read or write access in a predetermined period. In addition, the look-up table 120 can also be designed such that if the frequency of read or write access in a predetermined period is lower, the number of pulses of the oscillation signal SROSC becomes more.

In addition, in this embodiment, when the signal ACCFREQ indicates a low frequency (Low), the comparison table 120 outputs the signal SRDIV<n:0> indicating that the number of pulses is 12 to the comparator 130; when the signal ACCFREQ indicates a middle frequency (Middle) When the comparison table 120 outputs the signal SRDIV<n:0> indicating the number of pulses is 6 to the comparator 130; when the signal ACCFREQ indicates high frequency (High), the comparison table 120 will indicate the signal SRDIV<n with the number of pulses 3 :0>output to the comparator 130.

If the signal SRCNT<n:0> representing the number of pulses of the oscillation signal SROSC is input from the counter 110, the comparator 130 will calculate the number of pulses of the oscillation signal SROSC (for example, the value of the signal SRCNT<n:0>+1 in Figure 3) ), and the signal SRDIV<n:0> input from the comparison table 120 for comparison. Then, when the number of pulses of the oscillation signal SROSC is consistent with the value of the signal SRDIV<n:0>, the comparator 130 outputs the signal SRRST to the counter 110.

When the value of the signal SRCNT<n:0> output from the counter 110 is 0, the timing generator 140 outputs the high-level refresh trigger signal SRTRG to the sequencer 150.

If the high-level refresh trigger signal SRTRG is input from the timing generator 140, the sequencer 150 outputs the high-level refresh signal REF to the refresh address counter 160 and the column control unit 22. In addition, for example, if the signal ACCESS that requires read or write access and the high-level refresh trigger signal SRTRG are input at almost the same time point, the sequencer 150 can also execute the signals ACCESS and SRTRG. Arbitration (mediation) between the two, and adjust the output time point of the refresh signal REF.

The refresh address counter 160 outputs a signal RFA indicating the column address that is the target of the refresh operation to the column control unit 22. In addition, each time a refresh operation is performed (that is, a high-level refresh signal REF is input from the sequencer 150), the refresh address counter 160 increments the column address that becomes the target of the refresh operation. For example, when the pulse of the refresh signal REF falls, the refresh address counter 160 may increment the column address.

FIG. 3 is a timing chart showing the voltage transitions of various signals in the semiconductor memory device of this embodiment. At time t1, when the signal ACCFREQ indicating that the read or write access in a predetermined period is low frequency (Low) is input to the comparison table 120, the comparison table 120 will signal the corresponding pulse number (for example, 12 here). SRDIV<n:0> is output to the comparator 130. In addition, since the value of the signal SRCNT<n:0> is 0, the timing generator 140 outputs the high-level refresh trigger signal SRTRG to the sequencer 150. Then, the sequencer 150 outputs the high-level refresh signal REF to the refresh address counter 160 and the column control unit 22. In this way, the refresh operation is performed on the column address ("0" in the illustration) indicated by the signal RFA. Then, at time t2 after the pulse of the refresh signal REF falls, the refresh address counter 160 increments the column address indicated by the signal RFA (in the example, it increments from "0" to "1").

In this way, when the frequency of the read or write access in a predetermined period is Low, every time the number of pulses of the oscillation signal SROSC generated by the oscillator 100 reaches 12, a refresh signal REF is generated.

Next, at time t3, when the signal ACCFREQ indicating that the read or write access in a predetermined period is high frequency (High) is input to the comparison table 120, the comparison table 120 will correspond to the number of pulses (for example, 3 here) The signal SRDIV<n:0> is output to the comparator 130. In addition, the timing generator 140 outputs the high-level refresh trigger signal SRTRG to the sequencer 150. Then, the sequencer 150 outputs the high-level refresh signal REF to the refresh address counter 160 and the column control unit 22. In this way, a refresh operation is performed for the column address ("1" in the illustration) indicated by the signal RFA. Then, when the pulse of the refresh signal REF falls, the refresh address counter 160 increments the column address indicated by the signal RFA (in the example, it increments from "1" to "2").

In addition, when the signal SRCNT<n:0> indicating that the number of pulses of the oscillation signal SROSC is 3 is input from the counter 110, since the number of pulses of the oscillation signal SROSC is consistent with the value of the signal SRDIV<n:0>, the comparator 130 The signal SRRST is output to the counter 110. At this time, the counter 110 resets the count value of the pulse of the oscillation signal SROSC to the initial value.

Then, at time t4 and t5, the high-level refresh signal REF is output to the refresh address counter 160 and the column control section 22, and the column addresses indicated by the signal RFA (in the example, “2” and “2” and 「3」) Perform refresh operation.

In this way, when the frequency of read or write access in a predetermined period is High, every time the number of pulses of the oscillation signal SROSC generated by the oscillator 100 reaches 3, a refresh signal REF is generated.

Next, at time t6, when the signal ACCFREQ indicating that the read or write access in a predetermined period is a middle frequency (Middle) is input to the comparison table 120, the comparison table 120 sets the corresponding pulse number (for example, 6 here) The signal SRDIV<n:0> is output to the comparator 130. In addition, the timing generator 140 outputs the high-level refresh trigger signal SRTRG to the sequencer 150. Then, the sequencer 150 outputs the high-level refresh signal REF to the refresh address counter 160 and the column control unit 22. In this way, a refresh operation is performed for the column address ("4" in the illustration) indicated by the signal RFA. Then, when the pulse of the refresh signal REF falls, the refresh address counter 160 increments the column address indicated by the signal RFA (in the illustration, it increments from "4" to "5").

In addition, when the signal SRCNT<n:0> indicating that the number of pulses of the oscillation signal SROSC is 6 is input from the counter 110, since the number of pulses of the oscillation signal SROSC is consistent with the value of the signal SRDIV<n:0>, the comparator 130 The signal SRRST is output to the counter 110. At this time, the counter 110 resets the count value of the pulse of the oscillation signal SROSC to the initial value.

Then, at time t7, the high-level refresh signal REF is output to the refresh address counter 160 and the column control section 22, and the column address indicated by the signal RFA ("5" in the illustration) is refreshed.

In this way, when the frequency of read or write access in a predetermined period is the middle frequency (Middle), every time the number of pulses of the oscillation signal SROSC generated by the oscillator 100 reaches 6, a refresh signal REF is generated.

In addition, in this embodiment, one example is used to illustrate the case of performing a refresh operation when the value of the signal SRCNT<n:0> is an initial value (for example, 0 here); however, the present invention is not limited to this. For example, the refresh operation can also be performed when the value of the signal SRCNT<n:0> is other than 0.

As described above, in this embodiment, if the frequency of read or write access requests to the memory in a predetermined period is higher, the refresh request (here, the refresh signal REF) can be generated at a shorter interval.

As described above, according to the semiconductor memory device of this embodiment, for example, when a read or write access is frequently requested within a predetermined period, the refresh operation of the memory 20 can be frequently performed accordingly. In this way, the data damage caused by the row hammering problem can be avoided. On the other hand, if the frequency of read or write access requests in a predetermined period is lower, the refresh operation of the memory 20 can be performed at a relatively long interval. Therefore, compared with the case where the refresh operation is often performed at a short interval , Which can reduce the number of refresh operations performed. Thereby, it is possible to suppress an increase in power consumption of the semiconductor memory device.

Hereinafter, the second embodiment of the present invention will be described. The semiconductor memory device of this embodiment is different from the first embodiment in that if the frequency of read or write access requests to the memory 20 within a predetermined period of time is higher, the control unit 10 controls all the devices in response to the refresh request. The number of refresh operations performed increases, and the refresh request is generated at regular intervals in order to perform the refresh operation of the memory 20. Hereinafter, a configuration different from the first embodiment will be described.

Fig. 4 shows a configuration example of the control unit 10 related to the second embodiment. In this embodiment, the control unit 10 includes an oscillator 100, a timing generator 140, a sequencer 150, a refresh address counter 160, a counter 170, a refresh skip control unit 180, and a refresh skip unit 190. Here, the configurations of the oscillator 100, the sequencer 150, and the refresh address counter 160 are the same as those of the first embodiment described above.

In this embodiment, every time the oscillation signal SROSC is input from the oscillator 100, the timing generator 140 can also output the refresh request signal SRREQ with the same pulse as the oscillation signal SROSC to the counter 170 and the refresh skip unit 190.

The counter 170 counts the pulses of the refresh request signal SRREQ output from the timing generator 140, and outputs the n+1 (n is a positive integer) bit signal SRREQCNT<n:0> representing the count value of the pulse to the refresh skip Control unit 180. In addition, when a signal (not shown) for resetting the count value to the initial value (for example, 0) is input from the refresh skip control unit 180, the counter 170 may also reset the count value to the initial value.

If the initial value signal SRREQCNT<n:0> is input from the counter 170, the refresh skip control unit 180 outputs the high-level refresh skip signal REFSKIP to the refresh skip unit 190. In addition, each time the number of pulses of the refresh request signal SRREQ indicated by the signal SRREQCNT<n:0> reaches the number of pulses corresponding to the access frequency indicated by the signal ACCFREQ input from the column control section 22, the refresh skip control section 180 can also output a signal (not shown) for resetting the count value to the initial value to the counter 170. Here, the number of pulses corresponding to the access frequency indicated by the signal ACCFREQ can also be set like the above-mentioned comparison table 120. The lower the frequency of read or write access in a predetermined period, the number of pulses becomes more.

When the low-level refresh skip signal REFSKIP is input from the refresh skip control unit 180, the refresh skip unit 190 converts the refresh request signal SRREQ output from the timing generator 140 into a low-level refresh trigger signal SRTRG, and outputs it to Sequencer 150. In addition, when the high-level refresh skip signal REFSKIP is input from the refresh skip control unit 180, the refresh skip unit 190 converts the refresh request signal SRREQ output from the timing generator 140 into the high-level refresh trigger signal SRTRG, and Output to the sequencer 150.

FIG. 5 is a timing chart showing the voltage transitions of various signals in the semiconductor memory device of this embodiment. At time t11, if the input signal ACCFREQ indicating that the read or write access in a predetermined period is low frequency (Low), when the initial value signal SRREQCNT<n:0> is input from the counter 170, refresh skip control The unit 180 outputs the high-level refresh skip signal REFSKIP to the refresh skip unit 190. In addition, since the high-level refresh skip signal REFSKIP is input from the refresh skip control unit 180, the refresh skip unit 190 converts the refresh request signal SRREQ output from the timing generator 140 into the high-level refresh trigger signal SRTRG, and Output to the sequencer 150. In addition, the sequencer 150 outputs the high-level refresh signal REF to the refresh address counter 160 and the control unit 22. In this way, the refresh operation is performed on the column address ("0" in the illustration) indicated by the signal RFA. In addition, when the pulse of the refresh signal REF falls, the refresh address counter 160 increments the column address indicated by the signal RFA (in the illustration, it increments from "0" to "1").

In this way, if the read or write access in a predetermined period is low frequency (Low), every time a predetermined number (12 in the example) of refresh request signals SRREQ is generated, a refresh signal REF( That is, one refresh operation is performed).

Next, at time t12, if the input signal ACCFREQ indicating that the read or write access in the predetermined period is high frequency (High), when the initial value signal SRREQCNT<n:0> is input from the counter 170, the refresh jumps The control unit 180 outputs the high-level refresh skip signal REFSKIP to the refresh skip unit 190. In addition, the refresh skip unit 190 converts the refresh request signal SRREQ output from the timing generator 140 into a high-level refresh trigger signal SRTRG, and outputs it to the sequencer 150. In addition, the sequencer 150 outputs the high-level refresh signal REF to the refresh address counter 160 and the control unit 22. In this way, a refresh operation is performed for the column address ("1" in the illustration) indicated by the signal RFA. In addition, when the pulse of the refresh signal REF falls, the refresh address counter 160 increments the column address indicated by the signal RFA (in the example, it increments from "1" to "2").

In addition, when the number of pulses of the refresh request signal SRREQ indicated by the signal SRREQCNT<n:0> reaches the number of pulses corresponding to the access frequency indicated by the signal ACCFREQ input from the column control unit 22 (3 in the example), The refresh skip control unit 180 outputs a signal (not shown) for resetting the count value to the initial value to the counter 170. At this time, the counter 170 resets the count value of the pulse of the refresh request signal SRREQ to the initial value.

Then, at time t13 and t14, the high-level refresh signal REF is output to the refresh address counter 160 and the column control section 22, and the column addresses indicated by the signal RFA (in the example, “2” and “2” and 「3」) Perform refresh operation.

In this way, if the read or write access in a predetermined period is high frequency (High), each time a predetermined number of refresh request signals SRREQ (3 in the illustration) are generated, a refresh signal REF( That is, one refresh operation is performed).

Next, at time t15, if the input signal ACCFREQ indicating that the read or write access in a predetermined period is a middle frequency (Middle), when the initial value signal RREQCNT<n:0> is input from the counter 170, the refresh jumps The control unit 180 outputs the high-level refresh skip signal REFSKIP to the refresh skip unit 190. In addition, the refresh skip unit 190 converts the refresh request signal SRREQ output from the timing generator 140 into a high-level refresh trigger signal SRTRG, and outputs it to the sequencer 150. In addition, the sequencer 150 outputs the high-level refresh signal REF to the refresh address counter 160 and the control unit 22. In this way, a refresh operation is performed for the column address ("4" in the illustration) indicated by the signal RFA. In addition, when the pulse of the refresh signal REF falls, the refresh address counter 160 increments the column address indicated by the signal RFA (in the illustration, it increments from "4" to "5").

In addition, when the number of pulses of the refresh request signal SRREQ indicated by the signal SRREQCNT<n:0> reaches the number of pulses corresponding to the access frequency indicated by the signal ACCFREQ input from the column control unit 22 (6 in the illustration), The refresh skip control unit 180 outputs a signal (not shown) for resetting the count value to the initial value to the counter 170. At this time, the counter 170 resets the count value of the pulse of the refresh request signal SRREQ to the initial value.

Then, at time t16, the high-level refresh signal REF is output to the refresh address counter 160 and the column control section 22, and the column address indicated by the signal RFA ("5" in the illustration) is refreshed.

In this way, if the read or write access in a predetermined period is at the middle frequency (Middle), each time a predetermined number of refresh request signals SRREQ (6 in the example) are generated, a refresh signal REF( That is, one refresh operation is performed).

In addition, in this embodiment, one example is used to illustrate the case of performing a refresh operation when the value of the signal SRCNT<n:0> is an initial value (for example, 0 here); however, the present invention is not limited to this. For example, the refresh operation can also be performed when the value of the signal SRCNT<n:0> is other than 0.

As described above, according to the semiconductor memory device of this embodiment, if the frequency of read or write access requests to the memory within a predetermined period is higher, the refresh request signal SRREQ generated at regular intervals can be addressed. Increase the number of refresh operations performed (that is, increase the number of refresh operations performed). Thereby, the refresh operation of the memory can be performed frequently, and the data damage caused by the row hammering problem can be avoided.

Hereinafter, the third embodiment of the present invention will be described. The semiconductor memory device of this embodiment is different from the foregoing embodiments in that the control unit 20 controls the refresh operation interval for each of the plurality of blocks of consecutive column addresses. Hereinafter, the configuration different from the above-mentioned respective embodiments will be described.

In this embodiment, the semiconductor memory device includes a plurality of (for example, 4 here) blocks, and each block includes a refresh address counter. The refresh address counter specifies the address at which the refresh operation is performed according to the refresh request. . In addition, the control unit 10 controls the execution of the refresh operation corresponding to the column address specified by the refresh address counter corresponding to each block of the plurality of blocks for each block of the plurality of blocks. In this way, when performing a refresh operation on any of the plurality of blocks, the refresh address counter can be used to easily specify the column address for the refresh operation. In addition, among the plurality of blocks, the number of consecutive column addresses in each block may be the same or different.

Fig. 6 shows a configuration example of the control unit 10 related to the third embodiment. In this embodiment, the control unit 10 includes: an oscillator 100, a timing generator 140, a sequencer 150, a refresh address counter 160, and refresh address counters 161, 162, 163, and 164, which are respectively arranged in a plurality of blocks ( In the illustration, each of the blocks (block 0 to block 3, a total of 4 blocks), the refresh skip control unit 180, and the refresh skip unit 190. Here, the configurations of the oscillator 100, the timing generator 140, the sequencer 150, the counter 170, and the refresh skip unit 190 are the same as in the second embodiment described above.

In this embodiment, the refresh address counter 160 can also be designed to input the refresh request signal SRREQ from the timing generator 140. In this case, the refresh address counter 160 can also count the number of pulses of the refresh request signal SRREQ so as to cycle within a predetermined counting range (for example, 0-3). In addition, for example, every time the rising edge of the pulse of the refresh request signal SRREQ starting from No. 0 to a predetermined number (for example, No. 3) is counted, the refresh address counter 160 can also be used to change the number to the refresh operation. The target block is switched to the signal RFA (BLOCK) of other blocks, and is output to the refresh skip control unit 180. In addition, the refresh address counter 160 outputs the refresh signal REF input from the sequencer 150 to the refresh address counters 161 to 164 of each block during the period when the signal RFA (BLOCK) is output, and the signal RFA ( The refresh address counter (for example, refresh address counter 161) corresponding to the block (for example, block 0) designated by BLOCK).

The refresh address counter 161 of the block 0 outputs the signal RFA BLK0 indicating the column address in the block 0 that is the target of the refresh operation to the column control unit 22. In addition, each time a refresh operation is performed for block 0, the refresh address counter 161 increments the column address in block 0 that is the target of the refresh operation. The refresh address counter 162 of the block 1 outputs the signal RFA BLK1 indicating the column address in the block 1 that is the target of the refresh operation to the column control unit 22. In addition, each time a refresh operation is performed for block 1, the refresh address counter 162 increments the column address in block 1 that is the target of the refresh operation. The refresh address counter 163 of the block 2 outputs the signal RFA BLK2 indicating the column address in the block 2 that is the target of the refresh operation to the column control unit 22. In addition, each time a refresh operation is performed for block 2, the refresh address counter 163 increments the column address in block 2 that is the target of the refresh operation. The refresh address counter 164 of the block 3 outputs the signal RFA BLK3 indicating the column address in the block 3 that is the target of the refresh operation to the column control unit 22. In addition, each time a refresh operation is performed on block 3, the refresh address counter 164 increments the column address in block 3 that is the target of the refresh operation.

In this embodiment, if the initial value signal SRREQCNT<n:0> is input from the counter 170, the refresh skip control unit 180 outputs the high-level refresh skip signal REFSKIP to the refresh skip unit 190. In addition, each time the pulse number of the refresh request signal SRREQ shown by the signal SRREQCNT<n:0> reaches the access frequency corresponding to the block shown by the signal RFA(BLOCK) input from the refresh address counter 160 (from When the number of pulses corresponding to the signal ACCFREQ input by the column control unit 22 is shown, the refresh skip control unit 180 may also output a signal (not shown) for resetting the count value to the initial value to the counter 170. Here, the signal ACCFREQ can also target a plurality of blocks 0 to 3, respectively representing the frequency of read or write access requests within a predetermined period.

FIG. 7 is a timing chart showing the voltage transitions of various signals in the semiconductor memory device of this embodiment. Here is one example to illustrate the following situations: the access frequency for block 0 (ACCFREQ(BLK0)) is low frequency (Low); the access frequency for block 3 (ACCFREQ(BLK3)) is low frequency (Low) ; The access frequency for block 1 (ACCFREQ (BLK1)) is the middle frequency (Middle); the access frequency for block 2 (ACCFREQ (BLK2)) is the high frequency (High).

In addition, as shown in Figure 7, one example is used to illustrate the following situation: if the access to the block is Low, then one refresh signal REF is generated for every four refresh request signals SRREQ; if When the access to the block is Middle, 2 refresh signals REF are generated for every 4 refresh request signals SRREQ; if the access to the block is High, then every 4 refresh requests The signal SRREQ generates 4 refresh signals REF.

At time t21, the refresh address counter 160 outputs the signal RFA (BLOCK) used to designate block 0 as the target of the refresh operation to the refresh skip control unit 180. The refresh skip control unit 180 determines, based on the signal RFA (BLOCK) input from the refresh address counter 160 and the signal ACCFREQ input from the column control unit 22, that block 0 whose access is low frequency is designated as the target of the refresh operation.

Here, when the initial value signal SRREQCNT<n:0> is input from the counter 170, the refresh skip control unit 180 may also output the high-level refresh skip signal REFSKIP to the refresh skip unit 190. In addition, when the signal SRREQCNT<n:0> with a value other than the initial value is input from the counter 170, the refresh skip control unit 180 may also output the low-level refresh skip signal REFSKIP to the refresh skip unit 190.

Thereby, when the signal SRREQCNT<n:0> of the initial value is input to the refresh skip control unit 180, the refresh operation is performed for the column address ("0" in the illustration) indicated by the signal RFA BLK0. In addition, when the pulse of the refresh signal REF falls, the refresh address counter 161 of the block 0 increments the column address indicated by the signal RFA BLK0 (in the example, it increments from "0" to "1").

In this way, one refresh signal REF is generated (that is, one refresh operation is performed) for block 0 whose read or write access is low in a predetermined period.

Then, at time t22, when the refresh address counter 160 receives a predetermined number of refresh signals REF (for example, 4 here), the refresh address counter 160 will increment the count value by 1, and use it to specify the area. The block 1 is output to the refresh skip control unit 180 as the signal RFA (BLOCK) that is the target of the refresh operation. The refresh skip control unit 180 determines that the block 1 whose access is the medium frequency is designated as the target of the refresh operation based on the signal RFA (BLOCK) input from the refresh address counter 160 and the signal ACCFREQ input from the column control unit 22.

Here, when the signal SRREQCNT<n:0> of the initial value is input from the counter 170, the refresh skip control unit 180 may also skip the high-level refresh skip REFSKIP and output it to the refresh skip unit 190. In addition, when the signal SRREQCNT<n:0> of a predetermined value other than the initial value (for example, 2 here) is input from the counter 170, the refresh skip control unit 180 may also skip the high-level refresh skip REFSKIP and output it to the refresh skip过部190。 过部190.

Thereby, when the signal SRREQCNT<n:0> of the initial value is input to the refresh skip control unit 180, the refresh operation is performed for the column address (“0” in the illustration) indicated by the signal RFA BLK1. At this time, when the pulse of the refresh signal REF falls, the refresh address counter 162 of the block 1 increments the column address indicated by the signal RFA BLK1 (in the example, it increments from "0" to "1").

In addition, when a signal SRREQCNT<n:0> of a predetermined value other than the initial value (for example, 2 here) is input to the refresh skip control unit 180, the column address shown by the signal RFA BLK1 (in the example, "1 ") Perform refresh operation. When the pulse of the refresh signal REF falls, the refresh address counter 162 of the block 1 increments the column address indicated by the signal RFA BLK1 (in the example, it increments from "1" to "2").

In this way, two refresh signals REF are generated (that is, two refresh operations are performed) for block 1 where the read or write access in a predetermined period is a middle frequency (Middle).

Then, at time t23, when the refresh address counter 160 receives a predetermined number of refresh signals REF (for example, 4 here), the refresh address counter 160 will increment the count value by 1, and use it to specify the area. The block 2 signal RFA (BLOCK), which is the target of the refresh operation, is output to the refresh skip control unit 180. The refresh skip control unit 180 determines, based on the signal RFA (BLOCK) input from the refresh address counter 160 and the signal ACCFREQ input from the column control unit 22, that the block 2 whose access is high frequency is designated as the target of the refresh operation.

Here, every time the signal SRREQCNT<n:0> is input from the counter 170, the refresh skip control unit 180 may also output the high-level refresh skip signal REFSKIP to the refresh skip unit 190.

In this way, every time the signal SRREQCNT<n:0> is input to the refresh skip control unit 180, the column address shown by the signal RFA BLK2 (in the example, it is "0", "1", "2" , "3") to perform refresh operations in sequence. At this time, the refresh address counter 162 of block 2 increments the column address indicated by the signal RFA BLK2 (in the example, it increments to "0" to "4").

In this way, 4 refresh signals REF are generated for block 2 where the read or write access is high in a predetermined period (that is, 4 refresh operations are performed).

Then, at time t24, when the refresh address counter 160 receives a predetermined number of refresh signals REF (for example, 4 here), the refresh address counter 160 will increment the count value by 1, and use it to specify the area. Block 3 is the signal RFA (BLOCK) that is the target of the refresh operation and is output to the refresh skip control unit 180. The refresh skip control unit 180 determines, based on the signal RFA (BLOCK) input from the refresh address counter 160 and the signal ACCFREQ input from the column control unit 22, that the block 3 whose access is low frequency is designated as the target of the refresh operation.

In addition, the related processing for the refresh operation of block 3 is the same as the related processing of the refresh operation for block 0 described above.

Then, at time t25, when the refresh address counter 160 receives a predetermined number of refresh signals REF (for example, 4 here), and when the count value of the refresh address counter 160 reaches a predetermined threshold (for example, this At 3), the refresh address counter 160 will reset the count value to the initial value (for example, 0 here), and output the signal RFA (BLOCK) used to designate block 0 as the object of the refresh operation to refresh The control unit 180 is skipped. In this case, when the refresh signal REF is input, the refresh address counter 161 of block 0 increments the column address indicated by the signal RFA BLK0 (in the example, it increments from "1" to "2").

Then, at time t26, when the refresh address counter 160 receives a predetermined number of refresh signals REF (for example, 4 here), the refresh address counter 160 will increment the count value by 1, and use it to specify the area. The block 1 is output to the refresh skip control unit 180 as the signal RFA (BLOCK) that is the target of the refresh operation. In this case, when the refresh signal REF is input, the refresh address counter 162 of block 1 increments the column address indicated by the signal RFA BLK1 (in the example, it increments from "2" to "4").

In addition, in this embodiment, one example is used to describe when the access to the block is Low and the value of the signal SRCNT<n:0> is the initial value (for example, 0 here), and when When the access to the block is in the middle frequency (Middle) and the value of the signal SRCNT<n:0> is the initial value (for example, 0 here) or a predetermined value (for example, 2 here), the refresh operation is performed Situation; however, the present invention is not limited to this. For example, the refresh operation can also be performed when the value of the signal SRCNT<n:0> is any other value.

As described above, according to the semiconductor memory device of this embodiment, it is possible to control the blocks with a high frequency of read or write access requirements among a plurality of blocks 0 to 3, so that the interval of refresh operations is shortened; and Among the plurality of blocks, the block with low frequency for controlling read or write access requests makes the interval of refresh operations longer. As a result, compared with the case where the entire memory is refreshed at short intervals, the number of refresh operations can be reduced, and the increase in power consumption of the semiconductor memory device can be further suppressed.

Hereinafter, a modification of the above-mentioned third embodiment will be described. In the above-mentioned third embodiment, one example is used to illustrate the case where the refresh address counters 161 to 164 are respectively set in a plurality of blocks 0 to 3; however, the present invention is not limited to this. For example, the control unit 10 may also control the refresh operation interval for each of the plurality of blocks without using the refresh address counters 161 to 164.

FIG. 8 shows a configuration example of the control unit 10 in the semiconductor memory device of the modification. In this modification, the control unit 10 includes an oscillator 100, a counter 110, a look-up table 120, a comparator 130, a timing generator 140, a sequencer 150, a refresh address counter 160, a refresh skip control unit 180, and refresh Skip section 190. Here, the configurations of the oscillator 100, the counter 110, the look-up table 120, the comparator 130, the timing generator 140, and the sequencer 150 are the same as those of the first embodiment described above.

In this modified example, the refresh address counter 160 outputs the signal RFA to the column control unit 22 as in the first embodiment described above. In addition, in this modification, the refresh address counter 160 also outputs the signal RFA to the refresh skip control unit 180. In addition, every time a refresh operation is performed, and every time the signal RFAINC used to increment the column address that becomes the target of the refresh operation is input from the refresh skip section 190, the refresh address counter 160 is incremented to become the target of the refresh operation. Column address. In addition, in this modified example, for example, the column address may also be incremented so as to circulate within a predetermined range (for example, 0~3).

In addition, every time the column address in the memory cell array 24 is fully counted once, the refresh address counter 160 increments the number of bypasses of all the column addresses, and outputs a signal CNT indicating the number of bypasses to the refresh skip section 180. Here, for example, the number of detours can also be increased so as to circulate within a predetermined range (for example, 0~3). In addition, although it is not shown in Figure 8, the refresh address counter 160 can also output the signal RFA (BLOCK) used to specify the block as the target of the refresh operation to the refresh as in the second embodiment described above. The control unit 180 is skipped.

In this modification, the refresh skip control unit 180 is based on the access frequency corresponding to the block indicated by the signal RFA (BLOCK) input from the refresh address counter 160 (the signal ACCFREQ (BLOCK) input from the column control unit 22) , And the signal RFA and the signal CNT input from the refresh address counter 160 will output the refresh skip signal REFSKIP indicating whether to perform refresh for the column address indicated by the signal RFA, and output to the refresh skip unit 190.

Here, for example, the refresh skip control unit 180 may also use the look-up table shown in FIG. 9 to determine whether to perform refresh for the column address indicated by the signal RFA. Figure 9 (a) ~ (c) shows an example of the structure of the comparison table. As shown in Figure 9(a)~(c), the comparison table can also be based on the value of each signal RFA (0~3 in the figure) and the value of each signal CNT (0~3 in the figure), respectively To correspond to the information indicating whether the refresh operation is performed or not (refresh operation skipped).

Figure 9(a) shows an example of the relationship between the value of the signal CNT and the value of the signal RFA when the access frequency for the block indicated by the signal RFA (BLOCK) is low. In the example shown in Figure 9(a), when the value of the signal CNT is 0, the refresh operation is performed for the 0th column address (the value of RFA<1:0> is "0"); No. 1~3 column address (RFA<1:0> value is "1"~"3") do not perform refresh operation (skip refresh operation). In addition, set that when the value of the signal CNT is 1, the refresh operation is only performed on the first column address; when the value of the signal CNT is 2, the refresh operation is only performed on the second column address; when the signal CNT When the value of is 3, the refresh operation is performed only for the third column address. That is, when the access frequency for the block is Low, every time all the addresses in the memory cell array 24 are circumvented, one of the addresses 0~3 in the block will be used. The address performs a refresh operation, and all addresses 0~3 in the block are refreshed by bypassing 4 times.

Figure 9(b) shows an example of the relationship between the value of the signal CNT and the value of the signal RFA when the access frequency for the block indicated by the signal RFA (BLOCK) is the middle frequency (Middle). In the example shown in Figure 9(b), when the value of the signal CNT is 0, the column addresses of No. 0 and No. 2 (RFA<1:0> are "0" and "2". ") Perform a refresh operation; for the first and third column addresses (RFA<1:0> are "1" and "3"), no refresh operation is performed (the refresh operation is skipped). In addition, set that when the value of the signal CNT is 1, the refresh operation is only performed on the column addresses of No. 1 and No. 3; when the value of the signal CNT is 2, only the column addresses of No. 0 and No. 2 are performed. When the value of the signal CNT is 3, the refresh operation is performed only for the column addresses of No. 1 and No. 3. That is, when the access frequency for the block is the middle frequency (Middle), every time all the addresses in the memory cell array 24 are circumvented, 2 of the addresses 0~3 in the block will be used. The address performs a refresh operation, and all addresses 0~3 in the block are refreshed by bypassing twice.

Figure 9(c) shows an example of the relationship between the value of the signal CNT and the value of the signal RFA when the access frequency for the block indicated by the signal RFA (BLOCK) is high. In the example shown in Figure 9(c), when the value of the signal CNT is 0, it is set for each column address from No. 0 to No. 3 (RFA<1:0> has a value of "0"~" 3") Perform refresh operation. In addition, when the value of the signal CNT is set to 1~3, the refresh operation is also performed for each column address of No. 0~3. That is, when the access frequency for a block is High, every time all addresses in the memory cell array 24 are detoured, a refresh operation is performed on all addresses 0 to 3 in the block.

The refresh skip control unit 180 uses the look-up table shown in FIGS. 9(a) to (c) to determine whether to perform a refresh operation for the column address indicated by the signal RFA. Then, when it is determined that the refresh operation is performed, the refresh skip control unit 180 outputs the high-level refresh skip signal REFSKIP to the refresh skip unit 190; when it is determined that the refresh operation is not performed (skip), the refresh skip The control unit 180 outputs the low-level refresh skip signal REFSKIP to the refresh skip unit 190.

In this modification, when the high-level refresh skip signal REFSKIP is input from the refresh skip control unit 180, the refresh skip unit 190 converts the refresh request signal SRREQ output from the timing generator 140 into a high-level refresh trigger signal SRTRG, and output to the sequencer 150. In addition, when the low-level refresh skip signal REFSKIP is input from the refresh skip control unit 180, the refresh skip unit 190 converts the refresh request signal SRREQ output from the timing generator 140 into a low-level refresh trigger signal SRTRG and outputs it To the sequencer 150; and output the signal RFAINC to the refresh address counter 160.

Figures 10 to 12 are timing charts showing the voltage transitions of the signals in the semiconductor memory device of this modification example. In addition, here is one example to illustrate the following situations: the access frequency (ACCFREQ (BLOCK)) for block 0 and block 3 is low frequency (Low); the access frequency for block 1 is middle frequency (Middle) ; The access frequency for block 2 (ACCFREQ (BLK2)) is high frequency (High).

Figure 10 shows an example of the refresh operation for each column address 0~3 of block 0. First, the refresh address counter 160 combines the signal CNT indicating the 0th detour, the signal RFA indicating that the object of the refresh operation is the 0th column address, and the signal RFA (BLOCK) indicating that the object of the refresh operation is the block 0 ), output to the refresh skip control unit 180. In this case, the refresh skip control unit 180 uses the signals input from the refresh address counter 160 and the look-up table shown in FIG. 9(a) to determine that the refresh operation is performed for the 0th column address. Then, the refresh skip control unit 180 outputs the high-level refresh skip signal REFSKIP to the refresh skip unit 190. At this time, the refresh skip unit 190 converts the refresh request signal SRREQ output from the timing generator 140 into a high-level refresh trigger signal SRTRG, and outputs it to the sequencer 150. Then, by outputting a refresh signal REF from the sequencer 150, a refresh operation is performed for the 0th column address.

In addition, when the refresh signal is input from the sequencer 150, the refresh address counter 160 outputs the signal RFA indicating that the object of the refresh operation is the first to third column addresses to the refresh skip control unit 180. Here, the refresh skip control unit 180 uses the signals input from the refresh address counter 160 and the comparison table shown in Figure 9(a) to determine that the refresh operation is not performed for the column addresses 1 to 3 ( Skip refresh operation). Then, the refresh skip control unit 180 outputs the low-level refresh skip signal REFSKIP to the refresh skip unit 190. At this time, the refresh skip unit 190 converts the refresh request signal SRREQ output from the timing generator 140 into a low-level refresh trigger signal SRTRG, and outputs it to the sequencer 150. In addition, the refresh skip unit 190 outputs a signal RFAINC for incrementing the column address that is the target of the refresh operation to the refresh address counter 160. Then, by outputting the low-level refresh signal REF from the sequencer 150, the refresh operation for the first to third column addresses is skipped.

In this way, as shown in Figure 10(a), when the 0th detour (the value of signal CNT is "0"), the 0th of block 0 (the value of signal RFA(BLOCK) is 0) The column address of the number (RFA[1:0] value is "0") to perform refresh operation. In addition, as shown in Figure 10(b), during the first detour (the value of signal CNT is "1"), the first column address of block 0 (RFA[1:0] The value is "1") to perform refresh operation. In addition, as shown in Figure 10(c), during the second detour (the value of the signal CNT is "2"), the second column address of block 0 (RFA[1:0] The value is "2") to perform refresh operation. Then, as shown in Figure 10(d), in the third detour (the value of signal CNT is "3"), the third column address of block 0 (RFA[1:0] The value is "3") to perform refresh operation.

Therefore, when the access frequency for block 0 is Low, every time all the addresses in the memory cell array 24 are detoured, one of the addresses 0 to 3 in block 0 The address performs a refresh operation, and all addresses 0~3 in block 0 are refreshed by bypassing 4 times.

Figure 11 shows an example of the refresh operation for each column address 0~3 of block 1. As shown in Figure 11(a), when the 0th detour (the value of signal CNT is "0"), it is for the 0th column of block 1 (the value of signal RFA(BLOCK) is 1) The address (the value of RFA[1:0] is "0") and the second column address (the value of RFA[1:0] is "2") perform the refresh operation. Then, as shown in Figure 11(b), during the first detour (the value of the signal CNT is "1"), the first column address of block 1 (RFA[1:0] The value of is "1") and the third column address (the value of RFA[1:0] is "3") to perform the refresh operation. Then, as shown in Figure 11(c), during the second detour (the value of the signal CNT is "2"), the address of the column No. 0 and the column position No. 2 of the block 1 The address performs a refresh operation. Then, as shown in Figure 11(d), during the third detour (the value of the signal CNT is "3"), the first column address and the third column address of block 1 The address performs a refresh operation.

In this way, when the access frequency for block 1 is the middle frequency (Middle), every time all the addresses in the memory cell array 24 are circumvented, 2 of the addresses 0~3 in block 1 will be changed. Perform refresh operation on each address. By bypassing twice, all addresses 0~3 in block 1 are refreshed.

Figure 12 shows an example of a refresh operation for each column address 0~3 of block 2. As shown in Figure 12(a), in the 0th detour (the value of signal CNT is "0"), for block 2 (the value of signal RFA(BLOCK) is 2) the 0th to the first The column address of No. 3 (RFA[1:0] value is "0" ~ "3") perform refresh operation respectively. Then, as shown in Fig. 12(b)~(d), during the first to third detours (the value of signal CNT is "1" ~ "3"), the same applies to block 2 The column addresses of No. 0 to No. 3 (the value of RFA[1:0] is "0" to "3") are refreshed respectively.

Like this, when the access frequency for block 2 is High, every time all addresses in the memory cell array 24 are detoured, all addresses 0~3 in block 2 are refreshed. .

In addition, the related processing for the refresh operation of block 3 is the same as the related processing of the refresh operation for block 0 described above.

In addition, in this modified example, one example is used to illustrate the case where four column addresses 0 to 3 are set for every plural number of blocks 0 to 3; however, the present invention is not limited to this. For example, it is also possible to set a plurality of column addresses other than 4 for every block 0~3. As described above, the semiconductor memory device according to this modification example has the same operations and effects as those of the third embodiment.

The respective embodiments and modified examples described above are described in order to facilitate the understanding of the present invention, and are not described in order to limit the present invention. Therefore, the elements disclosed in the foregoing embodiments and modifications are intended to include all design changes or equivalents pertaining to the technical field of the present invention. For example, in the above-mentioned third embodiment and modification examples, one example is used to describe the case where the control unit 10 controls the refresh operation interval for every four blocks; however, the present invention is not limited to this. For example, the control unit 10 may also control the interval of refresh operations for every plural blocks other than four.

In addition, in each of the above-mentioned embodiments, one example is used to describe the case where the frequency of access is classified into three (low frequency, medium frequency, and high frequency); however, the present invention is not limited to this. For example, the frequency of access can also be classified into two or more than four.

10: Control Department

20: memory

21: instruction decoder

22: Column control section

23: Row Control Department

24: Memory cell array

100: Oscillator

110: counter

120: comparison table

130: Comparator

140: Timing Generator

150: Sequencer

160: refresh address counter

161: refresh address counter

162: refresh address counter

163: refresh address counter

164: refresh address counter

170: counter

180: refresh skip control section

190: refresh skip

ACCESS: Signal

ACCFREQ: Signal

ACCFREQ (BLOCK): Access frequency (signal)

ACCFREQ (BLK0): Access frequency

ACCFREQ (BLK1): Access frequency

ACCFREQ (BLK2): Access frequency

ACCFREQ (BLK3): Access frequency

CLEN, SAEN: signal

CMDRD: trigger signal

CMDWR: trigger signal

CNT: Signal

REF: refresh signal

REFSKIP: refresh skip signal

RFA: Signal

RFA (BLOCK): signal

RFA BLK0: Signal

RFA BLK1: Signal

RFA BLK2: Signal

RFA BLK3: Signal

RFAINC: Signal

SRCNT: Signal

SRDIV: Signal

SROSC: Oscillation signal

SRREQ: Refresh request signal

SRREQCNT: Signal

SRRST: Signal

SRTRG: refresh trigger signal

WLOFF: Signal

WLON: Signal

FIG. 1 is a block diagram showing a configuration example of the semiconductor memory device according to the first embodiment of the present invention. Fig. 2 shows an example of the configuration of the control unit. FIG. 3 is a timing chart showing the voltage transitions of various signals in the semiconductor memory device of the first embodiment. FIG. 4 is a block diagram showing a configuration example of the control unit in the semiconductor memory device according to the second embodiment of the present invention. FIG. 5 is a timing chart showing the voltage transitions of various signals in the semiconductor memory device of the second embodiment. FIG. 6 is a block diagram showing an example of the configuration of the control unit in the semiconductor memory device according to the third embodiment of the present invention. FIG. 7 is a timing chart showing the voltage transitions of various signals in the semiconductor memory device of the third embodiment. FIG. 8 is a block diagram showing a configuration example of a control unit in a semiconductor memory device according to a modification of the present invention. Figure 9 (a) ~ (c) shows an example of the structure of the comparison table. Figures 10 to 12 are timing diagrams showing the voltage transitions of various signals in the semiconductor memory device of the modified example.

10: Control Department

100: Oscillator

110: counter

120: comparison table

130: Comparator

140: Timing Generator

150: Sequencer

160: refresh address counter

ACCESS: Signal

ACCFREQ: Signal

REF: refresh signal

RFA: Signal

SRCNT: Signal

SRDIV: Signal

SROSC: Oscillation signal

SRRST: Signal

SRTRG: refresh trigger signal

Claims (8)

A semiconductor memory device includes: a control unit that controls the interval of refresh operations of the memory; if the frequency of read or write access requests to the memory within a predetermined period of time is higher, the refresh operation of the memory is controlled The interval becomes shorter; wherein, the control unit controls the interval of the refresh operation separately for each of the plurality of blocks of consecutive column addresses. For example, the semiconductor memory device of claim 1, wherein, if the frequency of read or write access requests to the memory within the predetermined period is higher, the interval at which the control unit controls the refresh request becomes shorter, and the refresh The request is generated at regular intervals in order to perform the refresh operation of the memory. For example, the semiconductor memory device of claim 1, wherein, if the frequency of read or write access requests to the memory within the predetermined period is higher, the control unit controls the number of refresh operations performed in response to the refresh request Increasingly, the refresh request is generated at regular intervals in order to perform the refresh operation of the memory. For example, the semiconductor memory device of claim 1, wherein each of the plurality of blocks respectively includes a refresh address counter, and the refresh address counter specifies the column address of the refresh operation according to the refresh request; wherein, the control The unit controls the execution of the refresh operation corresponding to the column address specified by the refresh address counter corresponding to each block of the plurality of blocks for each block of the plurality of blocks. For example, the semiconductor memory device of claim 1, further comprising: a refresh address counter, which specifies the column address of the refresh operation according to the refresh request; wherein the control unit controls the refresh for each of the plurality of blocks Address counter designation The refresh operation corresponding to the column address is executed. Such as the semiconductor memory device of claim 5, wherein if the column address specified by the refresh address counter is set to the corresponding block, the higher the frequency of the read or write access request, the more at least 1 When any one of the predetermined column addresses is consistent, the control unit executes the refresh operation corresponding to the designated column address. For example, the semiconductor memory device of any one of claims 1 to 3, wherein, every time the predetermined period passes, the control unit controls the frequency of read or write access requests to the memory within the predetermined period The interval between memory refresh operations. For example, the semiconductor memory device of any one of request items 1 to 3, wherein the frequency of read or write access requests performed on the memory is classified into a predetermined number.

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