JPH0227590A - Dynamic memory refreshment control device - Google Patents

Abstract

PURPOSE:To improve the using efficiency of a memory by comparing the row address or column address of a most newly accessed memory address with the address to be refreshed, and stopping a refreshing action when the both addresses correspond. CONSTITUTION:When the refreshing action is required, the address value of a refresh counter (REF CTR) 7 is compared with the row address of the memory address remaining in a memory address register 1 by a comparing circuit 12. When the both addresses correspond, the output of the comparing circuit 12 is significant, the output of an inverter 13 is not significant, the output of an AND circuit 14 is not significant, a timing generation and a memory access control circuit 9 are not activated at all, the refreshing request becomes invalid, and the refreshing action is stopped only at such a time. Thus, the useless action that the element on the same row address is continuously refreshed is evaded, and the memory using efficiency can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device for refresh operation of a dynamic memory.

(Prior Art) FIG. 2 is a block diagram showing the configuration of a conventional dynamic memory refresh operation control device. In the figure, 1 is an address register, 2 is an address row address, 3 is a column address, and 4 is a multiplexer (hereinafter referred to as MPX) that selects the row address and column address, 5 is a timer that generates refresh timing for the dynamic memory, 6 is the output pulse of timer 5, and 7 is a refresh counter (hereinafter referred to as MPX) that holds the refresh address. Below R
8 is a multiplexer (hereinafter referred to as MPX) that switches the address during normal memory access and the address during refresh, 9 is a timing generation and memory access control circuit that generates various timings for memory access. , 10 is a row address and column address switching signal, 11 is REF at refresh time
This is a selection signal for selecting CTR.

Next, the operation will be explained.

When a dynamic memory access request occurs, if no refresh request occurs at this time, the address
The row address 2 of register 1 is passed through MPX4 by signal 10 generated by timing generation circuit 9 and signal 11
The row address is sent to the memory section through the MPX8. Then set column address 3 to MPX4 and 8 in the same way.
is sent to the memory section through. When the output 6 of the timer 5 that requests a refresh operation becomes significant, the REFCTR 7 is counted up, and the control circuit 9 generates a timing signal for the refresh operation and also outputs a selection signal 11.
to the opposite level of normal memory access, and RE
Sends the refresh address held in F CTR7 to the memory section and performs a refresh operation.

(Problem to be Solved by the Invention) Since the conventional dynamic memory refresh operation control device has the configuration and operation described above, it is necessary to perform the refresh operation whenever a prescribed refresh request occurs. Since the refresh operation is performed with normal memory access prohibited, this has been a factor in reducing memory usage efficiency.

The present invention was made under these circumstances, and it is an object of the present invention to provide a dynamic memory refresh control device that can increase memory utilization efficiency.

[Means to solve the problem]

The present invention focuses on the fact that when a dynamic memory is accessed, elements at a row address or column address related to the access are refreshed, and a refresh control device for a dynamic memory is configured as follows.

That is, the device is provided with means for comparing the row address or column address of the most recently accessed memory address with the address of the refresh to be performed from now on, and stopping the refresh operation when the two addresses match.

(Operation) With this configuration, it is possible to eliminate the wasteful operation of continuously refreshing elements at the same row address or column address.

【Example〕

This invention will be explained below with reference to Examples.

FIG. 1 is a block diagram of a "dynamic memory refresh control device" which is an embodiment of the present invention.

In the figure, 12 is a comparison circuit that compares the row address and refresh address and outputs a significant signal when both addresses match; 13 is an inversion circuit that inverts the output of the comparison circuit 12; and 14 is an inversion circuit 13. This is an AND circuit that performs an AND with the timer output 6 that requests a refresh operation.

1 to 11 are the same as the parts with the same symbols in the conventional example shown in FIG.

The operation during normal memory access, which will be explained next, is the same as that of the conventional configuration, so the explanation will be omitted. When a refresh operation becomes necessary, the refresh request signal 6 becomes significant by the timer 5, and the REF
CTR7 is counted up, and the comparison circuit 12 compares the address value of REF CTR7 with the row address 2 of the memory address remaining in memory address register 1 (this value is the value at the time of the most recent memory access). When they are compared and the two addresses do not match, the output of the inverter 13 becomes significant, and this signal and the timer output 6 are ANDed by the AND circuit 14, and the output is YES, 1! Then, the timing generation and memory access control circuit 9 is requested to perform a refresh operation. If the two addresses match, the output of the comparison circuit 12 becomes significant, and the output of the inverter 13 does not become significant.

The output of the AND circuit 14 is not significant, the timing generation and memory access III control circuit 9 is not activated at all, the refresh request is invalidated, and the refresh operation is stopped only at this time.

In this way, if the row address at the time of the most recent memory access matches the address of the refresh counter, it is possible to avoid wasteful operations in which elements at the same row address are continuously refreshed.

Although this embodiment is an example in which a refresh operation is performed on a row-by-row basis, it goes without saying that the present invention can be applied to a system where a refresh operation is performed on a column-by-column basis.

(Effects of the Invention) As described above, according to the present invention, memory usage efficiency can be improved by avoiding unnecessary operations such as refreshing elements at the same row address successively.

In particular, when a program runs in a specific range for a long time, interference with memory access due to refresh operations can be significantly reduced, and a drop in efficiency can be avoided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. In the figure, 2 is the row address, 7 is the refresh counter,
9 is a timing generation and memory access control circuit, 1
2 is a comparison circuit. Note that the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] It is characterized by comprising means for comparing the row address or column address of the most recently accessed memory address with the address of the refresh to be performed from now on, and stopping the refresh operation when the two addresses match. Dynamic memory refresh control device.